Lines Matching +full:0 +full:x2000
40 #define CSR_RING_ID 0x0008
44 #define CSR_RING_ID_BUF 0x000c
45 #define CSR_PBM_COAL 0x0014
46 #define CSR_PBM_CTICK0 0x0018
47 #define CSR_PBM_CTICK1 0x001c
48 #define CSR_PBM_CTICK2 0x0020
49 #define CSR_PBM_CTICK3 0x0024
50 #define CSR_THRESHOLD0_SET1 0x0030
51 #define CSR_THRESHOLD1_SET1 0x0034
52 #define CSR_RING_NE_INT_MODE 0x017c
53 #define CSR_RING_CONFIG 0x006c
54 #define CSR_RING_WR_BASE 0x0070
57 #define INC_DEC_CMD_ADDR 0x002c
59 #define BUF_LEN_CODE_2K 0x5000
66 #define EMPTY_SLOT ~0ULL
72 #define RING_BUFNUM_MASK GENMASK(5, 0)
78 #define RINGADDRH_POS 0
88 #define RECOMTIMEOUTH_POS 0
96 #define MAC_OFFSET 0x30
97 #define OFFSET_4 0x04
98 #define OFFSET_8 0x08
100 #define BLOCK_ETH_CSR_OFFSET 0x2000
101 #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000
102 #define BLOCK_ETH_RING_IF_OFFSET 0x9000
103 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000
104 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
105 #define BLOCK_ETH_MAC_OFFSET 0x0000
106 #define BLOCK_ETH_STATS_OFFSET 0x0000
107 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
109 #define CLKEN_ADDR 0xc208
110 #define SRST_ADDR 0xc200
112 #define MAC_ADDR_REG_OFFSET 0x00
113 #define MAC_COMMAND_REG_OFFSET 0x04
114 #define MAC_WRITE_REG_OFFSET 0x08
115 #define MAC_READ_REG_OFFSET 0x0c
116 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
118 #define STAT_ADDR_REG_OFFSET 0x14
119 #define STAT_COMMAND_REG_OFFSET 0x18
120 #define STAT_WRITE_REG_OFFSET 0x1c
121 #define STAT_READ_REG_OFFSET 0x20
122 #define STAT_COMMAND_DONE_REG_OFFSET 0x24
124 #define PCS_ADDR_REG_OFFSET 0x00
125 #define PCS_COMMAND_REG_OFFSET 0x04
126 #define PCS_WRITE_REG_OFFSET 0x08
127 #define PCS_READ_REG_OFFSET 0x0c
128 #define PCS_COMMAND_DONE_REG_OFFSET 0x10
130 #define MII_MGMT_CONFIG_ADDR 0x20
131 #define MII_MGMT_COMMAND_ADDR 0x24
132 #define MII_MGMT_ADDRESS_ADDR 0x28
133 #define MII_MGMT_CONTROL_ADDR 0x2c
134 #define MII_MGMT_STATUS_ADDR 0x30
135 #define MII_MGMT_INDICATORS_ADDR 0x34
137 #define BUSY_MASK BIT(0)
138 #define READ_CYCLE_MASK BIT(0)
139 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
141 #define ENET_SPARE_CFG_REG_ADDR 0x0750
142 #define RSIF_CONFIG_REG_ADDR 0x0010
143 #define RSIF_RAM_DBG_REG0_ADDR 0x0048
144 #define RGMII_REG_0_ADDR 0x07e0
145 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
146 #define DEBUG_REG_ADDR 0x0700
147 #define CFG_BYPASS_ADDR 0x0294
148 #define CLE_BYPASS_REG0_0_ADDR 0x0490
149 #define CLE_BYPASS_REG1_0_ADDR 0x0494
151 #define RESUME_TX BIT(0)
153 #define TX_PORT0 BIT(0)
162 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
166 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
167 #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0))
169 #define CSR_ECM_CFG_0_ADDR 0x0220
170 #define CSR_ECM_CFG_1_ADDR 0x0224
171 #define CSR_MULTI_DPF0_ADDR 0x0230
172 #define RXBUF_PAUSE_THRESH 0x0534
173 #define RXBUF_PAUSE_OFF_THRESH 0x0540
174 #define DEF_PAUSE_THRES 0x7d
175 #define DEF_PAUSE_OFF_THRES 0x6d
176 #define DEF_QUANTA 0x8000
177 #define NORM_PAUSE_OPCODE 0x0001
181 #define ICM_CONFIG0_REG_0_ADDR 0x0400
182 #define ICM_CONFIG2_REG_0_ADDR 0x0410
183 #define ECM_CONFIG0_REG_0_ADDR 0x0500
184 #define ECM_CONFIG0_REG_1_ADDR 0x0504
185 #define ICM_ECM_DROP_COUNT_REG0_ADDR 0x0508
186 #define ICM_ECM_DROP_COUNT_REG1_ADDR 0x050c
187 #define RX_DV_GATE_REG_0_ADDR 0x05fc
190 #define RESUME_RX0 BIT(0)
191 #define ENET_CFGSSQMIFPRESET_ADDR 0x14
192 #define ENET_CFGSSQMIWQRESET_ADDR 0x1c
193 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
194 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
195 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
196 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
197 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
198 #define ENET_BLOCK_MEM_RDY_ADDR 0x74
199 #define MAC_CONFIG_1_ADDR 0x00
200 #define MAC_CONFIG_2_ADDR 0x04
201 #define MAX_FRAME_LEN_ADDR 0x10
202 #define INTERFACE_CONTROL_ADDR 0x38
203 #define STATION_ADDR0_ADDR 0x40
204 #define STATION_ADDR1_ADDR 0x44
206 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
208 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
210 #define TX_EN BIT(0)
216 #define FULL_DUPLEX2 BIT(0)
220 #define TR64_ADDR 0x20
221 #define TR127_ADDR 0x21
222 #define TR255_ADDR 0x22
223 #define TR511_ADDR 0x23
224 #define TR1K_ADDR 0x24
225 #define TRMAX_ADDR 0x25
226 #define TRMGV_ADDR 0x26
228 #define RFCS_ADDR 0x29
229 #define RMCA_ADDR 0x2a
230 #define RBCA_ADDR 0x2b
231 #define RXCF_ADDR 0x2c
232 #define RXPF_ADDR 0x2d
233 #define RXUO_ADDR 0x2e
234 #define RALN_ADDR 0x2f
235 #define RFLR_ADDR 0x30
236 #define RCDE_ADDR 0x31
237 #define RCSE_ADDR 0x32
238 #define RUND_ADDR 0x33
239 #define ROVR_ADDR 0x34
240 #define RFRG_ADDR 0x35
241 #define RJBR_ADDR 0x36
242 #define RDRP_ADDR 0x37
244 #define TMCA_ADDR 0x3a
245 #define TBCA_ADDR 0x3b
246 #define TXPF_ADDR 0x3c
247 #define TDFR_ADDR 0x3d
248 #define TEDF_ADDR 0x3e
249 #define TSCL_ADDR 0x3f
250 #define TMCL_ADDR 0x40
251 #define TLCL_ADDR 0x41
252 #define TXCL_ADDR 0x42
253 #define TNCL_ADDR 0x43
254 #define TPFH_ADDR 0x44
255 #define TDRP_ADDR 0x45
256 #define TJBR_ADDR 0x46
257 #define TFCS_ADDR 0x47
258 #define TXCF_ADDR 0x48
259 #define TOVR_ADDR 0x49
260 #define TUND_ADDR 0x4a
261 #define TFRG_ADDR 0x4b
262 #define DUMP_ADDR 0x27
264 #define ECM_DROP_COUNT(src) xgene_get_bits(src, 0, 15)
269 #define USERINFO_POS 0
285 #define DATAADDR_POS 0
295 #define TCPHDR_POS 0
313 #define DATALEN_MASK GENMASK(11, 0)
315 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
317 #define TSO_MSS0_POS 0
371 RING_BUFNUM_REGULAR = 0x0,
372 RING_BUFNUM_BUFPOOL = 0x20,
403 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; in xgene_enet_is_bufpool()
411 return 0; in xgene_enet_get_fpsel()