Lines Matching +full:0 +full:x2000
7 #define ICH_FLASH_GFPREG 0x0000
8 #define ICH_FLASH_HSFSTS 0x0004
9 #define ICH_FLASH_HSFCTL 0x0006
10 #define ICH_FLASH_FADDR 0x0008
11 #define ICH_FLASH_FDATA0 0x0010
12 #define ICH_FLASH_PR0 0x0074
18 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
21 #define ICH_CYCLE_READ 0
25 #define FLASH_GFPREG_BASE_MASK 0x1FFF
33 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
35 #define E1000_ICH_FWSM_FW_VALID 0x00008000
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
39 #define E1000_ICH_MNG_IAMT_MODE 0x2
41 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380
43 #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
46 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
47 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
49 #define E1000_H2ME 0x05B50 /* Host to ME */
50 #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
51 #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
58 #define E1000_ICH_NVM_SIG_WORD 0x13u
59 #define E1000_ICH_NVM_SIG_MASK 0xC000u
60 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0u
61 #define E1000_ICH_NVM_SIG_VALUE 0x80u
66 #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
71 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
72 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
74 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
75 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
76 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
78 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
79 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
80 #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
82 #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
83 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
84 #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
85 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
86 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
87 #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
88 #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
90 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
91 #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
93 #define K1_ENTRY_LATENCY 0
96 #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
97 #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
98 #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000
99 #define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000
103 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
104 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
112 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
113 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
114 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
128 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
129 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
132 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
133 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
134 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
138 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
139 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
157 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
160 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
164 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
168 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
169 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
170 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
171 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
172 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
173 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
175 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400
177 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800
178 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
182 #define HV_SMB_ADDR_MASK 0x007F
183 #define HV_SMB_ADDR_PEC_EN 0x0200
184 #define HV_SMB_ADDR_VALID 0x0080
185 #define HV_SMB_ADDR_FREQ_MASK 0x1100
190 #define E1000_STRAP 0x0000C
191 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
193 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
198 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
199 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
200 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
204 #define HV_KMRN_MDIO_SLOW 0x0400
208 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
213 #define HV_PM_CTRL_K1_CLK_REQ 0x200
214 #define HV_PM_CTRL_K1_ENABLE 0x4000
217 #define I217_PLL_CLOCK_GATE_MASK 0x07FF
223 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
228 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800
232 #define I82579_LPI_CTRL_100_ENABLE 0x2000
233 #define I82579_LPI_CTRL_1000_ENABLE 0x4000
234 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
235 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
238 #define I82579_EMI_ADDR 0x10
239 #define I82579_EMI_DATA 0x11
240 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
241 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
242 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
243 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
244 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */
245 #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
246 #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
247 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
248 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
249 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
253 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
254 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
255 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
256 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
257 #define I217_RX_CONFIG 0xB20C /* Receive configuration */
259 #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
260 #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
264 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
266 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
268 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
270 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
273 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
276 #define E1000_LTRV 0x000F8
284 #define E1000_PCI_LTR_CAP_LPT 0xA8