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/linux-3.3/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c24 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
28 #define PHY_CONTROL 0x00 /* Control Register */
29 #define PHY_STATUS 0x01 /* Status Regiser */
30 #define PHY_ID1 0x02 /* Phy Id Register (word 1) */
31 #define PHY_ID2 0x03 /* Phy Id Register (word 2) */
32 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
33 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
34 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Register */
35 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
36 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
[all …]
/linux-3.3/drivers/net/ethernet/smsc/
Dsmc9194.h45 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
58 . yyyy yyyy = 0x33, for identification purposes.
62 /* BANK 0 */
64 #define TCR 0 /* transmit control register */
65 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
66 #define TCR_FDUPLX 0x0800 /* receive packets sent out */
67 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
68 #define TCR_MON_CNS 0x0400 /* monitors the carrier status */
69 #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
71 #define TCR_CLEAR 0 /* do NOTHING */
[all …]
/linux-3.3/drivers/staging/comedi/drivers/
Dni_stc.h34 #define _bit15 0x8000
35 #define _bit14 0x4000
36 #define _bit13 0x2000
37 #define _bit12 0x1000
38 #define _bit11 0x0800
39 #define _bit10 0x0400
40 #define _bit9 0x0200
41 #define _bit8 0x0100
42 #define _bit7 0x0080
43 #define _bit6 0x0040
[all …]
/linux-3.3/drivers/staging/sbe-2t3e3/
Dmaps.c18 { 0x0000, 0x0080 }, /* 0 - Port Control Register A (PCRA) */
19 { 0x0004, 0x0084 }, /* 1 - Port Control Register B (PCRB) */
20 { 0x0008, 0x0088 }, /* 2 - LCV Count Register (PLCR) */
21 { 0x000c, 0x008c }, /* 3 - LCV Threshold register (PLTR) */
22 { 0x0010, 0x0090 }, /* 4 - Payload Fill Register (PPFR) */
23 { 0x0200, 0x0200 }, /* 5 - Board ID / FPGA Programming Status Register */
24 { 0x0204, 0x0204 }, /* 6 - FPGA Version Register */
25 { 0x0800, 0x1000 }, /* 7 - Framer Registers Base Address */
26 { 0x2000, 0x2000 }, /* 8 - Serial Chip Select Register */
27 { 0x2004, 0x2004 }, /* 9 - Static Reset Register */
[all …]
/linux-3.3/arch/blackfin/include/asm/
Dgptimers.h49 #define TIMER_GROUP1 0
59 #define TIMER0bit 0x0001 /* 0001b */
60 #define TIMER1bit 0x0002 /* 0010b */
61 #define TIMER2bit 0x0004 /* 0100b */
62 #define TIMER3bit 0x0008
63 #define TIMER4bit 0x0010
64 #define TIMER5bit 0x0020
65 #define TIMER6bit 0x0040
66 #define TIMER7bit 0x0080
67 #define TIMER8bit 0x0100
[all …]
/linux-3.3/drivers/media/common/tuners/
Dmc44s803_priv.h28 SPI or I2C Address : 0xc0-0xc6
42 0A | LNA AGC
43 0B | Data Register Address
44 0C | Regulator Test
45 0D | VCO Test
46 0E | LNA Gain/Input Power
47 0F | ID Bits
55 #define MC44S803_REG_POWER 0
65 #define MC44S803_REG_LNAAGC 0x0A
66 #define MC44S803_REG_DATAREG 0x0B
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dadder875-redboot.dts28 #size-cells = <0>;
30 PowerPC,875@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
47 reg = <0 0x01000000>;
55 reg = <0xfa200100 0x40>;
58 0 0 0xfe000000 0x00800000
59 2 0 0xfa100000 0x00008000
[all …]
Dadder875-uboot.dts28 #size-cells = <0>;
30 PowerPC,875@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
47 reg = <0 0x01000000>;
55 reg = <0xff000100 0x40>;
58 0 0 0xfe000000 0x01000000
61 flash@0,0 {
[all …]
/linux-3.3/arch/m68k/include/asm/
Dprocessor.h29 __asm__ __volatile__(".word 0x4e68" : "=a" (usp)); in rdusp()
42 __asm__ __volatile__(".word 0x4e60" : : "a" (a0) ); in wrusp()
52 #define TASK_SIZE (0xC0000000UL)
54 #define TASK_SIZE (0x0E000000UL)
56 #define TASK_SIZE (0xF0000000UL)
59 #define TASK_SIZE (0xFFFFFFFFUL)
72 #define TASK_UNMAPPED_BASE 0x60000000UL
74 #define TASK_UNMAPPED_BASE 0x0A000000UL
76 #define TASK_UNMAPPED_BASE 0xC0000000UL
80 #define TASK_UNMAPPED_BASE 0
[all …]
/linux-3.3/drivers/mtd/nand/
Ddenali.h22 #define DEVICE_RESET 0x0
23 #define DEVICE_RESET__BANK0 0x0001
24 #define DEVICE_RESET__BANK1 0x0002
25 #define DEVICE_RESET__BANK2 0x0004
26 #define DEVICE_RESET__BANK3 0x0008
28 #define TRANSFER_SPARE_REG 0x10
29 #define TRANSFER_SPARE_REG__FLAG 0x0001
31 #define LOAD_WAIT_CNT 0x20
32 #define LOAD_WAIT_CNT__VALUE 0xffff
34 #define PROGRAM_WAIT_CNT 0x30
[all …]
/linux-3.3/drivers/net/ethernet/sis/
Dsis900.h18 #define SIS900_TOTAL_SIZE 0x100
22 cr=0x0, //Command Register
23 cfg=0x4, //Configuration Register
24 mear=0x8, //EEPROM Access Register
25 ptscr=0xc, //PCI Test Control Register
26 isr=0x10, //Interrupt Status Register
27 imr=0x14, //Interrupt Mask Register
28 ier=0x18, //Interrupt Enable Register
29 epar=0x18, //Enhanced PHY Access Register
30 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux-3.3/drivers/net/ethernet/i825xx/
Dsun3_82586.h22 #define IEOB_NORSET 0x80 /* don't reset the board */
23 #define IEOB_ONAIR 0x40 /* put us on the air */
24 #define IEOB_ATTEN 0x20 /* attention! */
25 #define IEOB_IENAB 0x10 /* interrupt enable */
26 #define IEOB_XXXXX 0x08 /* free bit */
27 #define IEOB_XCVRL2 0x04 /* level 2 transceiver? */
28 #define IEOB_BUSERR 0x02 /* bus error */
29 #define IEOB_INT 0x01 /* interrupt */
32 #define IE_OBIO 0xc0000
38 #define SCP_DEFAULT_ADDRESS 0xfffff4
[all …]
Dni52.h15 #define NI52_RESET 0 /* writing to this address, resets the i82586 */
24 #define NI52_MAGICVAL1 0x00 /* magic-values for ni5210 card */
25 #define NI52_MAGICVAL2 0x55
30 #define SCP_DEFAULT_ADDRESS 0xfffff4
40 u8 sysbus; /* 0=16Bit,1=8Bit */
79 #define RUC_MASK 0x0070 /* mask for RU commands */
80 #define RUC_NOP 0x0000 /* NOP-command */
81 #define RUC_START 0x0010 /* start RU */
82 #define RUC_RESUME 0x0020 /* resume RU after suspend */
83 #define RUC_SUSPEND 0x0030 /* suspend RU */
[all …]
/linux-3.3/fs/jfs/
Djfs_txnmgr.h75 #define COMMIT_SYNC 0x0001 /* synchronous commit */
76 #define COMMIT_FORCE 0x0002 /* force pageout at end of commit */
77 #define COMMIT_FLUSH 0x0004 /* init flush at end of commit */
78 #define COMMIT_MAP 0x00f0
79 #define COMMIT_PMAP 0x0010 /* update pmap */
80 #define COMMIT_WMAP 0x0020 /* update wmap */
81 #define COMMIT_PWMAP 0x0040 /* update pwmap */
82 #define COMMIT_FREE 0x0f00
83 #define COMMIT_DELETE 0x0100 /* inode delete */
84 #define COMMIT_TRUNCATE 0x0200 /* file truncation */
[all …]
/linux-3.3/drivers/scsi/
Dqlogicpti.h10 #define SBUS_CFG1 0x006UL
11 #define SBUS_CTRL 0x008UL
12 #define SBUS_STAT 0x00aUL
13 #define SBUS_SEMAPHORE 0x00cUL
14 #define CMD_DMA_CTRL 0x022UL
15 #define DATA_DMA_CTRL 0x042UL
16 #define MBOX0 0x080UL
17 #define MBOX1 0x082UL
18 #define MBOX2 0x084UL
19 #define MBOX3 0x086UL
[all …]
/linux-3.3/include/linux/
Dmdio.h61 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
62 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
63 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
64 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
65 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
66 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
72 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
76 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
83 #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
86 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
[all …]
/linux-3.3/arch/mips/mti-malta/
Dmalta-init.c74 int i, index=0; in prom_getenv()
79 if(strncmp(envname, prom_envp(index), i) == 0) { in prom_getenv()
90 if (c >= '0' && c <= '9') in str2hexnum()
91 return c - '0'; in str2hexnum()
94 return 0; /* foo */ in str2hexnum()
101 for (i = 0; i < 6; i++) { in str2eaddr()
126 for (i=0; i<5; i++) in get_ethernet_addr()
131 return 0; in get_ethernet_addr()
138 int baud = 0; in console_config()
139 char parity = '\0', bits = '\0', flow = '\0'; in console_config()
[all …]
/linux-3.3/arch/arm/mach-sa1100/include/mach/
DSA-1101.h31 * It then appears from 0xf4000000.
34 #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000)
35 #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE)
43 #define C 0
51 #define __SHMEM_CONTROL0 0x00000000
52 #define __SYSTEM_CONTROL1 0x00000400
53 #define __ARBITER 0x00020000
54 #define __SYSTEM_CONTROL2 0x00040000
55 #define __SYSTEM_CONTROL3 0x00060000
56 #define __PARALLEL_PORT 0x00080000
[all …]
/linux-3.3/sound/soc/codecs/
Dad1980.h14 #define ADC 0x0001
15 #define DAC 0x0002
16 #define ANL 0x0004
17 #define REF 0x0008
18 #define PR0 0x0100
19 #define PR1 0x0200
20 #define PR2 0x0400
21 #define PR3 0x0800
22 #define PR4 0x1000
23 #define PR5 0x2000
[all …]
/linux-3.3/drivers/isdn/hisax/
Dhfc_sx.h19 #define HFCSX_BTRANS_THRESMASK 0x00
23 #define HFCSX_C_I 0x02
24 #define HFCSX_TRxR 0x03
25 #define HFCSX_MON1_D 0x0A
26 #define HFCSX_MON2_D 0x0B
31 #define HFCSX_B1_SSL 0x20
32 #define HFCSX_B2_SSL 0x21
33 #define HFCSX_AUX1_SSL 0x22
34 #define HFCSX_AUX2_SSL 0x23
35 #define HFCSX_B1_RSL 0x24
[all …]
/linux-3.3/drivers/s390/char/
Dsclp.h20 #define EVTYP_OPCMD 0x01
21 #define EVTYP_MSG 0x02
22 #define EVTYP_STATECHANGE 0x08
23 #define EVTYP_PMSGCMD 0x09
24 #define EVTYP_CNTLPROGOPCMD 0x20
25 #define EVTYP_CNTLPROGIDENT 0x0B
26 #define EVTYP_SIGQUIESCE 0x1D
27 #define EVTYP_VT220MSG 0x1A
28 #define EVTYP_CONFMGMDATA 0x04
29 #define EVTYP_SDIAS 0x1C
[all …]
/linux-3.3/arch/sh/include/mach-dreamcast/mach/
Dpci.h16 #define GAPSPCI_REGS 0x01001400
17 #define GAPSPCI_DMA_BASE 0x01840000
19 #define GAPSPCI_BBA_CONFIG 0x01001600
20 #define GAPSPCI_BBA_CONFIG_SIZE 0x2000
/linux-3.3/include/asm-generic/
Dpoll.h5 #define POLLIN 0x0001
6 #define POLLPRI 0x0002
7 #define POLLOUT 0x0004
8 #define POLLERR 0x0008
9 #define POLLHUP 0x0010
10 #define POLLNVAL 0x0020
13 #define POLLRDNORM 0x0040
14 #define POLLRDBAND 0x0080
16 #define POLLWRNORM 0x0100
19 #define POLLWRBAND 0x0200
[all …]
/linux-3.3/include/linux/mfd/wm8350/
Dpmic.h24 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
25 #define WM8350_CSA_FLASH_CONTROL 0xAD
26 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
27 #define WM8350_CSB_FLASH_CONTROL 0xAF
28 #define WM8350_DCDC_LDO_REQUESTED 0xB0
29 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
30 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
31 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
32 #define WM8350_DCDC1_CONTROL 0xB4
33 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/linux-3.3/arch/microblaze/platform/generic/
Dsystem.dts39 reg = < 0x90000000 0x10000000 >;
47 linux,stdout-path = "/plb@0/serial@84000000";
51 #cpus = <0x1>;
52 #size-cells = <0>;
53 microblaze_0: cpu@0 {
56 d-cache-baseaddr = <0x90000000>;
57 d-cache-highaddr = <0x9fffffff>;
58 d-cache-line-size = <0x10>;
59 d-cache-size = <0x2000>;
61 i-cache-baseaddr = <0x90000000>;
[all …]

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