Lines Matching +full:0 +full:x2000
45 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
58 . yyyy yyyy = 0x33, for identification purposes.
62 /* BANK 0 */
64 #define TCR 0 /* transmit control register */
65 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
66 #define TCR_FDUPLX 0x0800 /* receive packets sent out */
67 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
68 #define TCR_MON_CNS 0x0400 /* monitors the carrier status */
69 #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
71 #define TCR_CLEAR 0 /* do NOTHING */
78 #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
81 #define RCR_SOFTRESET 0x8000 /* resets the chip */
82 #define RCR_STRIP_CRC 0x200 /* strips CRC */
83 #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
84 #define RCR_ALMUL 0x4 /* receive all multicast packets */
85 #define RCR_PROMISC 0x2 /* enable promiscuous mode */
89 #define RCR_CLEAR 0x0 /* set it to a base state */
97 #define CONFIG 0
98 #define CFG_AUI_SELECT 0x100
105 #define CTL_POWERDOWN 0x2000
106 #define CTL_LE_ENABLE 0x80
107 #define CTL_CR_ENABLE 0x40
108 #define CTL_TE_ENABLE 0x0020
109 #define CTL_AUTO_RELEASE 0x0800
110 #define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
113 #define MMU_CMD 0
115 #define MC_NOP 0
116 #define MC_ALLOC 0x20 /* or with number of 256 byte packets */
117 #define MC_RESET 0x40
118 #define MC_REMOVE 0x60 /* remove the current rx packet */
119 #define MC_RELEASE 0x80 /* remove and release the current rx packet */
120 #define MC_FREEPKT 0xA0 /* Release packet in PNR register */
121 #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
126 #define FP_RXEMPTY 0x8000
127 #define FP_TXEMPTY 0x80
130 #define PTR_READ 0x2000
131 #define PTR_RCV 0x8000
132 #define PTR_AUTOINC 0x4000
133 #define PTR_AUTO_INC 0x0040
140 #define IM_RCV_INT 0x1
141 #define IM_TX_INT 0x2
142 #define IM_TX_EMPTY_INT 0x4
143 #define IM_ALLOC_INT 0x8
144 #define IM_RX_OVRN_INT 0x10
145 #define IM_EPH_INT 0x20
146 #define IM_ERCV_INT 0x40 /* not on SMC9192 */
149 #define MULTICAST1 0
179 #define TS_SUCCESS 0x0001
180 #define TS_LOSTCAR 0x0400
181 #define TS_LATCOL 0x0200
182 #define TS_16COL 0x0010
187 #define RS_ALGNERR 0x8000
188 #define RS_BADCRC 0x2000
189 #define RS_ODDFRAME 0x1000
190 #define RS_TOOLONG 0x0800
191 #define RS_TOOSHORT 0x0400
192 #define RS_MULTICAST 0x0001
202 /* select a register bank, 0 to 3 */