Lines Matching +full:0 +full:x2000
31 * It then appears from 0xf4000000.
34 #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000)
35 #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE)
43 #define C 0
51 #define __SHMEM_CONTROL0 0x00000000
52 #define __SYSTEM_CONTROL1 0x00000400
53 #define __ARBITER 0x00020000
54 #define __SYSTEM_CONTROL2 0x00040000
55 #define __SYSTEM_CONTROL3 0x00060000
56 #define __PARALLEL_PORT 0x00080000
57 #define __VIDMEM_CONTROL 0x00100000
58 #define __UPDATE_FIFO 0x00120000
59 #define __SHMEM_CONTROL1 0x00140000
60 #define __INTERRUPT_CONTROL 0x00160000
61 #define __USB_CONTROL 0x00180000
62 #define __TRACK_INTERFACE 0x001a0000
63 #define __MOUSE_INTERFACE 0x001b0000
64 #define __KEYPAD_INTERFACE 0x001c0000
65 #define __PCMCIA_INTERFACE 0x001e0000
66 #define __VGA_CONTROL 0x00200000
67 #define __GPIO_INTERFACE 0x00300000
84 #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
85 #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
86 #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */
93 #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */
94 #define SKCR_BCLKEn 0x0002 /* Enables BCLK */
95 #define SKCR_Sleep 0x0004 /* Sleep Mode */
96 #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */
97 #define SKCR_VCOON 0x0010 /* VCO bias */
98 #define SKCR_ScanTestEn 0x0020 /* Enables scan test */
99 #define SKCR_ClockTestEn 0x0040 /* Enables clock test */
101 #define SMCR_DCAC Fld(2,0) /* Number of column address bits */
103 #define SMCR_ArbiterBias 0x0008 /* favor video or USB */
111 #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
119 #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \
134 #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */
135 #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */
136 #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */
143 #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */
144 #define VMCCR_Config 0x0001 /* DRAM size */
166 #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */
167 #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */
168 #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */
169 #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */
179 #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */
181 #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */
194 #define _SKPCR _SA1101(0x00000400)
195 #define _SKCDR _SA1101(0x00040000)
196 #define _DACDR1 _SA1101(0x00060000)
197 #define _DACDR2 _SA1101(0x00060400)
205 #define SKPCR_UCLKEn 0x01 /* USB Enable */
206 #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */
207 #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */
208 #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */
209 #define SKPCR_PICLKEn 0x10 /* parallel port Enable */
210 #define SKPCR_DCLKEn 0x20 /* DACs Enable */
211 #define SKPCR_nKPADEn 0x40 /* Multiplexer */
213 #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */
225 #define DACDR_DACCount Fld(8,0) /* Count value */
261 #define _IEEE_Config _IEEE( 0x0000 )
262 #define _IEEE_Control _IEEE( 0x0400 )
263 #define _IEEE_Data _IEEE( 0x4000 )
264 #define _IEEE_Addr _IEEE( 0x0800 )
265 #define _IEEE_Status _IEEE( 0x0c00 )
266 #define _IEEE_IntStatus _IEEE( 0x1000 )
267 #define _IEEE_FifoLevels _IEEE( 0x1400 )
268 #define _IEEE_InitTime _IEEE( 0x1800 )
269 #define _IEEE_TimerStatus _IEEE( 0x1c00 )
270 #define _IEEE_FifoReset _IEEE( 0x2000 )
271 #define _IEEE_ReloadValue _IEEE( 0x3c00 )
272 #define _IEEE_TestControl _IEEE( 0x2400 )
273 #define _IEEE_TestDataIn _IEEE( 0x2800 )
274 #define _IEEE_TestDataInEn _IEEE( 0x2c00 )
275 #define _IEEE_TestCtrlIn _IEEE( 0x3000 )
276 #define _IEEE_TestCtrlInEn _IEEE( 0x3400 )
277 #define _IEEE_TestDataStat _IEEE( 0x3800 )
300 #define IEEE_Config_M Fld(3,0) /* Mode select */
301 #define IEEE_Config_D 0x04 /* FIFO access enable */
302 #define IEEE_Config_B 0x08 /* 9-bit word enable */
303 #define IEEE_Config_T 0x10 /* Data transfer enable */
304 #define IEEE_Config_A 0x20 /* Data transfer direction */
305 #define IEEE_Config_E 0x40 /* Timer enable */
306 #define IEEE_Control_A 0x08 /* AutoFd output */
307 #define IEEE_Control_E 0x04 /* Selectin output */
308 #define IEEE_Control_T 0x02 /* Strobe output */
309 #define IEEE_Control_I 0x01 /* Port init output */
312 #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */
313 #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */
314 #define IEEE_Status_A 0x0100 /* nAutoFd port output status */
315 #define IEEE_Status_E 0x0080 /* nSelectIn port output status */
316 #define IEEE_Status_T 0x0040 /* nStrobe port output status */
317 #define IEEE_Status_I 0x0020 /* nInit port output status */
318 #define IEEE_Status_B 0x0010 /* Busy port inout status */
319 #define IEEE_Status_S 0x0008 /* Select port input status */
320 #define IEEE_Status_K 0x0004 /* nAck port input status */
321 #define IEEE_Status_F 0x0002 /* nFault port input status */
322 #define IEEE_Status_R 0x0001 /* pError port input status */
324 #define IEEE_IntStatus_IntReqDat 0x0100
325 #define IEEE_IntStatus_IntReqEmp 0x0080
326 #define IEEE_IntStatus_IntReqInt 0x0040
327 #define IEEE_IntStatus_IntReqRav 0x0020
328 #define IEEE_IntStatus_IntReqTim 0x0010
329 #define IEEE_IntStatus_RevAddrComp 0x0008
330 #define IEEE_IntStatus_RevDataComp 0x0004
331 #define IEEE_IntStatus_FwdAddrComp 0x0002
332 #define IEEE_IntStatus_FwdDataComp 0x0001
335 #define IEEE_InitTime_TimValInit Fld(22,0)
336 #define IEEE_TimerStatus_TimValStat Fld(22,0)
337 #define IEEE_ReloadValue_Reload Fld(4,0)
339 #define IEEE_TestControl_RegClk 0x04
341 #define IEEE_TestControl_TimerTestModeEn 0x01
342 #define IEEE_TestCtrlIn_PError 0x10
343 #define IEEE_TestCtrlIn_nFault 0x08
344 #define IEEE_TestCtrlIn_nAck 0x04
345 #define IEEE_TestCtrlIn_PSel 0x02
346 #define IEEE_TestCtrlIn_Busy 0x01
355 * VgaTiming0 VGA Timing Register 0
371 #define _VideoControl _VGA( 0x0000 )
372 #define _VgaTiming0 _VGA( 0x0400 )
373 #define _VgaTiming1 _VGA( 0x0800 )
374 #define _VgaTiming2 _VGA( 0x0c00 )
375 #define _VgaTiming3 _VGA( 0x1000 )
376 #define _VgaBorder _VGA( 0x1400 )
377 #define _VgaDBAR _VGA( 0x1800 )
378 #define _VgaDCAR _VGA( 0x1c00 )
379 #define _VgaStatus _VGA( 0x2000 )
380 #define _VgaInterruptMask _VGA( 0x2400 )
381 #define _VgaPalette _VGA( 0x40000 )
382 #define _DacControl _VGA( 0x3000 )
383 #define _VgaTest _VGA( 0x2c00 )
400 #define VideoControl_VgaEn 0x00000000
401 #define VideoControl_BGR 0x00000001
413 #define VgaTiming1_LPS Fld(10,0)
418 #define VgaTiming2_IVS 0x01
419 #define VgaTiming2_IHS 0x02
420 #define VgaTiming2_CVS 0x04
421 #define VgaTiming2_CHS 0x08
423 #define VgaTiming3_HBS Fld(8,0)
428 #define VgaBorder_BCOL Fld(24,0)
430 #define VgaStatus_VFUF 0x01
431 #define VgaStatus_VNext 0x02
432 #define VgaStatus_VComp 0x04
434 #define VgaInterruptMask_VFUFMask 0x00
435 #define VgaInterruptMask_VNextMask 0x01
436 #define VgaInterruptMask_VCompMask 0x02
438 #define VgaPalette_R Fld(8,0)
442 #define DacControl_DACON 0x0001
443 #define DacControl_COMPON 0x0002
444 #define DacControl_PEDON 0x0004
449 #define VgaTest_TDAC 0x00
451 #define VgaTest_DACTESTDAC 0x10
494 #define _Revision _USB( 0x0000 )
495 #define _Control _USB( 0x0888 )
496 #define _CommandStatus _USB( 0x0c00 )
497 #define _InterruptStatus _USB( 0x1000 )
498 #define _InterruptEnable _USB( 0x1400 )
499 #define _HCCA _USB( 0x1800 )
500 #define _PeriodCurrentED _USB( 0x1c00 )
501 #define _ControlHeadED _USB( 0x2000 )
502 #define _BulkHeadED _USB( 0x2800 )
503 #define _BulkCurrentED _USB( 0x2c00 )
504 #define _DoneHead _USB( 0x3000 )
505 #define _FmInterval _USB( 0x3400 )
506 #define _FmRemaining _USB( 0x3800 )
507 #define _FmNumber _USB( 0x3c00 )
508 #define _PeriodicStart _USB( 0x4000 )
509 #define _LSThreshold _USB( 0x4400 )
510 #define _RhDescriptorA _USB( 0x4800 )
511 #define _RhDescriptorB _USB( 0x4c00 )
512 #define _RhStatus _USB( 0x5000 )
513 #define _RhPortStatus _USB( 0x5400 )
514 #define _USBStatus _USB( 0x11800 )
515 #define _USBReset _USB( 0x11c00 )
517 #define _USTAR _USB( 0x10400 )
518 #define _USWER _USB( 0x10800 )
519 #define _USRFR _USB( 0x10c00 )
520 #define _USNFR _USB( 0x11000 )
521 #define _USTCSR _USB( 0x11400 )
522 #define _USSR _USB( 0x11800 )
562 #define USBReset_ForceIfReset 0x01
563 #define USBReset_ForceHcReset 0x02
564 #define USBReset_ClkGenReset 0x04
566 #define USTCR_RdBstCntrl Fld(3,0)
574 #define USSR_nAppMDEmpty 0x01
575 #define USSR_nAppMDFirst 0x02
576 #define USSR_nAppMDLast 0x04
577 #define USSR_nAppMDFull 0x08
578 #define USSR_nAppMAFull 0x10
579 #define USSR_XferReq 0x20
580 #define USSR_XferEnd 0x40
589 * INTTEST0 Test register 0
591 * INTENABLE0 Interrupt Enable register 0
593 * INTPOL0 Interrupt Polarity selection 0
596 * INTSTATCLR0 Interrupt Status 0
598 * INTSET0 Interrupt Set 0
604 #define _INTTEST0 _INT( 0x1000 )
605 #define _INTTEST1 _INT( 0x1400 )
606 #define _INTENABLE0 _INT( 0x2000 )
607 #define _INTENABLE1 _INT( 0x2400 )
608 #define _INTPOL0 _INT( 0x3000 )
609 #define _INTPOL1 _INT( 0x3400 )
610 #define _INTTSTSEL _INT( 0x5000 )
611 #define _INTSTATCLR0 _INT( 0x6000 )
612 #define _INTSTATCLR1 _INT( 0x6400 )
613 #define _INTSET0 _INT( 0x7000 )
614 #define _INTSET1 _INT( 0x7400 )
659 #define _KBDCR _KBD( 0x0000 )
660 #define _KBDSTAT _KBD( 0x0400 )
661 #define _KBDDATA _KBD( 0x0800 )
662 #define _KBDCLKDIV _KBD( 0x0c00 )
663 #define _KBDPRECNT _KBD( 0x1000 )
664 #define _KBDTEST1 _KBD( 0x2000 )
665 #define _KBDTEST2 _KBD( 0x2400 )
666 #define _KBDTEST3 _KBD( 0x2800 )
667 #define _KBDTEST4 _KBD( 0x2c00 )
668 #define _MSECR _MSE( 0x0000 )
669 #define _MSESTAT _MSE( 0x0400 )
670 #define _MSEDATA _MSE( 0x0800 )
671 #define _MSECLKDIV _MSE( 0x0c00 )
672 #define _MSEPRECNT _MSE( 0x1000 )
673 #define _MSETEST1 _MSE( 0x2000 )
674 #define _MSETEST2 _MSE( 0x2400 )
675 #define _MSETEST3 _MSE( 0x2800 )
676 #define _MSETEST4 _MSE( 0x2c00 )
700 #define KBDCR_ENA 0x08
701 #define KBDCR_FKD 0x02
702 #define KBDCR_FKC 0x01
704 #define KBDSTAT_TXE 0x80
705 #define KBDSTAT_TXB 0x40
706 #define KBDSTAT_RXF 0x20
707 #define KBDSTAT_RXB 0x10
708 #define KBDSTAT_ENA 0x08
709 #define KBDSTAT_RXP 0x04
710 #define KBDSTAT_KBD 0x02
711 #define KBDSTAT_KBC 0x01
713 #define KBDCLKDIV_DivVal Fld(4,0)
715 #define MSECR_ENA 0x08
716 #define MSECR_FKD 0x02
717 #define MSECR_FKC 0x01
719 #define MSESTAT_TXE 0x80
720 #define MSESTAT_TXB 0x40
721 #define MSESTAT_RXF 0x20
722 #define MSESTAT_RXB 0x10
723 #define MSESTAT_ENA 0x08
724 #define MSESTAT_RXP 0x04
725 #define MSESTAT_MSD 0x02
726 #define MSESTAT_MSC 0x01
728 #define MSECLKDIV_DivVal Fld(4,0)
730 #define KBDTEST1_CD 0x80
731 #define KBDTEST1_RC1 0x40
732 #define KBDTEST1_MC 0x20
734 #define KBDTEST1_T2 0x40
735 #define KBDTEST1_T1 0x20
736 #define KBDTEST1_T0 0x10
737 #define KBDTEST2_TICBnRES 0x08
738 #define KBDTEST2_RKC 0x04
739 #define KBDTEST2_RKD 0x02
740 #define KBDTEST2_SEL 0x01
741 #define KBDTEST3_ms_16 0x80
742 #define KBDTEST3_us_64 0x40
743 #define KBDTEST3_us_16 0x20
744 #define KBDTEST3_DIV8 0x10
745 #define KBDTEST3_DIn 0x08
746 #define KBDTEST3_CIn 0x04
747 #define KBDTEST3_KD 0x02
748 #define KBDTEST3_KC 0x01
749 #define KBDTEST4_BC12 0x80
750 #define KBDTEST4_BC11 0x40
751 #define KBDTEST4_TRES 0x20
752 #define KBDTEST4_CLKOE 0x10
753 #define KBDTEST4_CRES 0x08
754 #define KBDTEST4_RXB 0x04
755 #define KBDTEST4_TXB 0x02
756 #define KBDTEST4_SRX 0x01
758 #define MSETEST1_CD 0x80
759 #define MSETEST1_RC1 0x40
760 #define MSETEST1_MC 0x20
762 #define MSETEST1_T2 0x40
763 #define MSETEST1_T1 0x20
764 #define MSETEST1_T0 0x10
765 #define MSETEST2_TICBnRES 0x08
766 #define MSETEST2_RKC 0x04
767 #define MSETEST2_RKD 0x02
768 #define MSETEST2_SEL 0x01
769 #define MSETEST3_ms_16 0x80
770 #define MSETEST3_us_64 0x40
771 #define MSETEST3_us_16 0x20
772 #define MSETEST3_DIV8 0x10
773 #define MSETEST3_DIn 0x08
774 #define MSETEST3_CIn 0x04
775 #define MSETEST3_KD 0x02
776 #define MSETEST3_KC 0x01
777 #define MSETEST4_BC12 0x80
778 #define MSETEST4_BC11 0x40
779 #define MSETEST4_TRES 0x20
780 #define MSETEST4_CLKOE 0x10
781 #define MSETEST4_CRES 0x08
782 #define MSETEST4_RXB 0x04
783 #define MSETEST4_TXB 0x02
784 #define MSETEST4_SRX 0x01
806 #define _PADWR _PIO( 0x0000 )
807 #define _PBDWR _PIO( 0x0400 )
808 #define _PADRR _PIO( 0x0000 )
809 #define _PBDRR _PIO( 0x0400 )
810 #define _PADDR _PIO( 0x0800 )
811 #define _PBDDR _PIO( 0x0c00 )
812 #define _PASSR _PIO( 0x1000 )
813 #define _PBSSR _PIO( 0x1400 )
845 #define _PXDWR _KEYPAD( 0x0000 )
846 #define _PXDRR _KEYPAD( 0x0000 )
847 #define _PYDWR _KEYPAD( 0x0400 )
848 #define _PYDRR _KEYPAD( 0x0400 )
874 #define _PCSR _CARD( 0x0000 )
875 #define _PCCR _CARD( 0x0400 )
876 #define _PCSSR _CARD( 0x0800 )
883 #define PCSR_S0_ready 0x0001
884 #define PCSR_S1_ready 0x0002
885 #define PCSR_S0_detected 0x0004
886 #define PCSR_S1_detected 0x0008
887 #define PCSR_S0_VS1 0x0010
888 #define PCSR_S0_VS2 0x0020
889 #define PCSR_S1_VS1 0x0040
890 #define PCSR_S1_VS2 0x0080
891 #define PCSR_S0_WP 0x0100
892 #define PCSR_S1_WP 0x0200
893 #define PCSR_S0_BVD1_nSTSCHG 0x0400
894 #define PCSR_S0_BVD2_nSPKR 0x0800
895 #define PCSR_S1_BVD1_nSTSCHG 0x1000
896 #define PCSR_S1_BVD2_nSPKR 0x2000
898 #define PCCR_S0_VPP0 0x0001
899 #define PCCR_S0_VPP1 0x0002
900 #define PCCR_S0_VCC0 0x0004
901 #define PCCR_S0_VCC1 0x0008
902 #define PCCR_S1_VPP0 0x0010
903 #define PCCR_S1_VPP1 0x0020
904 #define PCCR_S1_VCC0 0x0040
905 #define PCCR_S1_VCC1 0x0080
906 #define PCCR_S0_reset 0x0100
907 #define PCCR_S1_reset 0x0200
908 #define PCCR_S0_float 0x0400
909 #define PCCR_S1_float 0x0800
911 #define PCSSR_S0_VCC0 0x0001
912 #define PCSSR_S0_VCC1 0x0002
913 #define PCSSR_S0_VPP0 0x0004
914 #define PCSSR_S0_VPP1 0x0008
915 #define PCSSR_S0_control 0x0010
916 #define PCSSR_S1_VCC0 0x0020
917 #define PCSSR_S1_VCC1 0x0040
918 #define PCSSR_S1_VPP0 0x0080
919 #define PCSSR_S1_VPP1 0x0100
920 #define PCSSR_S1_control 0x0200