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/linux-3.3/drivers/media/dvb/bt8xx/
Dbt878.h33 #define BT878_VERSION_CODE 0x000000
35 #define BT878_AINT_STAT 0x100
36 #define BT878_ARISCS (0xf<<28)
49 #define BT878_AINT_MASK 0x104
51 #define BT878_AGPIO_DMA_CTL 0x10c
52 #define BT878_A_GAIN (0xf<<28)
59 #define BT878_DA_LRD (0x1f<<16)
64 #define BT878_DA_SDR (0xf<<8)
72 #define BT878_APACK_LEN 0x110
73 #define BT878_AFP_LEN (0xff<<16)
[all …]
/linux-3.3/arch/mips/pci/
Dpci-vr41xx.h25 #define PCIU_BASE 0x0f000c00UL
26 #define PCIU_SIZE 0x200UL
28 #define PCIMMAW1REG 0x00
29 #define PCIMMAW2REG 0x04
30 #define PCITAW1REG 0x08
31 #define PCITAW2REG 0x0c
32 #define PCIMIOAWREG 0x10
33 #define IBA(addr) ((addr) & 0xff000000U)
34 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
35 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/linux-3.3/arch/powerpc/platforms/cell/
Dcelleb_scc.h24 #define PCI_VENDOR_ID_TOSHIBA_2 0x102f
25 #define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
26 #define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
27 #define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
28 #define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
29 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
30 #define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
31 #define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
34 #define SCC_EPCI_REG 0x0000d000
[all …]
/linux-3.3/arch/arm/mach-orion5x/include/mach/
Dbridge-regs.h16 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
18 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
20 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
21 #define WDT_RESET_OUT_EN 0x0002
23 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
25 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
27 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
29 #define WDT_INT_REQ 0x0008
31 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
33 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
[all …]
/linux-3.3/arch/arm/mach-mmp/include/mach/
Dentry-macro.S18 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
19 and \tmp, \tmp, #0xff00
20 cmp \tmp, #0x5800
22 addne \base, \base, #0x10c @ PJ1 AP INT SEL register
23 addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
27 ldr \tmp, [\base, #0]
28 and \irqnr, \tmp, #0x3f
Dregs-icu.h16 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
20 #define ICU_INT_CONF_MASK (0xf)
27 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
28 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
29 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
30 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
31 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
43 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
44 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
45 #define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
[all …]
/linux-3.3/arch/arm/mach-s3c64xx/include/mach/
Dregs-sys.h20 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
21 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
24 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
26 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
/linux-3.3/arch/arm/mach-exynos/include/mach/
Dregs-mct.h20 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
21 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
22 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
24 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
25 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
26 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
28 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
30 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
31 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
32 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
[all …]
/linux-3.3/include/linux/
Datmel_pdc.h19 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
20 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
21 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
22 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
23 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
24 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
25 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
26 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
28 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
29 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
Dtifm.h23 FM_SET_INTERRUPT_ENABLE = 0x008,
24 FM_CLEAR_INTERRUPT_ENABLE = 0x00c,
25 FM_INTERRUPT_STATUS = 0x014
30 SOCK_CONTROL = 0x004,
31 SOCK_PRESENT_STATE = 0x008,
32 SOCK_DMA_ADDRESS = 0x00c,
33 SOCK_DMA_CONTROL = 0x010,
34 SOCK_DMA_FIFO_INT_ENABLE_SET = 0x014,
35 SOCK_DMA_FIFO_INT_ENABLE_CLEAR = 0x018,
36 SOCK_DMA_FIFO_STATUS = 0x020,
[all …]
/linux-3.3/arch/arm/mach-w90x900/include/mach/
Dregs-irq.h25 #define REG_AIC_IRQSC (AIC_BA+0x80)
26 #define REG_AIC_GEN (AIC_BA+0x84)
27 #define REG_AIC_GASR (AIC_BA+0x88)
28 #define REG_AIC_GSCR (AIC_BA+0x8C)
29 #define REG_AIC_IRSR (AIC_BA+0x100)
30 #define REG_AIC_IASR (AIC_BA+0x104)
31 #define REG_AIC_ISR (AIC_BA+0x108)
32 #define REG_AIC_IPER (AIC_BA+0x10C)
33 #define REG_AIC_ISNR (AIC_BA+0x110)
34 #define REG_AIC_IMR (AIC_BA+0x114)
[all …]
/linux-3.3/arch/arm/mach-ks8695/include/mach/
Dregs-pci.h14 #define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
19 #define KS8695_CRCFID (0x000) /* Configuration: Identification */
20 #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
21 #define KS8695_CRCFRV (0x008) /* Configuration: Revision */
22 #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
23 #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
24 #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
25 #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
26 #define KS8695_PBCA (0x100) /* Bridge Configuration Address */
27 #define KS8695_PBCD (0x104) /* Bridge Configuration Data */
[all …]
/linux-3.3/arch/arm/mach-s5pc100/include/mach/
Dregs-clock.h22 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
23 #define S5P_MPLL_LOCK S5P_CLKREG(0x04)
24 #define S5P_EPLL_LOCK S5P_CLKREG(0x08)
25 #define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
27 #define S5P_APLL_CON S5P_CLKREG(0x100)
28 #define S5P_MPLL_CON S5P_CLKREG(0x104)
29 #define S5P_EPLL_CON S5P_CLKREG(0x108)
30 #define S5P_HPLL_CON S5P_CLKREG(0x10C)
32 #define S5P_CLK_SRC0 S5P_CLKREG(0x200)
33 #define S5P_CLK_SRC1 S5P_CLKREG(0x204)
[all …]
/linux-3.3/arch/arm/mach-omap2/
Domap-smc.S30 smc #0
46 mov r1, #0x0 @ Process ID
47 mov r6, #0xff
48 mov r12, #0x00 @ Secure Service ID
49 mov r7, #0
50 mcr p15, 0, r7, c7, c5, 6
53 smc #0
59 ldr r12, =0x104
61 smc #0
67 ldr r12, =0x105
[all …]
Dmailbox.c22 #define MAILBOX_REVISION 0x000
23 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
26 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
27 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
29 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
30 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
36 #define MBOX_REG_SIZE 0x120
[all …]
/linux-3.3/arch/powerpc/platforms/82xx/
Dpq2.c24 #define RMR_CSRE 0x00000001
33 in_8(&cpm2_immr->im_clkrst.res[0]); in pq2_restart()
42 if (bus == 0 && PCI_SLOT(devfn) == 0) in pq2_pci_exclude_device()
53 if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) in pq2_pci_add_bridge()
64 setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); in pq2_pci_add_bridge()
/linux-3.3/arch/arm/mach-at91/include/mach/
Dat91_aic.h31 #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
32 #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
34 #define AT91_AIC_SRCTYPE_LOW (0 << 5)
39 #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
40 #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
41 #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
42 #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
43 #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
45 #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
46 #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
[all …]
/linux-3.3/drivers/media/dvb/b2c2/
Dflexcop-reg.h10 FLEXCOP_UNK = 0,
17 FC_UNK = 0,
30 FC_USB = 0,
45 #define fc_data_Tag_ID_DVB 0x3e
46 #define fc_data_Tag_ID_ATSC 0x3f
47 #define fc_data_Tag_ID_IDSB 0x8b
49 #define fc_key_code_default 0x1
50 #define fc_key_code_even 0x2
51 #define fc_key_code_odd 0x3
62 FC_WRITE = 0,
[all …]
/linux-3.3/arch/arm/include/asm/hardware/
Dcache-l2x0.h25 #define L2X0_CACHE_ID 0x000
26 #define L2X0_CACHE_TYPE 0x004
27 #define L2X0_CTRL 0x100
28 #define L2X0_AUX_CTRL 0x104
29 #define L2X0_TAG_LATENCY_CTRL 0x108
30 #define L2X0_DATA_LATENCY_CTRL 0x10C
31 #define L2X0_EVENT_CNT_CTRL 0x200
32 #define L2X0_EVENT_CNT1_CFG 0x204
33 #define L2X0_EVENT_CNT0_CFG 0x208
34 #define L2X0_EVENT_CNT1_VAL 0x20C
[all …]
/linux-3.3/drivers/video/omap2/dss/
Dti_hdmi_4xxx_ip.h35 #define HDMI_WP_REVISION 0x0
36 #define HDMI_WP_SYSCONFIG 0x10
37 #define HDMI_WP_IRQSTATUS_RAW 0x24
38 #define HDMI_WP_IRQSTATUS 0x28
39 #define HDMI_WP_PWR_CTRL 0x40
40 #define HDMI_WP_IRQENABLE_SET 0x2C
41 #define HDMI_WP_VIDEO_CFG 0x50
42 #define HDMI_WP_VIDEO_SIZE 0x60
43 #define HDMI_WP_VIDEO_TIMING_H 0x68
44 #define HDMI_WP_VIDEO_TIMING_V 0x6C
[all …]
/linux-3.3/arch/arm/mach-ux500/
Dmodem-irq-db5500.c17 #define MODEM_INTCON_BASE_ADDR 0xBFFD3000
18 #define MODEM_INTCON_SIZE 0xFFF
20 #define DEST_IRQ41_OFFSET 0x2A4
21 #define DEST_IRQ43_OFFSET 0x2AC
22 #define DEST_IRQ45_OFFSET 0x2B4
24 #define PRIO_IRQ41_OFFSET 0x6A4
25 #define PRIO_IRQ43_OFFSET 0x6AC
26 #define PRIO_IRQ45_OFFSET 0x6B4
28 #define ALLOW_IRQ_OFFSET 0x104
30 #define MODEM_INTCON_CPU_NBR 0x1
[all …]
/linux-3.3/arch/arm/mach-imx/
Dmach-imx6q.c37 wdog_base = of_iomap(np, 0); in imx6q_restart()
58 soft_restart(0); in imx6q_restart()
65 phy_write(phydev, 0x0b, 0x8105); in ksz9021rn_phy_fixup()
66 phy_write(phydev, 0x0c, 0x0000); in ksz9021rn_phy_fixup()
69 phy_write(phydev, 0x0b, 0x8104); in ksz9021rn_phy_fixup()
70 phy_write(phydev, 0x0c, 0xf0f0); in ksz9021rn_phy_fixup()
71 phy_write(phydev, 0x0b, 0x104); in ksz9021rn_phy_fixup()
73 return 0; in ksz9021rn_phy_fixup()
102 return 0; in imx6q_gpio_add_irq_domain()
113 l2x0_of_init(0, ~0UL); in imx6q_init_irq()
/linux-3.3/drivers/net/wireless/mwifiex/
Dcfp.c40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
/linux-3.3/drivers/media/video/ivtv/
Divtv-firmware.c31 #define IVTV_MASK_SPU_ENABLE 0xFFFFFFFE
32 #define IVTV_MASK_VPU_ENABLE15 0xFFFFFFF6
33 #define IVTV_MASK_VPU_ENABLE16 0xFFFFFFFB
34 #define IVTV_CMD_VDM_STOP 0x00000000
35 #define IVTV_CMD_AO_STOP 0x00000005
36 #define IVTV_CMD_APU_PING 0x00000000
37 #define IVTV_CMD_VPU_STOP15 0xFFFFFFFE
38 #define IVTV_CMD_VPU_STOP16 0xFFFFFFEE
39 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
40 #define IVTV_CMD_SPU_STOP 0x00000001
[all …]
/linux-3.3/drivers/firewire/
Dohci.h6 #define OHCI1394_Version 0x000
7 #define OHCI1394_GUID_ROM 0x004
8 #define OHCI1394_ATRetries 0x008
9 #define OHCI1394_CSRData 0x00C
10 #define OHCI1394_CSRCompareData 0x010
11 #define OHCI1394_CSRControl 0x014
12 #define OHCI1394_ConfigROMhdr 0x018
13 #define OHCI1394_BusID 0x01C
14 #define OHCI1394_BusOptions 0x020
15 #define OHCI1394_GUIDHi 0x024
[all …]

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