Lines Matching +full:0 +full:x104
31 #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
32 #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
34 #define AT91_AIC_SRCTYPE_LOW (0 << 5)
39 #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
40 #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
41 #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
42 #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
43 #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
45 #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
46 #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
47 #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
48 #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
51 #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
52 #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
53 #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
54 #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
55 #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
56 #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
57 #define AT91_AIC_DCR 0x138 /* Debug Control Register */
58 #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
61 #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
62 #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
63 #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */