1 /* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h 2 * 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com/ 5 * 6 * S5PC100 - Clock register definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_REGS_CLOCK_H 14 #define __ASM_ARCH_REGS_CLOCK_H __FILE__ 15 16 #include <mach/map.h> 17 18 #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 19 20 #define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x)) 21 22 #define S5P_APLL_LOCK S5P_CLKREG(0x00) 23 #define S5P_MPLL_LOCK S5P_CLKREG(0x04) 24 #define S5P_EPLL_LOCK S5P_CLKREG(0x08) 25 #define S5P_HPLL_LOCK S5P_CLKREG(0x0C) 26 27 #define S5P_APLL_CON S5P_CLKREG(0x100) 28 #define S5P_MPLL_CON S5P_CLKREG(0x104) 29 #define S5P_EPLL_CON S5P_CLKREG(0x108) 30 #define S5P_HPLL_CON S5P_CLKREG(0x10C) 31 32 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) 33 #define S5P_CLK_SRC1 S5P_CLKREG(0x204) 34 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) 35 #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) 36 37 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) 38 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) 39 #define S5P_CLK_DIV2 S5P_CLKREG(0x308) 40 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) 41 #define S5P_CLK_DIV4 S5P_CLKREG(0x310) 42 43 #define S5P_CLK_OUT S5P_CLKREG(0x400) 44 45 #define S5P_CLKGATE_D00 S5P_CLKREG(0x500) 46 #define S5P_CLKGATE_D01 S5P_CLKREG(0x504) 47 #define S5P_CLKGATE_D02 S5P_CLKREG(0x508) 48 49 #define S5P_CLKGATE_D10 S5P_CLKREG(0x520) 50 #define S5P_CLKGATE_D11 S5P_CLKREG(0x524) 51 #define S5P_CLKGATE_D12 S5P_CLKREG(0x528) 52 #define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) 53 #define S5P_CLKGATE_D14 S5P_CLKREG(0x530) 54 #define S5P_CLKGATE_D15 S5P_CLKREG(0x534) 55 56 #define S5P_CLKGATE_D20 S5P_CLKREG(0x540) 57 58 #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560) 59 #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564) 60 61 /* CLKDIV0 */ 62 #define S5P_CLKDIV0_D0_MASK (0x7<<8) 63 #define S5P_CLKDIV0_D0_SHIFT (8) 64 #define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) 65 #define S5P_CLKDIV0_PCLKD0_SHIFT (12) 66 67 /* CLKDIV1 */ 68 #define S5P_CLKDIV1_D1_MASK (0x7<<12) 69 #define S5P_CLKDIV1_D1_SHIFT (12) 70 #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) 71 #define S5P_CLKDIV1_PCLKD1_SHIFT (16) 72 73 #define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) 74 #define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200) 75 76 #define S5PC100_SWRESET_RESETVAL 0xc100 77 78 #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 79 80 #endif /* __ASM_ARCH_REGS_CLOCK_H */ 81