Lines Matching +full:0 +full:x104
22 #define MAILBOX_REVISION 0x000
23 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
26 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
27 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
29 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
30 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
36 #define MBOX_REG_SIZE 0x120
38 #define OMAP4_MBOX_REG_SIZE 0x130
84 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); in omap2_mbox_startup()
88 return 0; in omap2_mbox_startup()
116 return (mbox_read_reg(fifo->msg_stat) == 0); in omap2_mbox_fifo_empty()
182 for (i = 0; i < nr_regs; i++) { in omap2_mbox_save_ctx()
199 for (i = 0; i < nr_regs; i++) { in omap2_mbox_restore_ctx()
224 * MAILBOX 0: ARM -> DSP,
236 .msg = MAILBOX_MESSAGE(0),
237 .fifo_stat = MAILBOX_FIFOSTATUS(0),
243 .irqenable = MAILBOX_IRQENABLE(0),
244 .irqstatus = MAILBOX_IRQSTATUS(0),
245 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
247 .irqdisable = MAILBOX_IRQENABLE(0),
300 .msg = MAILBOX_MESSAGE(0),
301 .fifo_stat = MAILBOX_FIFOSTATUS(0),
307 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
308 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
309 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
311 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
329 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
330 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
333 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
357 list[0]->irq = platform_get_irq(pdev, 0); in omap2_mbox_probe()
364 list[0]->irq = platform_get_irq(pdev, 0); in omap2_mbox_probe()
368 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); in omap2_mbox_probe()
376 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); in omap2_mbox_probe()
384 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in omap2_mbox_probe()
395 return 0; in omap2_mbox_probe()
402 return 0; in omap2_mbox_remove()