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/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fff4000000000000) (OK)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
13 to uint64: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
[all …]
/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00ffffffffffffffff) (OK)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
19 to uint64: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
21 to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (OK)
[all …]
/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/qemu/hw/arm/
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Dintegratorcp.c58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
86 if (offset >= 0x100 && offset < 0x200) { in integratorcm_read()
88 if (offset >= 0x180) in integratorcm_read()
89 return 0; in integratorcm_read()
93 case 0: /* CM_ID */ in integratorcm_read()
94 return 0x411a3001; in integratorcm_read()
96 return 0; in integratorcm_read()
102 return 0x00100000; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
[all …]
/qemu/include/standard-headers/uefi/
H A Duefi.h49 #define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
51 #define EFI_HOB_TYPE_HANDOFF 0x0001
52 #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
53 #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
54 #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
55 #define EFI_HOB_TYPE_FV 0x0005
56 #define EFI_HOB_TYPE_CPU 0x0006
57 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
58 #define EFI_HOB_TYPE_FV2 0x0009
59 #define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
[all …]
/qemu/target/microblaze/
H A Dcpu.h44 #define MB_CPU_IRQ 0
49 #define SR_PC 0
54 #define SR_BTR 0xb
55 #define SR_EDR 0xd
58 #define MSR_BE (1<<0) /* 0x001 */
59 #define MSR_IE (1<<1) /* 0x002 */
60 #define MSR_C (1<<2) /* 0x004 */
61 #define MSR_BIP (1<<3) /* 0x008 */
62 #define MSR_FSL (1<<4) /* 0x010 */
63 #define MSR_ICE (1<<5) /* 0x020 */
[all …]
/qemu/include/hw/pci/
H A Dpcie_regs.h14 #define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */
15 #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
18 #define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
80 #define PCI_EXP_DEVCAP2_EFF 0x100000
81 #define PCI_EXP_DEVCAP2_EETLPP 0x200000
83 #define PCI_EXP_DEVCTL2_EETLPPB 0x8000
99 #define PCI_ERR_SIZEOF 0x48
101 #define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */
102 #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
103 #define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */
[all …]
/qemu/target/sh4/
H A Dhelper.c33 #define MMU_OK 0
53 return !(addr & 0x80000000); in cpu_sh4_is_cached()
70 if (do_exp && cs->exception_index != 0x1e0) { in superh_cpu_do_interrupt()
84 env->in_sleep = 0; in superh_cpu_do_interrupt()
88 (env->sr >> 4) & 0xf); in superh_cpu_do_interrupt()
97 case 0x0e0: in superh_cpu_do_interrupt()
100 case 0x040: in superh_cpu_do_interrupt()
103 case 0x0a0: in superh_cpu_do_interrupt()
106 case 0x180: in superh_cpu_do_interrupt()
109 case 0x1a0: in superh_cpu_do_interrupt()
[all …]
/qemu/hw/net/
H A De1000x_regs.h36 #define E1000_DEV_ID_82542 0x1000
37 #define E1000_DEV_ID_82543GC_FIBER 0x1001
38 #define E1000_DEV_ID_82543GC_COPPER 0x1004
39 #define E1000_DEV_ID_82544EI_COPPER 0x1008
40 #define E1000_DEV_ID_82544EI_FIBER 0x1009
41 #define E1000_DEV_ID_82544GC_COPPER 0x100C
42 #define E1000_DEV_ID_82544GC_LOM 0x100D
43 #define E1000_DEV_ID_82540EM 0x100E
44 #define E1000_DEV_ID_82540EM_LOM 0x1015
45 #define E1000_DEV_ID_82540EP_LOM 0x1016
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_fp0_arith.S23 assert eqi, a2, 0
31 test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
32 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \
34 test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
35 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \
39 test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
40 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
46 test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
47 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \
51 test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
[all …]
/qemu/tests/tcg/i386/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffe00000)
3 to double: f64(-nan:0x00fffc000000000000) (OK)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]
/qemu/tests/tcg/x86_64/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]
/qemu/hw/pci-host/
H A Duninorth.c61 slot = ctz32(reg & 0xfffff800); in unin_get_config_reg()
63 slot = -1; /* XXX: should this be 0? */ in unin_get_config_reg()
69 retval = (reg & (0xff - 7)) | (addr & 7); in unin_get_config_reg()
127 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); in pci_unin_main_realize()
129 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); in pci_unin_main_realize()
146 obj, "unin-pci-conf-idx", 0x1000); in pci_unin_main_init()
148 "unin-pci-conf-data", 0x1000); in pci_unin_main_init()
151 0x100000000ULL); in pci_unin_main_init()
153 "unin-pci-isa-mmio", 0x00800000); in pci_unin_main_init()
157 0x80000000ULL, 0x10000000ULL); in pci_unin_main_init()
[all …]
/qemu/linux-user/ppc/
H A Dtermbits.h24 #define TARGET_VINTR 0
150 #define TARGET_ISIG 0x00000080
151 #define TARGET_ICANON 0x00000100
152 #define TARGET_XCASE 0x00004000
153 #define TARGET_ECHO 0x00000008
154 #define TARGET_ECHOE 0x00000002
155 #define TARGET_ECHOK 0x00000004
156 #define TARGET_ECHONL 0x00000010
157 #define TARGET_NOFLSH 0x80000000
158 #define TARGET_TOSTOP 0x00400000
[all …]
/qemu/target/avr/
H A Dcpu.h38 * e.g. both have 0 address
42 #define MMU_CODE_IDX 0
51 /* CPU registers mapped into i/o ports 0x38-0x3f. */
52 #define REG_38_RAMPD 0
71 #define OFFSET_CODE 0x00000000
73 #define OFFSET_DATA 0x00800000
117 uint32_t pc_w; /* 0x003fffff up to 22 bits */
119 uint32_t sregC; /* 0x00000001 1 bit */
120 uint32_t sregZ; /* 0x00000001 1 bit */
121 uint32_t sregN; /* 0x00000001 1 bit */
[all …]

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