Lines Matching +full:0 +full:x00800000

61         slot = ctz32(reg & 0xfffff800);  in unin_get_config_reg()
63 slot = -1; /* XXX: should this be 0? */ in unin_get_config_reg()
69 retval = (reg & (0xff - 7)) | (addr & 7); in unin_get_config_reg()
127 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); in pci_unin_main_realize()
129 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); in pci_unin_main_realize()
146 obj, "unin-pci-conf-idx", 0x1000); in pci_unin_main_init()
148 "unin-pci-conf-data", 0x1000); in pci_unin_main_init()
151 0x100000000ULL); in pci_unin_main_init()
153 "unin-pci-isa-mmio", 0x00800000); in pci_unin_main_init()
157 0x80000000ULL, 0x10000000ULL); in pci_unin_main_init()
177 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); in pci_u3_agp_realize()
179 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); in pci_u3_agp_realize()
190 obj, "unin-pci-conf-idx", 0x1000); in pci_u3_agp_init()
192 "unin-pci-conf-data", 0x1000); in pci_u3_agp_init()
195 0x100000000ULL); in pci_u3_agp_init()
197 "unin-pci-isa-mmio", 0x00800000); in pci_u3_agp_init()
201 0x80000000ULL, 0x70000000ULL); in pci_u3_agp_init()
221 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); in pci_unin_agp_realize()
223 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); in pci_unin_agp_realize()
234 obj, "unin-agp-conf-idx", 0x1000); in pci_unin_agp_init()
236 obj, "unin-agp-conf-data", 0x1000); in pci_unin_agp_init()
254 PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); in pci_unin_internal_realize()
256 pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); in pci_unin_internal_realize()
267 obj, "unin-pci-conf-idx", 0x1000); in pci_unin_internal_init()
269 obj, "unin-pci-conf-data", 0x1000); in pci_unin_internal_init()
279 d->config[PCI_CACHE_LINE_SIZE] = 0x08; in unin_main_pci_host_realize()
280 d->config[PCI_LATENCY_TIMER] = 0x10; in unin_main_pci_host_realize()
281 d->config[PCI_CAPABILITY_LIST] = 0x00; in unin_main_pci_host_realize()
284 * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI in unin_main_pci_host_realize()
285 * memory space with base 0x80000000, size 0x10000000 for Apple's in unin_main_pci_host_realize()
288 d->config[0x48] = 0x0; in unin_main_pci_host_realize()
289 d->config[0x49] = 0x0; in unin_main_pci_host_realize()
290 d->config[0x4a] = 0x0; in unin_main_pci_host_realize()
291 d->config[0x4b] = 0x1; in unin_main_pci_host_realize()
296 d->config[PCI_CACHE_LINE_SIZE] = 0x08; in unin_agp_pci_host_realize()
297 d->config[PCI_LATENCY_TIMER] = 0x10; in unin_agp_pci_host_realize()
298 /* d->config[PCI_CAPABILITY_LIST] = 0x80; */ in unin_agp_pci_host_realize()
303 d->config[PCI_CACHE_LINE_SIZE] = 0x08; in u3_agp_pci_host_realize()
304 d->config[PCI_LATENCY_TIMER] = 0x10; in u3_agp_pci_host_realize()
309 d->config[PCI_CACHE_LINE_SIZE] = 0x08; in unin_internal_pci_host_realize()
310 d->config[PCI_LATENCY_TIMER] = 0x10; in unin_internal_pci_host_realize()
311 d->config[PCI_CAPABILITY_LIST] = 0x00; in unin_internal_pci_host_realize()
322 k->revision = 0x00; in unin_main_pci_host_class_init()
350 k->revision = 0x00; in u3_agp_pci_host_class_init()
378 k->revision = 0x00; in unin_agp_pci_host_class_init()
407 k->revision = 0x00; in unin_internal_pci_host_class_init()
511 case 0: in unin_read()
515 value = 0; in unin_read()
534 memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000); in unin_init()