Lines Matching +full:0 +full:x00800000

38  * e.g. both have 0 address
42 #define MMU_CODE_IDX 0
51 /* CPU registers mapped into i/o ports 0x38-0x3f. */
52 #define REG_38_RAMPD  0
71 #define OFFSET_CODE 0x00000000
73 #define OFFSET_DATA 0x00800000
117     uint32_t pc_w; /* 0x003fffff up to 22 bits */
119     uint32_t sregC; /* 0x00000001 1 bit */
120     uint32_t sregZ; /* 0x00000001 1 bit */
121     uint32_t sregN; /* 0x00000001 1 bit */
122     uint32_t sregV; /* 0x00000001 1 bit */
123     uint32_t sregS; /* 0x00000001 1 bit */
124     uint32_t sregH; /* 0x00000001 1 bit */
125     uint32_t sregT; /* 0x00000001 1 bit */
126     uint32_t sregI; /* 0x00000001 1 bit */
128     uint32_t rampD; /* 0x00ff0000 8 bits */
129     uint32_t rampX; /* 0x00ff0000 8 bits */
130     uint32_t rampY; /* 0x00ff0000 8 bits */
131     uint32_t rampZ; /* 0x00ff0000 8 bits */
132     uint32_t eind; /* 0x00ff0000 8 bits */
189     return (env->features & (1U << feature)) != 0;  in avr_feature()
210     return env->sregI != 0;  in cpu_interrupts_enabled()
215     return (env->sregC) << 0  in cpu_get_sreg()
227     env->sregC = (sreg >> 0) & 0x01;  in cpu_set_sreg()
228     env->sregZ = (sreg >> 1) & 0x01;  in cpu_set_sreg()
229     env->sregN = (sreg >> 2) & 0x01;  in cpu_set_sreg()
230     env->sregV = (sreg >> 3) & 0x01;  in cpu_set_sreg()
231     env->sregS = (sreg >> 4) & 0x01;  in cpu_set_sreg()
232     env->sregH = (sreg >> 5) & 0x01;  in cpu_set_sreg()
233     env->sregT = (sreg >> 6) & 0x01;  in cpu_set_sreg()
234     env->sregI = (sreg >> 7) & 0x01;  in cpu_set_sreg()