| /qemu/include/hw/misc/macio/ |
| H A D | pmu.h | 25 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
26 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
27 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
28 #define PMU_SET_RTC 0x30 /* set real-time clock */
29 #define PMU_READ_RTC 0x38 /* read real-time clock */
33 #define PMU_PCEJECT 0x4c /* eject PC-card from slot */
41 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
67 #define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
85 #define PMU_I2C_MODE_STDSUB 1
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| /qemu/target/hexagon/imported/mmvec/ |
| H A D | encode_ext.def | 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
24 DEF_ENC(V6_extractw, ICLASS_LD" 001 0 000sssss PP0uuuuu --1ddddd") /* coproc insn, returns Rd */
32 DEF_CLASS32(ICLASS_NCJ" 1--- -------- PP------ --------",COPROC_VMEM)
33 DEF_CLASS32(ICLASS_NCJ" 1000 0-0ttttt PPi--iii ---ddddd",BaseOffset_VMEM_Loads)
34 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPivviii ---ddddd",BaseOffset_if_Pv_VMEM_Loads)
35 DEF_CLASS32(ICLASS_NCJ" 1000 0-1ttttt PPi--iii --------",BaseOffset_VMEM_Stores1)
36 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPi--iii 00------",BaseOffset_VMEM_Stores2)
37 DEF_CLASS32(ICLASS_NCJ" 1000 1-1ttttt PPivviii --------",BaseOffset_if_Pv_VMEM_Stores)
39 DEF_CLASS32(ICLASS_NCJ" 1001 0-0xxxxx PP---iii ---ddddd",PostImm_VMEM_Loads)
40 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP-vviii ---ddddd",PostImm_if_Pv_VMEM_Loads)
[all …]
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| /qemu/chardev/ |
| H A D | baum.c | 4 * Copyright (c) 2008, 2010-2011, 2016-2017 Samuel Thibault
28 #include "qemu/main-loop.h"
91 #define Y_MAX 1
110 #define TYPE_CHARDEV_BRAILLE "chardev-braille"
135 DO(BRLAPI_DOTS(1, 0, 0, 0, 0, 0, 0, 0), 'a'),
136 DO(BRLAPI_DOTS(1, 1, 0, 0, 0, 0, 0, 0), 'b'),
137 DO(BRLAPI_DOTS(1, 0, 0, 1, 0, 0, 0, 0), 'c'),
138 DO(BRLAPI_DOTS(1, 0, 0, 1, 1, 0, 0, 0), 'd'),
139 DO(BRLAPI_DOTS(1, 0, 0, 0, 1, 0, 0, 0), 'e'),
140 DO(BRLAPI_DOTS(1, 1, 0, 1, 0, 0, 0, 0), 'f'),
[all …]
|
| /qemu/tests/qemu-iotests/ |
| H A D | 261.out | 9 ID: 1
12 [1]
31 ID: 1
37 [1]
66 ID: 1
72 [1]
93 ID: 1
99 [1]
124 --- sn0 ---
135 [1]
[all …]
|
| H A D | 122 | 4 # Test some qemu-img convert cases
28 status=1 # failure is the default!
37 trap "_cleanup; exit \$status" 0 1 2 3 15
49 $QEMU_IO -c "write -P 0x11 0 64M" "$TEST_IMG".base 2>&1 | _filter_qemu_io | _filter_testdir
53 echo "=== Check allocation status regression with -B ==="
56 _make_test_img -b "$TEST_IMG".base -F $IMGFMT
57 $QEMU_IO -c "write -P 0x22 0 3M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
58 $QEMU_IMG convert -O $IMGFMT -B "$TEST_IMG".base \
59 -o backing_fmt=$IMGFMT "$TEST_IMG" "$TEST_IMG".orig
67 _make_test_img -b "$TEST_IMG".base -F $IMGFMT
[all …]
|
| /qemu/linux-user/arm/nwfpe/ |
| H A D | fpopcode.h | 27 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
28 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
30 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
31 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
54 P pre/post index bit: 0 = postindex, 1 = preindex
55 U up/down bit: 0 = stack grows down, 1 = stack grows up
56 W write back bit: 1 = update base register (Rn)
57 L load/store bit: 0 = store, 1 = load
64 uv transfer length (TABLE 1)
[all …]
|
| /qemu/ui/icons/ |
| H A D | qemu.svg | 1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
7 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
11 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
24 style="stop-color:#000000;stop-opacity:1;"
30 style="stop-color:#000000;stop-opacity:0.87843138;" />
32 style="stop-color:#ffffff;stop-opacity:0.43921569;"
38 style="stop-color:#181818;stop-opacity:1;" />
40 style="stop-color:#242424;stop-opacity:1;"
44 style="stop-color:#000000;stop-opacity:1;"
[all …]
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| /qemu/include/hw/misc/ |
| H A D | xlnx-versal-cfu.h | 8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * [1] Versal ACAP Technical Reference Manual,
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
15 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module
22 #include "hw/misc/xlnx-cfi-if.h"
25 #define TYPE_XLNX_VERSAL_CFU_APB "xlnx-versal-cfu-apb"
28 #define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx-versal-cfu-fdro"
31 #define TYPE_XLNX_VERSAL_CFU_SFR "xlnx-versal-cfu-sfr"
35 FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
36 FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
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| H A D | xlnx-versal-cframe-reg.h | 8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * [1] Versal ACAP Technical Reference Manual,
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
15 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFRAME_REG-Module
22 #include "hw/misc/xlnx-cfi-if.h"
23 #include "hw/misc/xlnx-versal-cfu.h"
26 #define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx-cframe-reg"
29 #define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
36 * 1, 2, 3).
75 FIELD(CTL, PER_FRAME_CRC, 0, 1)
[all …]
|
| /qemu/hw/intc/ |
| H A D | xlnx-pmu-iomod-intc.c | 34 #include "hw/intc/xlnx-pmu-iomod-intc.h"
36 #include "hw/qdev-properties.h"
48 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
55 FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)
56 FIELD(GPO0, RST_FTSM, 11, 1)
57 FIELD(GPO0, CLR_FTSTS, 10, 1)
58 FIELD(GPO0, RST_ON_SLEEP, 9, 1)
59 FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)
60 FIELD(GPO0, PIT3_PRESCALE, 7, 1)
63 FIELD(GPO0, PIT0_PRESCALE, 1, 2)
[all …]
|
| /qemu/hw/audio/ |
| H A D | intel-hda-defs.h | 7 /* --------------------------------------------------------------------- */
14 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
15 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
24 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
25 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
26 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
30 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
39 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
41 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
42 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
[all …]
|
| /qemu/pc-bios/ |
| H A D | qemu_logo.svg | 1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
7 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
11 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
26 style="stop-color:#000000;stop-opacity:1;"
32 style="stop-color:#000000;stop-opacity:0.87843138;" />
34 style="stop-color:#ffffff;stop-opacity:0.43921569;"
40 style="stop-color:#181818;stop-opacity:1;" />
42 style="stop-color:#242424;stop-opacity:1;"
46 style="stop-color:#000000;stop-opacity:1;"
[all …]
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| /qemu/target/hexagon/imported/ |
| H A D | encode_pp.def | 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
26 DEF_CLASS32("---- ---- -------- PP------ --------",ALL_PP)
27 DEF_FIELD32("---- ---- -------- !!------ --------",Parse,"Packet/Loop parse bits")
28 DEF_FIELD32("!!!! ---- -------- PP------ --------",ICLASS,"Instruction Class")
57 DEF_CLASS32(ICLASS_EXTENDER" ---- -------- PP------ --------",EXTENDER)
70 DEF_CLASS32(ICLASS_V2LDST" ---- -------- PP------ --------",V2LDST)
71 DEF_CLASS32(ICLASS_V2LDST" ---1 -------- PP------ --------",V2LD)
72 DEF_CLASS32(ICLASS_V2LDST" ---0 -------- PP------ --------",V2ST)
73 DEF_CLASS32(ICLASS_V2LDST" 0--1 -------- PP------ --------",PLD)
74 DEF_CLASS32(ICLASS_V2LDST" 0--0 -------- PP------ --------",PST)
[all …]
|
| /qemu/tests/unit/ |
| H A D | pkix_asn1_tab.c.inc | 9 {"id-ce", 1879048204, 0},
10 {"joint-iso-ccitt", 1073741825, "2"},
12 {0, 1, "29"},
13 {"id-ce-authorityKeyIdentifier", 1879048204, 0},
14 {0, 1073741825, "id-ce"},
15 {0, 1, "35"},
20 {0, 4104, "1"},
24 {"id-ce-subjectKeyIdentifier", 1879048204, 0},
25 {0, 1073741825, "id-ce"},
26 {0, 1, "14"},
[all …]
|
| H A D | test-smp-parse.c | 2 * SMP parsing unit-tests
10 * See the COPYING.LIB file in the top-level directory.
23 #define MIN_CPUS 1 /* set the min CPUs supported by the machine as 1 */
26 #define SMP_MACHINE_NAME "TEST-SMP"
29 * Used to define the generic 3-level CPU topology hierarchy
30 * -sockets/cores/threads
51 * Currently a 5-level topology hierarchy is supported on PC machines
52 * -sockets/dies/modules/cores/threads
67 * Currently a 4-level topology hierarchy is supported on ARM virt machines
68 * -sockets/clusters/cores/threads
[all …]
|
| H A D | test-hbitmap.c | 2 * Hierarchical bitmap unit-tests.
9 * See the COPYING file in the top-level directory.
44 hbitmap_iter_init(&hbi, data->hb, first); in hbitmap_test_check()
50 next = data->size; in hbitmap_test_check()
55 bit = i & (BITS_PER_LONG - 1); in hbitmap_test_check()
57 g_assert_cmpint(data->bits[pos] & (1UL << bit), ==, 0); in hbitmap_test_check()
60 if (next == data->size) { in hbitmap_test_check()
65 bit = i & (BITS_PER_LONG - 1); in hbitmap_test_check()
68 g_assert_cmpint(data->bits[pos] & (1UL << bit), !=, 0); in hbitmap_test_check()
72 g_assert_cmpint(count << data->granularity, ==, hbitmap_count(data->hb)); in hbitmap_test_check()
[all …]
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| /qemu/docs/specs/ |
| H A D | pci-ids.rst | 6 virtual devices. The vendor IDs are 1af4 (formerly Qumranet ID) and 1b36.
11 1af4 vendor ID
12 --------------
14 The 1000 -> 10ff device ID range is used as follows for virtio-pci devices.
18 1af4:1000
20 1af4:1001
22 1af4:1002
24 1af4:1003
26 1af4:1004
28 1af4:1005
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| /qemu/hw/net/can/ |
| H A D | xlnx-versal-canfd.c | 5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
42 #include "hw/qdev-properties.h"
45 #include "hw/net/xlnx-versal-canfd.h"
49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
56 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
[all …]
|
| /qemu/target/arm/tcg/ |
| H A D | vfp.decode | 30 # VFP registers have an odd encoding with a four-bit field
31 # and a one-bit field which are assembled in different orders
36 # support D16-D31" (which should UNDEF).
37 %vm_dp 5:1 0:4
38 %vm_sp 0:4 5:1
39 %vn_dp 7:1 16:4
40 %vn_sp 16:4 7:1
41 %vd_dp 22:1 12:4
42 %vd_sp 12:4 22:1
44 %vmov_idx_b 21:1 5:2
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|
| /qemu/hw/arm/ |
| H A D | smmuv3-internal.h | 2 * ARM SMMUv3 support - Internal API
4 * Copyright (C) 2014-2016 Broadcom Corporation
25 #include "hw/arm/smmu-common.h"
44 FIELD(IDR0, S2P, 0 , 1)
45 FIELD(IDR0, S1P, 1 , 1)
47 FIELD(IDR0, COHACC, 4 , 1)
48 FIELD(IDR0, BTM, 5 , 1)
50 FIELD(IDR0, DORMHINT, 8 , 1)
51 FIELD(IDR0, HYP, 9 , 1)
52 FIELD(IDR0, ATS, 10, 1)
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| /qemu/hw/m68k/ |
| H A D | mcf5206.c | 10 #include "qemu/error-report.h"
13 #include "hw/qdev-properties.h"
45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()
46 qemu_irq_raise(s->irq); in m5206_timer_update()
48 qemu_irq_lower(s->irq); in m5206_timer_update()
53 s->tmr = 0; in m5206_timer_reset()
54 s->trr = 0; in m5206_timer_reset()
62 ptimer_transaction_begin(s->timer); in m5206_timer_recalibrate()
63 ptimer_stop(s->timer); in m5206_timer_recalibrate()
65 if ((s->tmr & TMR_RST) == 0) { in m5206_timer_recalibrate()
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| /qemu/tests/tcg/hexagon/ |
| H A D | float_convd.ref | 3 to single: f32(-nan:0xffffffff) (INVALID)
4 to int32: -1 (INVALID)
5 to int64: -1 (INVALID)
6 to uint32: -1 (INVALID)
7 to uint64: -1 (INVALID)
8 from double: f64(-nan:0x00fff8000000000000)
9 to single: f32(-nan:0xffffffff) (OK)
10 to int32: -1 (INVALID)
11 to int64: -1 (INVALID)
12 to uint32: -1 (INVALID)
[all …]
|
| /qemu/target/hexagon/idef-parser/ |
| H A D | idef-parser.y | 3 * Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
14 #include "idef-parser.h"
15 #include "parser-helpers.h"
16 #include "idef-parser.tab.h"
17 #include "idef-parser.yy.h"
26 %lex-param {void *scanner}
27 %parse-param {void *scanner}
28 %parse-param {Context *c}
50 %expect 1
89 %left '-' '+'
[all …]
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| /qemu/target/i386/ |
| H A D | cpu.h | 24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-common.h"
27 #include "exec/cpu-defs.h"
28 #include "exec/cpu-interrupt.h"
31 #include "qapi/qapi-types-common.h"
32 #include "qemu/cpu-float.h"
34 #include "standard-headers/asm-x86/kvm_para.h"
48 R_ECX = 1,
65 R_CL = 1,
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|
| /qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 8 * Copyright (c) 1999-2007 Tensilica Inc.
19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
29 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
33 #define XCHAL_HAVE_DEBUG 1 /* debug option */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
36 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
[all …]
|
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![[all …]](/more/qemu/pc-bios/qemu_logo.svg?full=%5C-1){kind=link}