Lines Matching +full:- +full:1
10 #include "qemu/error-report.h"
13 #include "hw/qdev-properties.h"
45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()
46 qemu_irq_raise(s->irq); in m5206_timer_update()
48 qemu_irq_lower(s->irq); in m5206_timer_update()
53 s->tmr = 0; in m5206_timer_reset()
54 s->trr = 0; in m5206_timer_reset()
62 ptimer_transaction_begin(s->timer); in m5206_timer_recalibrate()
63 ptimer_stop(s->timer); in m5206_timer_recalibrate()
65 if ((s->tmr & TMR_RST) == 0) { in m5206_timer_recalibrate()
69 prescale = (s->tmr >> 8) + 1; in m5206_timer_recalibrate()
70 mode = (s->tmr >> 1) & 3; in m5206_timer_recalibrate()
79 if ((s->tmr & TMR_FRR) == 0) { in m5206_timer_recalibrate()
86 ptimer_set_freq(s->timer, 66000000 / prescale); in m5206_timer_recalibrate()
88 ptimer_set_limit(s->timer, s->trr, 0); in m5206_timer_recalibrate()
90 ptimer_run(s->timer, 0); in m5206_timer_recalibrate()
92 ptimer_transaction_commit(s->timer); in m5206_timer_recalibrate()
98 s->ter |= TER_REF; in m5206_timer_trigger()
106 return s->tmr; in m5206_timer_read()
108 return s->trr; in m5206_timer_read()
110 return s->tcr; in m5206_timer_read()
112 return s->trr - ptimer_get_count(s->timer); in m5206_timer_read()
114 return s->ter; in m5206_timer_read()
124 if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) { in m5206_timer_write()
127 s->tmr = val; in m5206_timer_write()
131 s->trr = val; in m5206_timer_write()
135 s->tcr = val; in m5206_timer_write()
138 ptimer_transaction_begin(s->timer); in m5206_timer_write()
139 ptimer_set_count(s->timer, val); in m5206_timer_write()
140 ptimer_transaction_commit(s->timer); in m5206_timer_write()
143 s->ter &= ~val; in m5206_timer_write()
153 s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_LEGACY); in m5206_timer_init()
154 s->irq = irq; in m5206_timer_init()
170 uint16_t imr; /* 1 == interrupt is masked. */
192 active = s->ipr & ~s->imr; in m5206_find_pending_irq()
196 for (i = 1; i < 14; i++) { in m5206_find_pending_irq()
197 if (active & (1 << i)) { in m5206_find_pending_irq()
198 if ((s->icr[i] & 0x1f) > level) { in m5206_find_pending_irq()
199 level = s->icr[i] & 0x1f; in m5206_find_pending_irq()
220 tmp = s->icr[irq]; in m5206_mbar_update()
228 vector = s->swivr; in m5206_mbar_update()
231 vector = s->uivr[0]; in m5206_mbar_update()
234 vector = s->uivr[1]; in m5206_mbar_update()
248 m68k_set_irq_level(s->cpu, level, vector); in m5206_mbar_update()
255 s->ipr |= 1 << irq; in m5206_mbar_set_irq()
257 s->ipr &= ~(1 << irq); in m5206_mbar_set_irq()
268 s->scr = 0xc0; in m5206_mbar_reset()
269 s->icr[1] = 0x04; in m5206_mbar_reset()
270 s->icr[2] = 0x08; in m5206_mbar_reset()
271 s->icr[3] = 0x0c; in m5206_mbar_reset()
272 s->icr[4] = 0x10; in m5206_mbar_reset()
273 s->icr[5] = 0x14; in m5206_mbar_reset()
274 s->icr[6] = 0x18; in m5206_mbar_reset()
275 s->icr[7] = 0x1c; in m5206_mbar_reset()
276 s->icr[8] = 0x1c; in m5206_mbar_reset()
277 s->icr[9] = 0x80; in m5206_mbar_reset()
278 s->icr[10] = 0x80; in m5206_mbar_reset()
279 s->icr[11] = 0x80; in m5206_mbar_reset()
280 s->icr[12] = 0x00; in m5206_mbar_reset()
281 s->icr[13] = 0x00; in m5206_mbar_reset()
282 s->imr = 0x3ffe; in m5206_mbar_reset()
283 s->rsr = 0x80; in m5206_mbar_reset()
284 s->swivr = 0x0f; in m5206_mbar_reset()
285 s->par = 0; in m5206_mbar_reset()
292 return m5206_timer_read(&s->timer[0], offset - 0x100); in m5206_mbar_read()
294 return m5206_timer_read(&s->timer[1], offset - 0x120); in m5206_mbar_read()
296 return mcf_uart_read(s->uart[0], offset - 0x140, size); in m5206_mbar_read()
298 return mcf_uart_read(s->uart[1], offset - 0x180, size); in m5206_mbar_read()
301 case 0x03: return s->scr; in m5206_mbar_read()
302 case 0x14 ... 0x20: return s->icr[offset - 0x13]; in m5206_mbar_read()
303 case 0x36: return s->imr; in m5206_mbar_read()
304 case 0x3a: return s->ipr; in m5206_mbar_read()
305 case 0x40: return s->rsr; in m5206_mbar_read()
307 case 0x42: return s->swivr; in m5206_mbar_read()
313 while (mask > current_machine->ram_size) { in m5206_mbar_read()
314 mask >>= 1; in m5206_mbar_read()
318 case 0x5c: return 1; /* DRAM bank 1 empty. */ in m5206_mbar_read()
319 case 0xcb: return s->par; in m5206_mbar_read()
320 case 0x170: return s->uivr[0]; in m5206_mbar_read()
321 case 0x1b0: return s->uivr[1]; in m5206_mbar_read()
332 m5206_timer_write(&s->timer[0], offset - 0x100, value); in m5206_mbar_write()
335 m5206_timer_write(&s->timer[1], offset - 0x120, value); in m5206_mbar_write()
338 mcf_uart_write(s->uart[0], offset - 0x140, value, size); in m5206_mbar_write()
341 mcf_uart_write(s->uart[1], offset - 0x180, value, size); in m5206_mbar_write()
346 s->scr = value; in m5206_mbar_write()
349 s->icr[offset - 0x13] = value; in m5206_mbar_write()
353 s->imr = value; in m5206_mbar_write()
357 s->rsr &= ~value; in m5206_mbar_write()
363 s->swivr = value; in m5206_mbar_write()
366 s->par = value; in m5206_mbar_write()
369 s->uivr[0] = value; in m5206_mbar_write()
375 s->uivr[1] = value; in m5206_mbar_write()
388 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
389 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
390 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
391 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
392 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
393 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
394 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
395 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
410 if (m5206_mbar_width[offset >> 2] > 1) { in m5206_mbar_readb()
412 val = m5206_mbar_readw(opaque, offset & ~1); in m5206_mbar_readb()
413 if ((offset & 1) == 0) { in m5206_mbar_readb()
418 return m5206_mbar_read(s, offset, 1); in m5206_mbar_readb()
441 val |= m5206_mbar_readb(opaque, offset + 1); in m5206_mbar_readw()
484 if (width > 1) { in m5206_mbar_writeb()
486 tmp = m5206_mbar_readw(opaque, offset & ~1); in m5206_mbar_writeb()
487 if (offset & 1) { in m5206_mbar_writeb()
492 m5206_mbar_writew(opaque, offset & ~1, tmp); in m5206_mbar_writeb()
495 m5206_mbar_write(s, offset, value, 1); in m5206_mbar_writeb()
522 m5206_mbar_writeb(opaque, offset + 1, value & 0xff); in m5206_mbar_writew()
551 case 1: in m5206_mbar_readfn()
566 case 1: in m5206_mbar_writefn()
583 .valid.min_access_size = 1,
592 memory_region_init_io(&s->iomem, NULL, &m5206_mbar_ops, s, in mcf5206_mbar_realize()
594 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in mcf5206_mbar_realize()
596 s->pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14); in mcf5206_mbar_realize()
597 m5206_timer_init(&s->timer[0], s->pic[9]); in mcf5206_mbar_realize()
598 m5206_timer_init(&s->timer[1], s->pic[10]); in mcf5206_mbar_realize()
599 s->uart[0] = mcf_uart_create(s->pic[12], serial_hd(0)); in mcf5206_mbar_realize()
600 s->uart[1] = mcf_uart_create(s->pic[13], serial_hd(1)); in mcf5206_mbar_realize()
604 DEFINE_PROP_LINK("m68k-cpu", m5206_mbar_state, cpu,
613 set_bit(DEVICE_CATEGORY_MISC, dc->categories); in mcf5206_mbar_class_init()
614 dc->desc = "MCF5206 system integration module"; in mcf5206_mbar_class_init()
615 dc->realize = mcf5206_mbar_realize; in mcf5206_mbar_class_init()