Lines Matching +full:- +full:1
5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
42 #include "hw/qdev-properties.h"
45 #include "hw/net/xlnx-versal-canfd.h"
49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
56 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
57 FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1)
58 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
59 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
71 FIELD(ERROR_STATUS_REGISTER, F_BERR, 11, 1)
72 FIELD(ERROR_STATUS_REGISTER, F_STER, 10, 1)
73 FIELD(ERROR_STATUS_REGISTER, F_FMER, 9, 1)
74 FIELD(ERROR_STATUS_REGISTER, F_CRCER, 8, 1)
75 FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
76 FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
77 FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
78 FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
79 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
82 FIELD(STATUS_REGISTER, SNOOP, 12, 1)
83 FIELD(STATUS_REGISTER, BSFR_CONFIG, 10, 1)
84 FIELD(STATUS_REGISTER, PEE_CONFIG, 9, 1)
86 FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
87 FIELD(STATUS_REGISTER, BBSY, 5, 1)
88 FIELD(STATUS_REGISTER, BIDLE, 4, 1)
89 FIELD(STATUS_REGISTER, NORMAL, 3, 1)
90 FIELD(STATUS_REGISTER, SLEEP, 2, 1)
91 FIELD(STATUS_REGISTER, LBACK, 1, 1)
92 FIELD(STATUS_REGISTER, CONFIG, 0, 1)
94 FIELD(INTERRUPT_STATUS_REGISTER, TXEWMFLL, 31, 1)
95 FIELD(INTERRUPT_STATUS_REGISTER, TXEOFLW, 30, 1)
98 FIELD(INTERRUPT_STATUS_REGISTER, RXMNF, 17, 1)
99 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 16, 1)
100 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 15, 1)
101 FIELD(INTERRUPT_STATUS_REGISTER, TXCRS, 14, 1)
102 FIELD(INTERRUPT_STATUS_REGISTER, TXRRS, 13, 1)
103 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
104 FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
105 FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
106 FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
112 FIELD(INTERRUPT_STATUS_REGISTER, ERROR_BIT, 8, 1)
113 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW, 6, 1)
114 FIELD(INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 5, 1)
115 FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
116 FIELD(INTERRUPT_STATUS_REGISTER, BSFRD, 3, 1)
117 FIELD(INTERRUPT_STATUS_REGISTER, PEE, 2, 1)
118 FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
119 FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
121 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEWMFLL, 31, 1)
122 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEOFLW, 30, 1)
123 FIELD(INTERRUPT_ENABLE_REGISTER, ERXMNF, 17, 1)
124 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL_1, 16, 1)
125 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFOFLW_1, 15, 1)
126 FIELD(INTERRUPT_ENABLE_REGISTER, ETXCRS, 14, 1)
127 FIELD(INTERRUPT_ENABLE_REGISTER, ETXRRS, 13, 1)
128 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
129 FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
130 FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
131 FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
132 FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
133 FIELD(INTERRUPT_ENABLE_REGISTER, ERFXOFLW, 6, 1)
134 FIELD(INTERRUPT_ENABLE_REGISTER, ETSCNT_OFLW, 5, 1)
135 FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
136 FIELD(INTERRUPT_ENABLE_REGISTER, EBSFRD, 3, 1)
137 FIELD(INTERRUPT_ENABLE_REGISTER, EPEE, 2, 1)
138 FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
139 FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1)
141 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEWMFLL, 31, 1)
142 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEOFLW, 30, 1)
143 FIELD(INTERRUPT_CLEAR_REGISTER, CRXMNF, 17, 1)
144 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL_1, 16, 1)
145 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFOFLW_1, 15, 1)
146 FIELD(INTERRUPT_CLEAR_REGISTER, CTXCRS, 14, 1)
147 FIELD(INTERRUPT_CLEAR_REGISTER, CTXRRS, 13, 1)
148 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
149 FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
150 FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
151 FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
152 FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
153 FIELD(INTERRUPT_CLEAR_REGISTER, CRFXOFLW, 6, 1)
154 FIELD(INTERRUPT_CLEAR_REGISTER, CTSCNT_OFLW, 5, 1)
155 FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
156 FIELD(INTERRUPT_CLEAR_REGISTER, CBSFRD, 3, 1)
157 FIELD(INTERRUPT_CLEAR_REGISTER, CPEE, 2, 1)
158 FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
159 FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1)
162 FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
164 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDC, 16, 1)
172 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR31, 31, 1)
173 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR30, 30, 1)
174 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR29, 29, 1)
175 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR28, 28, 1)
176 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR27, 27, 1)
177 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR26, 26, 1)
178 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR25, 25, 1)
179 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1)
180 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR23, 23, 1)
181 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR22, 22, 1)
182 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR21, 21, 1)
183 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR20, 20, 1)
184 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR19, 19, 1)
185 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR18, 18, 1)
186 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR17, 17, 1)
187 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR16, 16, 1)
188 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR15, 15, 1)
189 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR14, 14, 1)
190 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR13, 13, 1)
191 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR12, 12, 1)
192 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR11, 11, 1)
193 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR10, 10, 1)
194 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR9, 9, 1)
195 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR8, 8, 1)
196 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR7, 7, 1)
197 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR6, 6, 1)
198 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR5, 5, 1)
199 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR4, 4, 1)
200 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR3, 3, 1)
201 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR2, 2, 1)
202 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR1, 1, 1)
203 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1)
205 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS31, 31, 1)
206 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS30, 30, 1)
207 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS29, 29, 1)
208 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS28, 28, 1)
209 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS27, 27, 1)
210 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS26, 26, 1)
211 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS25, 25, 1)
212 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1)
213 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS23, 23, 1)
214 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS22, 22, 1)
215 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS21, 21, 1)
216 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS20, 20, 1)
217 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS19, 19, 1)
218 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS18, 18, 1)
219 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS17, 17, 1)
220 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS16, 16, 1)
221 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS15, 15, 1)
222 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS14, 14, 1)
223 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS13, 13, 1)
224 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS12, 12, 1)
225 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS11, 11, 1)
226 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS10, 10, 1)
227 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS9, 9, 1)
228 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS8, 8, 1)
229 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS7, 7, 1)
230 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS6, 6, 1)
231 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS5, 5, 1)
232 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS4, 4, 1)
233 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS3, 3, 1)
234 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS2, 2, 1)
235 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS1, 1, 1)
236 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1)
238 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR31, 31, 1)
239 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR30, 30, 1)
240 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR29, 29, 1)
241 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR28, 28, 1)
242 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR27, 27, 1)
243 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR26, 26, 1)
244 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR25, 25, 1)
245 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1)
246 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR23, 23, 1)
247 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR22, 22, 1)
248 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR21, 21, 1)
249 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR20, 20, 1)
250 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR19, 19, 1)
251 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR18, 18, 1)
252 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR17, 17, 1)
253 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR16, 16, 1)
254 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR15, 15, 1)
255 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR14, 14, 1)
256 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR13, 13, 1)
257 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR12, 12, 1)
258 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR11, 11, 1)
259 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR10, 10, 1)
260 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR9, 9, 1)
261 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR8, 8, 1)
262 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR7, 7, 1)
263 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR6, 6, 1)
264 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR5, 5, 1)
265 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR4, 4, 1)
266 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR3, 3, 1)
267 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR2, 2, 1)
268 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1)
269 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1)
272 1)
274 1)
276 1)
278 1)
280 1)
282 1)
284 1)
286 1)
288 1)
290 1)
292 1)
294 1)
296 1)
298 1)
300 1)
302 1)
304 1)
306 1)
308 1)
310 1)
312 1)
314 1)
315 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS9, 9, 1)
316 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS8, 8, 1)
317 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS7, 7, 1)
318 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS6, 6, 1)
319 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS5, 5, 1)
320 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS4, 4, 1)
321 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS3, 3, 1)
322 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS2, 2, 1)
323 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS1, 1, 1)
324 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1)
327 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI, 7, 1)
332 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF31, 31, 1)
333 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF30, 30, 1)
334 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF29, 29, 1)
335 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF28, 28, 1)
336 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF27, 27, 1)
337 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF26, 26, 1)
338 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF25, 25, 1)
339 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1)
340 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF23, 23, 1)
341 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF22, 22, 1)
342 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF21, 21, 1)
343 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF20, 20, 1)
344 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF19, 19, 1)
345 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF18, 18, 1)
346 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF17, 17, 1)
347 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF16, 16, 1)
348 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF15, 15, 1)
349 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF14, 14, 1)
350 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF13, 13, 1)
351 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF12, 12, 1)
352 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF11, 11, 1)
353 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF10, 10, 1)
354 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF9, 9, 1)
355 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF8, 8, 1)
356 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF7, 7, 1)
357 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF6, 6, 1)
358 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF5, 5, 1)
359 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF4, 4, 1)
360 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF3, 3, 1)
361 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF2, 2, 1)
362 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF1, 1, 1)
363 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1)
366 FIELD(RX_FIFO_STATUS_REGISTER, IRI_1, 23, 1)
369 FIELD(RX_FIFO_STATUS_REGISTER, IRI, 7, 1)
377 FIELD(TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
378 FIELD(TB_ID_REGISTER, IDE, 19, 1)
379 FIELD(TB_ID_REGISTER, ID_EXT, 1, 18)
380 FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1)
383 FIELD(TB0_DLC_REGISTER, FDF, 27, 1)
384 FIELD(TB0_DLC_REGISTER, BRS, 26, 1)
385 FIELD(TB0_DLC_REGISTER, RSVD2, 25, 1)
386 FIELD(TB0_DLC_REGISTER, EFC, 24, 1)
471 FIELD(AFMR_REGISTER, AMSRR, 20, 1)
472 FIELD(AFMR_REGISTER, AMIDE, 19, 1)
473 FIELD(AFMR_REGISTER, AMID_EXT, 1, 18)
474 FIELD(AFMR_REGISTER, AMRTR, 0, 1)
477 FIELD(AFIR_REGISTER, AISRR, 20, 1)
478 FIELD(AFIR_REGISTER, AIIDE, 19, 1)
479 FIELD(AFIR_REGISTER, AIID_EXT, 1, 18)
480 FIELD(AFIR_REGISTER, AIRTR, 0, 1)
483 FIELD(TXE_FIFO_TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
484 FIELD(TXE_FIFO_TB_ID_REGISTER, IDE, 19, 1)
485 FIELD(TXE_FIFO_TB_ID_REGISTER, ID_EXT, 1, 18)
486 FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1)
489 FIELD(TXE_FIFO_TB_DLC_REGISTER, FDF, 27, 1)
490 FIELD(TXE_FIFO_TB_DLC_REGISTER, BRS, 26, 1)
496 FIELD(RB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
497 FIELD(RB_ID_REGISTER, IDE, 19, 1)
498 FIELD(RB_ID_REGISTER, ID_EXT, 1, 18)
499 FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1)
502 FIELD(RB_DLC_REGISTER, FDF, 27, 1)
503 FIELD(RB_DLC_REGISTER, BRS, 26, 1)
504 FIELD(RB_DLC_REGISTER, ESI, 25, 1)
589 FIELD(RB_ID_REGISTER_1, SRR_RTR_RRS, 20, 1)
590 FIELD(RB_ID_REGISTER_1, IDE, 19, 1)
591 FIELD(RB_ID_REGISTER_1, ID_EXT, 1, 18)
592 FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1)
595 FIELD(RB_DLC_REGISTER_1, FDF, 27, 1)
596 FIELD(RB_DLC_REGISTER_1, BRS, 26, 1)
597 FIELD(RB_DLC_REGISTER_1, ESI, 25, 1)
683 const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] & in canfd_update_irq()
684 s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0; in canfd_update_irq()
688 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) > in canfd_update_irq()
689 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) { in canfd_update_irq()
690 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); in canfd_update_irq()
693 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) > in canfd_update_irq()
694 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) { in canfd_update_irq()
695 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1); in canfd_update_irq()
699 if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) > in canfd_update_irq()
700 ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) { in canfd_update_irq()
701 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1); in canfd_update_irq()
704 trace_xlnx_canfd_update_irq(path, s->regs[R_INTERRUPT_STATUS_REGISTER], in canfd_update_irq()
705 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq); in canfd_update_irq()
707 qemu_set_irq(s->irq_canfd_int, irq); in canfd_update_irq()
712 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_ier_post_write()
719 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_icr_pre_write()
722 s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val; in canfd_icr_pre_write()
728 if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) { in canfd_icr_pre_write()
729 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0); in canfd_icr_pre_write()
744 register_reset(&s->reg_info[i]); in canfd_config_reset()
752 register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); in canfd_config_mode()
753 register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); in canfd_config_mode()
754 register_reset(&s->reg_info[R_STATUS_REGISTER]); in canfd_config_mode()
757 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in canfd_config_mode()
758 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); in canfd_config_mode()
759 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); in canfd_config_mode()
760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); in canfd_config_mode()
761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0); in canfd_config_mode()
762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0); in canfd_config_mode()
763 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0); in canfd_config_mode()
764 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); in canfd_config_mode()
765 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); in canfd_config_mode()
766 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); in canfd_config_mode()
769 ptimer_transaction_begin(s->canfd_timer); in canfd_config_mode()
770 ptimer_set_count(s->canfd_timer, 0); in canfd_config_mode()
771 ptimer_transaction_commit(s->canfd_timer); in canfd_config_mode()
778 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); in update_status_register_mode_bits()
779 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); in update_status_register_mode_bits()
786 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); in update_status_register_mode_bits()
787 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); in update_status_register_mode_bits()
788 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); in update_status_register_mode_bits()
789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); in update_status_register_mode_bits()
792 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { in update_status_register_mode_bits()
793 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); in update_status_register_mode_bits()
794 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { in update_status_register_mode_bits()
795 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); in update_status_register_mode_bits()
796 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, in update_status_register_mode_bits()
798 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { in update_status_register_mode_bits()
799 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); in update_status_register_mode_bits()
802 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); in update_status_register_mode_bits()
804 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, in update_status_register_mode_bits()
809 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1); in update_status_register_mode_bits()
816 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_msr_pre_write()
828 if (multi_mode > 1) { in canfd_msr_pre_write()
834 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_msr_pre_write()
836 s->regs[R_MODE_SELECT_REGISTER] = val; in canfd_msr_pre_write()
840 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit); in canfd_msr_pre_write()
853 return s->regs[R_MODE_SELECT_REGISTER]; in canfd_msr_pre_write()
858 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); in canfd_exit_sleep_mode()
873 frame->flags = 0; in regs2frame()
877 s->cfg.tx_fifo)); in regs2frame()
879 dlc_reg_val = s->regs[reg_num + 1]; in regs2frame()
882 id_reg_val = s->regs[reg_num]; in regs2frame()
884 frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) | in regs2frame()
891 frame->can_id = FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID); in regs2frame()
898 frame->flags |= QEMU_CAN_FRMF_TYPE_FD; in regs2frame()
901 frame->flags |= QEMU_CAN_FRMF_BRS; in regs2frame()
905 frame->can_id |= QEMU_CAN_RTR_FLAG; in regs2frame()
909 frame->can_dlc = can_dlc2len(dlc_value); in regs2frame()
911 for (j = 0; j < frame->can_dlc; j++) { in regs2frame()
912 val = 8 * (3 - i); in regs2frame()
914 frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8); in regs2frame()
925 uint32_t clear_mask = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] & in process_cancellation_requests()
926 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER]; in process_cancellation_requests()
928 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &= ~clear_mask; in process_cancellation_requests()
929 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] &= ~clear_mask; in process_cancellation_requests()
937 const bool is_canfd_frame = frame->flags & QEMU_CAN_FRMF_TYPE_FD; in frame_to_reg_id()
938 const bool is_rtr = !is_canfd_frame && (frame->can_id & QEMU_CAN_RTR_FLAG); in frame_to_reg_id()
940 if (frame->can_id & QEMU_CAN_EFF_FLAG) { in frame_to_reg_id()
942 (frame->can_id & QEMU_CAN_EFF_MASK) >> 18); in frame_to_reg_id()
944 frame->can_id & QEMU_CAN_EFF_MASK); in frame_to_reg_id()
945 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1); in frame_to_reg_id()
946 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
948 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1); in frame_to_reg_id()
952 frame->can_id & QEMU_CAN_SFF_MASK); in frame_to_reg_id()
954 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
968 uint8_t dlc = frame->can_dlc; in store_rx_sequential()
973 /* Getting RX0/1 fill level */ in store_rx_sequential()
974 if ((fill_level) > rx_fifo - 1) { in store_rx_sequential()
982 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 1); in store_rx_sequential()
984 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 1); in store_rx_sequential()
987 uint16_t rx_timestamp = CANFD_TIMER_MAX - in store_rx_sequential()
988 ptimer_get_count(s->canfd_timer); in store_rx_sequential()
991 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 1); in store_rx_sequential()
993 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, in store_rx_sequential()
998 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, in store_rx_sequential()
999 fill_level + 1); in store_rx_sequential()
1001 R_RB_ID_REGISTER + (s->cfg.rx0_fifo * in store_rx_sequential()
1004 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, in store_rx_sequential()
1005 fill_level + 1); in store_rx_sequential()
1007 R_RB_ID_REGISTER_1 + (s->cfg.rx1_fifo * in store_rx_sequential()
1011 s->regs[store_location] = frame_to_reg_id(frame); in store_rx_sequential()
1015 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { in store_rx_sequential()
1016 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1); in store_rx_sequential()
1018 if (frame->flags & QEMU_CAN_FRMF_BRS) { in store_rx_sequential()
1019 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); in store_rx_sequential()
1021 if (frame->flags & QEMU_CAN_FRMF_ESI) { in store_rx_sequential()
1022 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); in store_rx_sequential()
1029 s->regs[store_location + 1] = dlc_reg_val; in store_rx_sequential()
1032 /* Register size is 4 byte but frame->data each is 1 byte. */ in store_rx_sequential()
1038 frame->data[i]); in store_rx_sequential()
1040 case 1: in store_rx_sequential()
1042 frame->data[i]); in store_rx_sequential()
1046 frame->data[i]); in store_rx_sequential()
1050 frame->data[i]); in store_rx_sequential()
1055 s->regs[store_location + rx_reg_num + 2] = data_reg_val; in store_rx_sequential()
1065 s->regs[store_location + rx_reg_num + 2] = data_reg_val; in store_rx_sequential()
1069 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); in store_rx_sequential()
1079 int filter_partition = ARRAY_FIELD_EX32(s->regs, in update_rx_sequential()
1090 if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) { in update_rx_sequential()
1092 s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]; in update_rx_sequential()
1097 uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] & in update_rx_sequential()
1099 uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] & in update_rx_sequential()
1100 s->regs[R_AFMR_REGISTER + 2 * i]; in update_rx_sequential()
1111 bool ext_ide = FIELD_EX32(s->regs[R_AFMR_REGISTER + 2 * i], in update_rx_sequential()
1132 acceptance_filter_status >>= 1; in update_rx_sequential()
1139 trace_xlnx_canfd_rx_fifo_filter_reject(path, frame->can_id, in update_rx_sequential()
1140 frame->can_dlc); in update_rx_sequential()
1143 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL); in update_rx_sequential()
1144 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI); in update_rx_sequential()
1147 if (store_index > s->cfg.rx0_fifo - 1) { in update_rx_sequential()
1148 store_index -= s->cfg.rx0_fifo; in update_rx_sequential()
1155 store_location, s->cfg.rx0_fifo, 0, in update_rx_sequential()
1158 /* RX 1 fill level message */ in update_rx_sequential()
1159 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, in update_rx_sequential()
1161 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, in update_rx_sequential()
1165 if (store_index > s->cfg.rx1_fifo - 1) { in update_rx_sequential()
1166 store_index -= s->cfg.rx1_fifo; in update_rx_sequential()
1173 store_location, s->cfg.rx1_fifo, 1, in update_rx_sequential()
1179 trace_xlnx_canfd_rx_data(path, frame->can_id, frame->can_dlc, in update_rx_sequential()
1180 frame->flags); in update_rx_sequential()
1187 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { in tx_ready_check()
1196 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in tx_ready_check()
1206 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { in tx_ready_check()
1226 if (FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, EFC)) { in tx_fifo_stamp()
1227 uint8_t dlc_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, in tx_fifo_stamp()
1229 bool fdf_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, in tx_fifo_stamp()
1231 bool brs_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, in tx_fifo_stamp()
1233 uint8_t mm_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, in tx_fifo_stamp()
1235 uint8_t fill_level = ARRAY_FIELD_EX32(s->regs, in tx_fifo_stamp()
1238 uint8_t read_index = ARRAY_FIELD_EX32(s->regs, in tx_fifo_stamp()
1243 if ((fill_level) > s->cfg.tx_fifo - 1) { in tx_fifo_stamp()
1246 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1); in tx_fifo_stamp()
1248 if (store_index > s->cfg.tx_fifo - 1) { in tx_fifo_stamp()
1249 store_index -= s->cfg.tx_fifo; in tx_fifo_stamp()
1252 assert(store_index < s->cfg.tx_fifo); in tx_fifo_stamp()
1258 s->regs[tx_event_reg0_id] = s->regs[tb0_regid]; in tx_fifo_stamp()
1260 uint16_t tx_timestamp = CANFD_TIMER_MAX - in tx_fifo_stamp()
1261 ptimer_get_count(s->canfd_timer); in tx_fifo_stamp()
1273 s->regs[tx_event_reg0_id + 1] = dlc_reg_val; in tx_fifo_stamp()
1275 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, in tx_fifo_stamp()
1276 fill_level + 1); in tx_fifo_stamp()
1286 if (tx_reg_1->can_id == tx_reg_2->can_id) { in g_cmp_ids()
1287 return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1; in g_cmp_ids()
1289 return (tx_reg_1->can_id < tx_reg_2->can_id) ? -1 : 1; in g_cmp_ids()
1296 for (iterator = list; iterator != NULL; iterator = iterator->next) { in free_list()
1297 g_free((tx_ready_reg_info *)iterator->data); in free_list()
1308 uint32_t reg_ready = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER]; in prepare_tx_data()
1311 for (i = 0; i < s->cfg.tx_fifo; i++) { in prepare_tx_data()
1312 if (reg_ready & 1) { in prepare_tx_data()
1314 tx_ready_reg_info *temp = g_new(tx_ready_reg_info, 1); in prepare_tx_data()
1316 temp->can_id = s->regs[reg_num]; in prepare_tx_data()
1317 temp->reg_num = reg_num; in prepare_tx_data()
1322 reg_ready >>= 1; in prepare_tx_data()
1325 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0; in prepare_tx_data()
1326 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0; in prepare_tx_data()
1350 for (iterator = list; iterator != NULL; iterator = iterator->next) { in transfer_data()
1352 ((tx_ready_reg_info *)iterator->data)->reg_num); in transfer_data()
1354 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { in transfer_data()
1356 tx_fifo_stamp(s, ((tx_ready_reg_info *)iterator->data)->reg_num); in transfer_data()
1358 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); in transfer_data()
1364 can_bus_client_send(&s->bus_client, &frame, 1); in transfer_data()
1366 ((tx_ready_reg_info *)iterator->data)->reg_num); in transfer_data()
1368 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXRRS, 1); in transfer_data()
1370 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { in transfer_data()
1376 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); in transfer_data()
1384 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_srr_pre_write()
1387 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, in canfd_srr_pre_write()
1397 } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_srr_pre_write()
1405 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); in canfd_srr_pre_write()
1407 ptimer_transaction_begin(s->canfd_timer); in canfd_srr_pre_write()
1408 ptimer_set_count(s->canfd_timer, 0); in canfd_srr_pre_write()
1409 ptimer_transaction_commit(s->canfd_timer); in canfd_srr_pre_write()
1414 return s->regs[R_SOFTWARE_RESET_REGISTER]; in canfd_srr_pre_write()
1419 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in filter_mask()
1420 uint32_t reg_idx = (reg->access->addr) / 4; in filter_mask()
1422 uint32_t filter_offset = (reg_idx - R_AFMR_REGISTER) / 2; in filter_mask()
1424 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & in filter_mask()
1425 (1 << filter_offset))) { in filter_mask()
1426 s->regs[reg_idx] = val; in filter_mask()
1431 path, filter_offset + 1); in filter_mask()
1434 return s->regs[reg_idx]; in filter_mask()
1439 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in filter_id()
1440 hwaddr reg_idx = (reg->access->addr) / 4; in filter_id()
1442 uint32_t filter_offset = (reg_idx - R_AFIR_REGISTER) / 2; in filter_id()
1444 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & in filter_id()
1445 (1 << filter_offset))) { in filter_id()
1446 s->regs[reg_idx] = val; in filter_id()
1451 path, filter_offset + 1); in filter_id()
1454 return s->regs[reg_idx]; in filter_id()
1459 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_tx_fifo_status_prew()
1462 uint8_t fill_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, in canfd_tx_fifo_status_prew()
1466 read_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, in canfd_tx_fifo_status_prew()
1467 TXE_RI) + 1; in canfd_tx_fifo_status_prew()
1469 if (read_ind > s->cfg.tx_fifo - 1) { in canfd_tx_fifo_status_prew()
1474 * Increase the read index by 1 and decrease the fill level by 1. in canfd_tx_fifo_status_prew()
1476 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, in canfd_tx_fifo_status_prew()
1478 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, in canfd_tx_fifo_status_prew()
1479 fill_ind - 1); in canfd_tx_fifo_status_prew()
1482 return s->regs[R_TX_EVENT_FIFO_STATUS_REGISTER]; in canfd_tx_fifo_status_prew()
1487 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_rx_fifo_status_prew()
1495 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI) + 1; in canfd_rx_fifo_status_prew()
1497 if (read_ind > s->cfg.rx0_fifo - 1) { in canfd_rx_fifo_status_prew()
1501 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) - 1; in canfd_rx_fifo_status_prew()
1503 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, read_ind); in canfd_rx_fifo_status_prew()
1504 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, fill_ind); in canfd_rx_fifo_status_prew()
1511 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI_1) + 1; in canfd_rx_fifo_status_prew()
1513 if (read_ind > s->cfg.rx1_fifo - 1) { in canfd_rx_fifo_status_prew()
1517 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) - 1; in canfd_rx_fifo_status_prew()
1519 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, read_ind); in canfd_rx_fifo_status_prew()
1520 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, fill_ind); in canfd_rx_fifo_status_prew()
1524 return s->regs[R_RX_FIFO_STATUS_REGISTER]; in canfd_rx_fifo_status_prew()
1529 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_tsr_pre_write()
1533 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0); in canfd_tsr_pre_write()
1534 ptimer_transaction_begin(s->canfd_timer); in canfd_tsr_pre_write()
1535 ptimer_set_count(s->canfd_timer, 0); in canfd_tsr_pre_write()
1536 ptimer_transaction_commit(s->canfd_timer); in canfd_tsr_pre_write()
1544 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_trr_reg_prew()
1546 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { in canfd_trr_reg_prew()
1559 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_trr_reg_postw()
1566 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_cancel_reg_postw()
1573 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); in canfd_write_check_prew()
1576 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_write_check_prew()
1785 for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) { in canfd_reset()
1786 register_reset(&s->reg_info[i]); in canfd_reset()
1789 ptimer_transaction_begin(s->canfd_timer); in canfd_reset()
1790 ptimer_set_count(s->canfd_timer, 0); in canfd_reset()
1791 ptimer_transaction_commit(s->canfd_timer); in canfd_reset()
1799 bool reset_state = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST); in can_xilinx_canfd_receive()
1800 bool can_enabled = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN); in can_xilinx_canfd_receive()
1815 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { in canfd_xilinx_receive()
1820 return 1; in canfd_xilinx_receive()
1824 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1); in canfd_xilinx_receive()
1826 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { in canfd_xilinx_receive()
1830 if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { in canfd_xilinx_receive()
1842 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0); in canfd_xilinx_receive()
1843 return 1; in canfd_xilinx_receive()
1854 s->bus_client.info = &canfd_xilinx_bus_client_info; in xlnx_canfd_connect_to_bus()
1856 return can_bus_insert_client(bus, &s->bus_client); in xlnx_canfd_connect_to_bus()
1873 RegisterInfo *r = &s->reg_info[index]; in canfd_populate_regarray()
1878 .data = &s->regs[index], in canfd_populate_regarray()
1884 r_array->r[i + pos] = r; in canfd_populate_regarray()
1921 s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE + in canfd_create_regarray()
1922 s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE + in canfd_create_regarray()
1926 s->tx_regs = g_new0(RegisterAccessInfo, in canfd_create_regarray()
1927 s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs)); in canfd_create_regarray()
1929 canfd_create_rai(s->tx_regs, canfd_tx_regs, in canfd_create_regarray()
1930 ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo); in canfd_create_regarray()
1932 s->rx0_regs = g_new0(RegisterAccessInfo, in canfd_create_regarray()
1933 s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs)); in canfd_create_regarray()
1935 canfd_create_rai(s->rx0_regs, canfd_rx0_regs, in canfd_create_regarray()
1936 ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo); in canfd_create_regarray()
1938 s->af_regs = g_new0(RegisterAccessInfo, in canfd_create_regarray()
1941 canfd_create_rai(s->af_regs, canfd_af_regs, in canfd_create_regarray()
1944 s->txe_regs = g_new0(RegisterAccessInfo, in canfd_create_regarray()
1947 canfd_create_rai(s->txe_regs, canfd_txe_regs, in canfd_create_regarray()
1950 if (s->cfg.enable_rx_fifo1) { in canfd_create_regarray()
1951 num_regs += s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE; in canfd_create_regarray()
1953 s->rx1_regs = g_new0(RegisterAccessInfo, in canfd_create_regarray()
1954 s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs)); in canfd_create_regarray()
1956 canfd_create_rai(s->rx1_regs, canfd_rx1_regs, in canfd_create_regarray()
1957 ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo); in canfd_create_regarray()
1960 r_array = g_new0(RegisterInfoArray, 1); in canfd_create_regarray()
1961 r_array->r = g_new0(RegisterInfo * , num_regs); in canfd_create_regarray()
1962 r_array->num_elements = num_regs; in canfd_create_regarray()
1963 r_array->prefix = device_prefix; in canfd_create_regarray()
1969 s->tx_regs, s->cfg.tx_fifo * in canfd_create_regarray()
1972 s->rx0_regs, s->cfg.rx0_fifo * in canfd_create_regarray()
1974 if (s->cfg.enable_rx_fifo1) { in canfd_create_regarray()
1976 s->rx1_regs, s->cfg.rx1_fifo * in canfd_create_regarray()
1980 s->af_regs, NUM_AF * NUM_REG_PER_AF); in canfd_create_regarray()
1982 s->txe_regs, NUM_TXE * NUM_REG_PER_TXE); in canfd_create_regarray()
1984 memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array, in canfd_create_regarray()
1995 memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); in canfd_realize()
1996 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in canfd_realize()
1997 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int); in canfd_realize()
1999 if (s->canfdbus) { in canfd_realize()
2000 if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) { in canfd_realize()
2010 s->canfd_timer = ptimer_init(xlnx_versal_canfd_ptimer_cb, s, in canfd_realize()
2015 ptimer_transaction_begin(s->canfd_timer); in canfd_realize()
2017 ptimer_set_freq(s->canfd_timer, s->cfg.ext_clk_freq); in canfd_realize()
2018 ptimer_set_limit(s->canfd_timer, CANFD_TIMER_MAX, 1); in canfd_realize()
2019 ptimer_run(s->canfd_timer, 0); in canfd_realize()
2020 ptimer_transaction_commit(s->canfd_timer); in canfd_realize()
2027 memory_region_init(&s->iomem, obj, TYPE_XILINX_CANFD, in canfd_init()
2033 .version_id = 1,
2034 .minimum_version_id = 1,
2044 DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40),
2045 DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40),
2046 DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20),
2047 DEFINE_PROP_BOOL("enable-rx-fifo1", XlnxVersalCANFDState,
2060 dc->realize = canfd_realize; in canfd_class_init()
2062 dc->vmsd = &vmstate_canfd; in canfd_class_init()