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/qemu/.gitlab-ci.d/
H A Dcrossbuilds.yml2 - local: '/.gitlab-ci.d/crossbuild-template.yml'
4 cross-armhf-user:
7 job: armhf-debian-cross-container
9 IMAGE: debian-armhf-cross
11 cross-arm64-system:
14 job: arm64-debian-cross-container
16 IMAGE: debian-arm64-cross
18 cross-arm64-user:
21 job: arm64-debian-cross-container
23 IMAGE: debian-arm64-cross
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H A Dcrossbuild-template.yml7 - ccache
12 - source scripts/ci/gitlab-ci-section
13 - section_start setup "Pre-script setup"
14 - JOBS=$(expr $(nproc) + 1)
15 - cat /packages.txt
16 - section_end setup
18 - export CCACHE_BASEDIR="$(pwd)"
19 - export CCACHE_DIR="$CCACHE_BASEDIR/ccache"
20 - export CCACHE_MAXSIZE="500M"
21 - export PATH="$CCACHE_WRAPPERSDIR:$PATH"
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H A Dbuildtest.yml2 - local: '/.gitlab-ci.d/buildtest-template.yml'
4 build-system-alpine:
6 - .native_build_job_template
7 - .native_build_artifact_template
9 - job: amd64-alpine-container
12 TARGETS: avr-softmmu loongarch64-softmmu mips64-softmmu mipsel-softmmu
13 MAKE_CHECK_ARGS: check-build
14 CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
16 check-system-alpine:
19 - job: build-system-alpine
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/qemu/docs/system/arm/
H A Dcpu-features.rst10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
11 architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
18 that implement the ARMv8-A architecture reference manual may optionally
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
21 not implement ARMv8-A, will not have the ``aarch64`` CPU property.
27 when using the KVM accelerator and when running on a host CPU type that
28 supports the feature. While ``aarch64`` currently only works with KVM,
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H A Dvirt.rst1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - Flash memory
35 - Either one or two PL011 UARTs for the NonSecure World
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/qemu/tests/qtest/
H A Darm-cpu-features.c9 * See the COPYING file in the top-level directory.
18 * We expect the SVE max-vq to be 16. Also it must be <= 64
23 #define MACHINE "-machine virt,gic-version=max -accel tcg "
24 #define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
25 #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
191 resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', " in assert_type_full()
207 resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', " in assert_bad_props()
234 if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) && in resp_get_sve_vls()
235 g_ascii_isdigit(e->key[3])) { in resp_get_sve_vls()
239 bits = g_ascii_strtoll(&e->key[3], &endptr, 10); in resp_get_sve_vls()
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/qemu/docs/system/i386/
H A Dmicrovm.rst8 designed for short-lived guests. microvm also establishes a baseline
14 -----------------
18 - ISA bus
19 - i8259 PIC (optional)
20 - i8254 PIT (optional)
21 - MC146818 RTC (optional)
22 - One ISA serial port (optional)
23 - LAPIC
24 - IOAPIC (with kernel-irqchip=split by default)
25 - kvmclock (if using KVM)
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H A Dtdx.rst5 Virtual Machine Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME)
12 -------------
15 while KVM hypervisor has TDX support and has TDX enabled. If those requirements
25 KVM vcpu ioctl ``KVM_TDX_INIT_MEM_REGION`` can be used to populate the TDVF
29 device and it actually works as RAM. "-bios" option is chosen to load TDVF.
32 command line to specify and load TDVF is ``-bios OVMF.fd``
35 ---------------------
37 Unlike non-TDX VM, the CPU features (enumerated by CPU or MSR) of a TD are not
43 - Attributes:
44 - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to TD,
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H A Dhyperv.rst1 Hyper-V Enlightenments
6 -----------
8 In some cases when implementing a hardware interface in software is slow, KVM
11 It may, however, be hard-to-impossible to add support for these interfaces to
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
20 -----
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
25 .. parsed-literal::
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/qemu/docs/devel/
H A Dtracing.rst19 $ qemu --trace "memory_region_ops_*" ...
25 ``./configure --enable-trace-backends=BACKENDS`` was not explicitly specified.
27 Multiple patterns can be specified by repeating the ``--trace`` option::
29 $ qemu --trace "kvm_*" --trace "virtio_*" ...
32 file to avoid long command-line options::
36 $ qemu --trace events=/tmp/events ...
41 Sub-directory setup
42 -------------------
45 "trace-events" file. All directories which contain "trace-events" files must be
47 file. During build, the "trace-events" file in each listed subdirectory will be
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H A Dkconfig.rst13 SCSI adapters. Arm, s390 and x86 boards can all present a virtio-blk
21 QEMU uses a simple domain-specific language to describe the dependencies
36 This domain-specific language is based on the Kconfig language that
41 is instead specified in per-target files under the ``configs/``
48 --------------------
78 include it for clarity and future-proofing. After ``bool`` the following
136 ------------------------------------
189 Device groups provide a convenient mechanism to enable/disable many
199 for example only VFIO (passthrough) and virtio-pci devices.
202 board (and not ones which are very board-specific or that need
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/qemu/target/arm/
H A Dcpu64.c18 * <http://www.gnu.org/licenses/gpl-2.0.html>
27 #include "system/kvm.h"
34 #include "hw/qdev-properties.h"
36 #include "cpu-features.h"
43 * then all other lengths are implicitly disabled. If sve-max-vq is in arm_cpu_sve_finalize()
47 * are enabled and sve-max-vq is not specified, then all lengths not in arm_cpu_sve_finalize()
48 * explicitly disabled will be enabled. Additionally, all power-of-two in arm_cpu_sve_finalize()
51 * disabled power-of-two vector length will be automatically disabled. in arm_cpu_sve_finalize()
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
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/qemu/linux-headers/asm-mips/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
18 * KVM MIPS specific structures and definitions.
28 * If Config[AT] is zero (32-bit CPU), the register contents are
29 * stored in the lower 32-bits of the struct kvm_regs fields and sign
30 * extended to 64-bits.
51 * bits[63..52] - As per linux/kvm.h
52 * bits[51..32] - Must be zero.
53 * bits[31..16] - Register set.
58 * bits[15..8] - COP0 register set.
61 * bits[7..3] - Register 'rd' index.
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/qemu/scripts/
H A Dmeson-buildoptions.sh1 # This file is generated by meson-buildoptions.py, do not edit!
3 printf "%s\n" ' --audio-drv-list=CHOICES Set audio driver list [default] (choices: alsa/co'
6 printf "%s\n" ' --bindir=VALUE Executable directory [bin]'
7 printf "%s\n" ' --block-drv-ro-whitelist=VALUE'
8 printf "%s\n" ' set block driver read-only whitelist (by default'
9 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
10 printf "%s\n" ' --block-drv-rw-whitelist=VALUE'
11 printf "%s\n" ' set block driver read-write whitelist (by default'
12 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
13 printf "%s\n" ' --datadir=VALUE Data file directory [share]'
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/qemu/hw/i386/kvm/
H A Di8254.c2 * KVM in-kernel PIT (i8254) support
4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include <linux/kvm.h>
28 #include "qapi/qapi-types-machine.h"
35 #include "hw/qdev-properties-system.h"
36 #include "system/kvm.h"
37 #include "target/i386/kvm/kvm_i386.h"
78 offset -= ts.tv_nsec; in kvm_pit_update_clock_offset()
79 offset -= (int64_t)ts.tv_sec * 1000000000; in kvm_pit_update_clock_offset()
84 s->kernel_clock_offset = clock_offset; in kvm_pit_update_clock_offset()
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/qemu/
H A D.travis.yml5 - gcc
9 # - OS name (currently only linux)
10 # - OS distribution (e.g. "jammy" for Linux)
11 # - Names and values of visible environment variables set in .travis.yml or Settings panel
19 # $ travis encrypt -r "qemu/qemu" "irc.oftc.net#qemu"
23 …- secure: "F7GDRgjuOo5IUyRLqSkmDL7kvdU4UcH3Lm/W2db2JnDHTGCqgEdaYEYKciyCLZ57vOTsTsOgesN8iUT7hNHBd1K…
30 - SRC_DIR=".."
31 - BUILD_DIR="build"
32 - BASE_CONFIG="--disable-docs --disable-tools"
33 - TEST_BUILD_CMD=""
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/qemu/target/loongarch/kvm/
H A Dkvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU LoongArch KVM
10 #include <linux/kvm.h>
11 #include "asm-loongarch/kvm_para.h"
14 #include "qemu/error-report.h"
15 #include "qemu/main-loop.h"
17 #include "system/kvm.h"
21 #include "system/address-spaces.h"
28 #include "cpu-csr.h"
45 .addr = (uint64_t)&env->stealtime.guest_addr, in kvm_get_stealtime()
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/qemu/tests/functional/
H A Dtest_intel_iommu.py11 # later. See the COPYING file in the top-level directory.
30 '/31/Cloud/x86_64/images/Fedora-Cloud-Base-31-1.9.x86_64.qcow2'),
36 IOMMU_ADDON = ',iommu_platform=on,disable-modern=off,disable-legacy=on'
42 self.vm.add_args('-drive', f'file={path},if=none,id=drv0,snapshot=on')
43 self.vm.add_args('-device', 'virtio-blk-pci,bus=pcie.0,' +
44 'drive=drv0,id=virtio-disk0,bootindex=1,'
46 self.vm.add_args('-device', 'virtio-gpu-pci' + self.IOMMU_ADDON)
48 self.vm.add_args('-netdev',
49 'user,id=n1,hostfwd=tcp:127.0.0.1:0-:%d' %
51 self.vm.add_args('-device',
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H A Dtest_aarch64_smmu.py3 # SPDX-License-Identifier: GPL-2.0-or-later
13 # later. See the COPYING file in the top-level directory.
28 IOMMU_ADDON = ',iommu_platform=on,disable-modern=off,disable-legacy=on'
36 self.vm.add_args('-device', 'virtio-blk-pci,bus=pcie.0,' +
37 'drive=drv0,id=virtio-disk0,bootindex=1,'
39 self.vm.add_args('-drive',
42 self.vm.add_args('-netdev',
43 'user,id=n1,hostfwd=tcp:127.0.0.1:0-:%d' %
45 self.vm.add_args('-device', 'virtio-net,netdev=n1' + self.IOMMU_ADDON)
48 self.require_accelerator("kvm")
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/qemu/docs/system/
H A Dcpu-models-x86.rst.inc1 Recommendations for KVM CPU model configuration on x86 hosts
10 Two ways to configure CPU models with QEMU / KVM
16 the guest. Note that KVM may filter out some host CPU model features
51 lists the long term stable CPU model versions (eg Haswell-v4).
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
59 :file: cpu-models-x86-abi.csv
61 :header-rows: 1
77 ``SierraForest``, ``SierraForest-v2``
78 Intel Xeon Processor (SierraForest, 2024), SierraForest-v2 mitigates
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/qemu/hw/xen/
H A Dxen_pt_load_rom.c2 * This is splited from hw/i386/kvm/pci-assign.c
6 #include "qemu/error-report.h"
29 if (dev->romfile || !dev->rom_bar) { in pci_assign_dev_load_option_rom()
41 error_report("pci-assign: Cannot open %s: %s", rom_file, strerror(errno)); in pci_assign_dev_load_option_rom()
45 if (fstat(fileno(fp), &st) == -1) { in pci_assign_dev_load_option_rom()
46 error_report("pci-assign: Cannot stat %s: %s", rom_file, strerror(errno)); in pci_assign_dev_load_option_rom()
56 if (dev->romsize != UINT_MAX) { in pci_assign_dev_load_option_rom()
57 if (st.st_size > dev->romsize) { in pci_assign_dev_load_option_rom()
59 rom_file, (long) st.st_size, dev->romsize); in pci_assign_dev_load_option_rom()
63 dev->romsize = st.st_size; in pci_assign_dev_load_option_rom()
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/qemu/hw/vfio/
H A Dpci.c10 * the COPYING file in the top-level directory.
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
30 #include "hw/qdev-properties.h"
31 #include "hw/qdev-properties-system.h"
34 #include "qemu/error-report.h"
35 #include "qemu/main-loop.h"
39 #include "system/kvm.h"
45 #include "migration/qemu-file.h"
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/qemu/stubs/
H A Dmeson.build5 stub_ss.add(files('cpu-get-clock.c'))
6 stub_ss.add(files('error-printf.c'))
8 stub_ss.add(files('iothread-lock.c'))
9 stub_ss.add(files('is-daemonized.c'))
10 stub_ss.add(files('monitor-core.c'))
11 stub_ss.add(files('replay-mode.c'))
12 stub_ss.add(files('trace-control.c'))
15 stub_ss.add(files('bdrv-next-monitor-owned.c'))
16 stub_ss.add(files('blk-commit-all.c'))
17 stub_ss.add(files('blk-exp-close-all.c'))
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/qemu/hw/arm/
H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
50 #include "system/kvm.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/core/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
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/qemu/docs/specs/
H A Driscv-iommu.rst1 .. _riscv-iommu:
3 RISC-V IOMMU support for RISC-V machines
6 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
9 The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
10 bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
11 RISC-V machine is compatible with both devices.
13 riscv-iommu-pci reference device
14 --------------------------------
16 This device implements the RISC-V IOMMU emulation as recommended by the section
18 class 08h, sub-class 06h and programming interface 00h.
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