Lines Matching +full:- +full:- +full:disable +full:- +full:kvm

10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
11 architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
18 that implement the ARMv8-A architecture reference manual may optionally
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
21 not implement ARMv8-A, will not have the ``aarch64`` CPU property.
27 when using the KVM accelerator and when running on a host CPU type that
28 supports the feature. While ``aarch64`` currently only works with KVM,
29 it could work with TCG. CPU features that are specific to KVM are
30 prefixed with "kvm-" and are described in "KVM VCPU Features".
36 CPU type is possible with the ``query-cpu-model-expansion`` QMP command.
37 Below are some examples where ``scripts/qmp/qmp-shell`` (see the top comment
41 (Note, we started QEMU with qemu-system-aarch64, so ``max`` is
42 implementing the ARMv8-A reference manual in this case)::
44 (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
58 all SVE vector lengths can be supported, when KVM is in use it's more
62 (2) Let's try to disable the PMU::
64 (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
76 (3) Let's try to disable ``aarch64``, which enables the AArch32 CPU feature::
78 (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
81 "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
87 (4) Let's disable ``sve`` and see what happens to all the optional SVE
90 (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
102 (5) Let's try probing CPU features for the Cortex-A15 CPU type::
104 (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
105 {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
110 -------------------------------------
122 A note about CPU models and KVM
123 -------------------------------
125 Named CPU models generally do not work with KVM. There are a few cases
126 that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a
127 seattle host, but mostly if KVM is enabled the ``host`` CPU type must be
135 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. The
138 When KVM is enabled, only the ``max``, ``host``, and current CPU type may be
140 CPU types that may work with KVM, but it does impose a small risk of users
142 above, the ``cortex-a57`` CPU type is also valid when KVM is enabled.
144 then attempt to query ``cortex-a57``, however that query will fail with our
146 users have been preferring the ``host`` CPU type for use with KVM for quite
147 some time. Additionally, if the KVM-enabled QEMU instance running on a
148 seattle host is using the ``cortex-a57`` CPU type, then querying ``cortex-a57``
158 $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
164 defaults, it would seem we need to disable many SVE vector lengths, rather
170 KVM VCPU Features
173 KVM VCPU features are CPU features that are specific to KVM, such as
175 The features' CPU properties are only available when KVM is enabled and
176 are named with the prefix "kvm-". KVM VCPU features may be probed,
178 the list of KVM VCPU features and their descriptions.
180 ``kvm-no-adjvtime``
181 By default kvm-no-adjvtime is disabled. This means that by default
194 Enable kvm-no-adjvtime to disable virtual time adjustment, also
195 restoring the legacy (pre-5.0) behavior.
197 ``kvm-steal-time``
198 Since v5.2, kvm-steal-time is enabled by default when KVM is
199 enabled, the feature is supported, and the guest is 64-bit.
201 When kvm-steal-time is enabled a 64-bit guest can account for time
214 Enable or disable ``FEAT_Pauth`` entirely.
216 ``pauth-impdef``
219 ``pauth-qarma3``
222 ``pauth-qarma5``
225 Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled,
229 non-cryptographic but significantly faster.
235 is used to enable or disable the entire SVE feature, just as the ``pmu``
237 is used to enable or disable specific vector lengths, where ``N`` is the
247 ---------------------------------------------
251 2) If a vector length ``N`` is enabled, then, when KVM is enabled, all
253 KVM is not enabled, then only all the smaller, power-of-two vector
254 lengths must be enabled. E.g. with KVM if the host supports all
255 vector lengths up to 512-bits (128, 256, 384, 512), then if ``sve512``
256 is enabled, the 128-bit vector length, 256-bit vector length, and
257 384-bit vector length must also be enabled. Without KVM, the 384-bit
260 3) If KVM is enabled then only vector lengths that the host CPU type
265 ----------------------------------
278 KVM is not in use means including the non-power-of-two lengths, and,
279 when KVM is in use, it means all vector lengths supported by the host
283 disable the last enabled vector length (see constraint (1) of "SVE
291 5) When KVM is enabled, if the host does not support SVE, then an error
295 6) When KVM is enabled, if the host does support SVE, then an error is
303 When KVM is not enabled, disabling a power-of-two vector length also
304 disables all vector lengths larger than the power-of-two length.
305 When KVM is enabled, then disabling any supported vector length also
312 Dependencies and Constraints", which will even be auto-enabled if
322 -------------------------
324 1) Disable SVE::
326 $ qemu-system-aarch64 -M virt -cpu max,sve=off
330 $ qemu-system-aarch64 -M virt -cpu max
332 3) When KVM is enabled, implicitly enable all host CPU supported vector
335 $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
337 4) Only enable the 128-bit vector length::
339 $ qemu-system-aarch64 -M virt -cpu max,sve128=on
341 5) Disable the 512-bit vector length and all larger vector lengths,
342 since 512 is a power-of-two. This results in all the smaller,
345 $ qemu-system-aarch64 -M virt -cpu max,sve512=off
347 6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
349 $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
351 7) The same as (6), but since the 128-bit and 256-bit vector
352 lengths are required for the 512-bit vector length to be enabled,
353 then allow them to be auto-enabled::
355 $ qemu-system-aarch64 -M virt -cpu max,sve512=on
357 8) Do the same as (7), but by first disabling SVE and then re-enabling it::
359 $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
363 $ qemu-system-aarch64 -M virt -cpu max,sve128=off
364 $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
367 --------------------------------
376 -------------------------
378 1) Disable SME::
380 $ qemu-system-aarch64 -M virt -cpu max,sme=off
384 $ qemu-system-aarch64 -M virt -cpu max
386 3) Only enable the 256-bit vector length::
388 $ qemu-system-aarch64 -M virt -cpu max,sme256=on
390 3) Enable the 256-bit and 1024-bit vector lengths::
392 $ qemu-system-aarch64 -M virt -cpu max,sme256=on,sme1024=on
394 4) Disable the 512-bit vector length. This results in all the other
398 $ qemu-system-aarch64 -M virt -cpu max,sve512=off
400 SVE User-mode Default Vector Length Property
401 --------------------------------------------
403 For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is
413 If this property is set to ``-1`` then the default vector length
420 used to enable or disable the entire SME feature, and ``sme<N>`` is
421 used to enable or disable specific vector lengths. Finally,
422 ``sme_fa64`` is used to enable or disable ``FEAT_SME_FA64``, which
426 SME is not supported by KVM at this time.
433 SME User-mode Default Vector Length Property
434 --------------------------------------------
436 For qemu-aarch64, the cpu property ``sme-default-vector-length=N`` is
442 As with ``sve-default-vector-length``, if the default length is larger
444 be reduced. If this property is set to ``-1`` then the default vector
452 The feature is enabled by the CPU property ``x-rme``, with the ``x-``
459 -----------------------------
462 configurations, ``x-l0gptsz=S`` may be used to specify the value
463 to encode into ``GPCCR_EL3.L0GPTSZ``, a read-only field that
467 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or