Lines Matching +full:- +full:- +full:disable +full:- +full:kvm
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
27 #include "system/kvm.h"
34 #include "hw/qdev-properties.h"
36 #include "cpu-features.h"
43 * then all other lengths are implicitly disabled. If sve-max-vq is in arm_cpu_sve_finalize()
47 * are enabled and sve-max-vq is not specified, then all lengths not in arm_cpu_sve_finalize()
48 * explicitly disabled will be enabled. Additionally, all power-of-two in arm_cpu_sve_finalize()
51 * disabled power-of-two vector length will be automatically disabled. in arm_cpu_sve_finalize()
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
65 * in the supported bitmap results in an error. When KVM is enabled we in arm_cpu_sve_finalize()
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
71 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
77 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
86 max_vq = 32 - clz32(vq_map); in arm_cpu_sve_finalize()
89 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { in arm_cpu_sve_finalize()
92 "length, sve-max-vq=%d (%d bits)\n", in arm_cpu_sve_finalize()
93 max_vq * 128, cpu->sve_max_vq, in arm_cpu_sve_finalize()
94 cpu->sve_max_vq * 128); in arm_cpu_sve_finalize()
100 * For KVM we have to automatically enable all supported uninitialized in arm_cpu_sve_finalize()
101 * lengths, even when the smaller lengths are not all powers-of-two. in arm_cpu_sve_finalize()
105 /* Propagate enabled bits down through required powers-of-two. */ in arm_cpu_sve_finalize()
108 } else if (cpu->sve_max_vq == 0) { in arm_cpu_sve_finalize()
110 * No explicit bits enabled, and no implicit bits from sve-max-vq. in arm_cpu_sve_finalize()
115 * Disable all SVE extensions as well. in arm_cpu_sve_finalize()
117 cpu->isar.id_aa64zfr0 = 0; in arm_cpu_sve_finalize()
125 /* Disabling a power-of-two disables all larger lengths. */ in arm_cpu_sve_finalize()
130 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; in arm_cpu_sve_finalize()
135 error_setg(errp, "cannot disable sve%d", vq * 128); in arm_cpu_sve_finalize()
144 max_vq = 32 - clz32(vq_map); in arm_cpu_sve_finalize()
149 * Process the sve-max-vq property. in arm_cpu_sve_finalize()
151 * sve-max-vq is currently set. in arm_cpu_sve_finalize()
153 if (cpu->sve_max_vq != 0) { in arm_cpu_sve_finalize()
154 max_vq = cpu->sve_max_vq; in arm_cpu_sve_finalize()
157 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { in arm_cpu_sve_finalize()
158 error_setg(errp, "cannot disable sve%d", max_vq * 128); in arm_cpu_sve_finalize()
160 "enabled, sve-max-vq=%d (%d bits)\n", in arm_cpu_sve_finalize()
165 /* Set all bits not explicitly set within sve-max-vq. */ in arm_cpu_sve_finalize()
170 * We should know what max-vq is now. Also, as we're done in arm_cpu_sve_finalize()
171 * manipulating sve-vq-map, we ensure any bits above max-vq in arm_cpu_sve_finalize()
181 vq = 32 - clz32(tmp); in arm_cpu_sve_finalize()
182 if (vq_map & (1 << (vq - 1))) { in arm_cpu_sve_finalize()
183 if (cpu->sve_max_vq) { in arm_cpu_sve_finalize()
184 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); in arm_cpu_sve_finalize()
186 "the vector length %d-bits.\n", vq * 128); in arm_cpu_sve_finalize()
188 "sve-max-vq with this CPU. Try " in arm_cpu_sve_finalize()
194 "the vector length %d-bits.\n", vq * 128); in arm_cpu_sve_finalize()
196 error_append_hint(errp, "SVE not supported by KVM " in arm_cpu_sve_finalize()
203 error_setg(errp, "cannot disable sve%d", vq * 128); in arm_cpu_sve_finalize()
204 error_append_hint(errp, "The KVM host requires all " in arm_cpu_sve_finalize()
210 /* Ensure all required powers-of-two are enabled. */ in arm_cpu_sve_finalize()
213 vq = 32 - clz32(tmp); in arm_cpu_sve_finalize()
214 error_setg(errp, "cannot disable sve%d", vq * 128); in arm_cpu_sve_finalize()
216 "is a power-of-two length smaller " in arm_cpu_sve_finalize()
238 cpu->sve_max_vq = max_vq; in arm_cpu_sve_finalize()
239 cpu->sve_vq.map = vq_map; in arm_cpu_sve_finalize()
253 bool sve = vq_map == &cpu->sve_vq; in cpu_arm_get_vq()
262 value = extract32(vq_map->map, vq - 1, 1); in cpu_arm_get_vq()
278 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); in cpu_arm_set_vq()
279 vq_map->init |= 1 << (vq - 1); in cpu_arm_set_vq()
294 error_setg(errp, "'sve' feature not supported by KVM on this host"); in cpu_arm_set_sve()
298 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_sve()
300 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_sve()
305 uint32_t vq_map = cpu->sme_vq.map; in arm_cpu_sme_finalize()
306 uint32_t vq_init = cpu->sme_vq.init; in arm_cpu_sme_finalize()
307 uint32_t vq_supported = cpu->sme_vq.supported; in arm_cpu_sme_finalize()
312 cpu->isar.id_aa64smfr0 = 0; in arm_cpu_sme_finalize()
316 /* TODO: KVM will require limitations via SMCR_EL2. */ in arm_cpu_sme_finalize()
321 error_setg(errp, "cannot disable sme%d", vq * 128); in arm_cpu_sme_finalize()
329 vq = 32 - clz32(vq_map); in arm_cpu_sme_finalize()
336 /* TODO: KVM will require limitations via SMCR_EL2. */ in arm_cpu_sme_finalize()
339 cpu->sme_vq.map = vq_map; in arm_cpu_sme_finalize()
353 t = cpu->isar.id_aa64pfr1; in cpu_arm_set_sme()
355 cpu->isar.id_aa64pfr1 = t; in cpu_arm_set_sme()
370 t = cpu->isar.id_aa64smfr0; in cpu_arm_set_sme_fa64()
372 cpu->isar.id_aa64smfr0 = t; in cpu_arm_set_sme_fa64()
388 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ in cpu_arm_set_default_vec_len()
389 if (default_len == -1) { in cpu_arm_set_default_vec_len()
404 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); in cpu_arm_set_default_vec_len()
406 error_setg(errp, "cannot set %s-default-vector-length", which); in cpu_arm_set_default_vec_len()
443 cpu_arm_set_vq, NULL, &cpu->sve_vq); in aarch64_add_sve_properties()
448 object_property_add(obj, "sve-default-vector-length", "int32", in aarch64_add_sve_properties()
451 &cpu->sve_default_vq); in aarch64_add_sve_properties()
468 cpu_arm_set_vq, NULL, &cpu->sme_vq); in aarch64_add_sme_properties()
473 object_property_add(obj, "sme-default-vector-length", "int32", in aarch64_add_sme_properties()
476 &cpu->sme_default_vq); in aarch64_add_sme_properties()
486 * These properties enable or disable Pauth as a whole, or change in arm_cpu_pauth_finalize()
493 isar1 = cpu->isar.id_aa64isar1; in arm_cpu_pauth_finalize()
499 isar2 = cpu->isar.id_aa64isar2; in arm_cpu_pauth_finalize()
505 * Exit early if PAuth is enabled and fall through to disable it. in arm_cpu_pauth_finalize()
508 if (cpu->prop_pauth) { in arm_cpu_pauth_finalize()
518 assert(!cpu->prop_pauth); in arm_cpu_pauth_finalize()
522 if (cpu->prop_pauth) { in arm_cpu_pauth_finalize()
523 if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) || in arm_cpu_pauth_finalize()
524 (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) || in arm_cpu_pauth_finalize()
525 (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) { in arm_cpu_pauth_finalize()
527 "cannot enable pauth-impdef, pauth-qarma3 and " in arm_cpu_pauth_finalize()
528 "pauth-qarma5 at the same time"); in arm_cpu_pauth_finalize()
532 bool use_default = !cpu->prop_pauth_qarma5 && in arm_cpu_pauth_finalize()
533 !cpu->prop_pauth_qarma3 && in arm_cpu_pauth_finalize()
534 !cpu->prop_pauth_impdef; in arm_cpu_pauth_finalize()
536 if (cpu->prop_pauth_qarma5 || in arm_cpu_pauth_finalize()
538 cpu->backcompat_pauth_default_use_qarma5)) { in arm_cpu_pauth_finalize()
541 } else if (cpu->prop_pauth_qarma3) { in arm_cpu_pauth_finalize()
544 } else if (cpu->prop_pauth_impdef || in arm_cpu_pauth_finalize()
546 !cpu->backcompat_pauth_default_use_qarma5)) { in arm_cpu_pauth_finalize()
552 } else if (cpu->prop_pauth_impdef || in arm_cpu_pauth_finalize()
553 cpu->prop_pauth_qarma3 || in arm_cpu_pauth_finalize()
554 cpu->prop_pauth_qarma5) { in arm_cpu_pauth_finalize()
555 error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or " in arm_cpu_pauth_finalize()
556 "pauth-qarma5 without pauth"); in arm_cpu_pauth_finalize()
561 cpu->isar.id_aa64isar1 = isar1; in arm_cpu_pauth_finalize()
562 cpu->isar.id_aa64isar2 = isar2; in arm_cpu_pauth_finalize()
568 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
570 DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false);
572 DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false);
583 * property for KVM or hvf. Is it just a bit backward? Yes it is! in aarch64_add_pauth_properties()
586 * provide the separate pauth-impdef property for KVM or hvf, in aarch64_add_pauth_properties()
589 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); in aarch64_add_pauth_properties()
602 * We only install the property for tcg -cpu max; this is the in arm_cpu_lpa2_finalize()
605 if (!cpu->prop_lpa2) { in arm_cpu_lpa2_finalize()
609 t = cpu->isar.id_aa64mmfr0; in arm_cpu_lpa2_finalize()
614 cpu->isar.id_aa64mmfr0 = t; in arm_cpu_lpa2_finalize()
621 cpu->dtb_compatible = "arm,cortex-a57"; in aarch64_a57_initfn()
622 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a57_initfn()
623 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a57_initfn()
624 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a57_initfn()
625 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a57_initfn()
626 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a57_initfn()
627 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a57_initfn()
628 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a57_initfn()
629 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a57_initfn()
630 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a57_initfn()
631 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; in aarch64_a57_initfn()
632 cpu->midr = 0x411fd070; in aarch64_a57_initfn()
633 cpu->revidr = 0x00000000; in aarch64_a57_initfn()
634 cpu->reset_fpsid = 0x41034070; in aarch64_a57_initfn()
635 cpu->isar.mvfr0 = 0x10110222; in aarch64_a57_initfn()
636 cpu->isar.mvfr1 = 0x12111111; in aarch64_a57_initfn()
637 cpu->isar.mvfr2 = 0x00000043; in aarch64_a57_initfn()
638 cpu->ctr = 0x8444c004; in aarch64_a57_initfn()
639 cpu->reset_sctlr = 0x00c50838; in aarch64_a57_initfn()
640 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a57_initfn()
641 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a57_initfn()
642 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a57_initfn()
643 cpu->id_afr0 = 0x00000000; in aarch64_a57_initfn()
644 cpu->isar.id_mmfr0 = 0x10101105; in aarch64_a57_initfn()
645 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a57_initfn()
646 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a57_initfn()
647 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a57_initfn()
648 cpu->isar.id_isar0 = 0x02101110; in aarch64_a57_initfn()
649 cpu->isar.id_isar1 = 0x13112111; in aarch64_a57_initfn()
650 cpu->isar.id_isar2 = 0x21232042; in aarch64_a57_initfn()
651 cpu->isar.id_isar3 = 0x01112131; in aarch64_a57_initfn()
652 cpu->isar.id_isar4 = 0x00011142; in aarch64_a57_initfn()
653 cpu->isar.id_isar5 = 0x00011121; in aarch64_a57_initfn()
654 cpu->isar.id_isar6 = 0; in aarch64_a57_initfn()
655 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a57_initfn()
656 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a57_initfn()
657 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a57_initfn()
658 cpu->isar.id_aa64mmfr0 = 0x00001124; in aarch64_a57_initfn()
659 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a57_initfn()
660 cpu->isar.dbgdevid = 0x01110f13; in aarch64_a57_initfn()
661 cpu->isar.dbgdevid1 = 0x2; in aarch64_a57_initfn()
662 cpu->isar.reset_pmcr_el0 = 0x41013000; in aarch64_a57_initfn()
663 cpu->clidr = 0x0a200023; in aarch64_a57_initfn()
665 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a57_initfn()
667 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); in aarch64_a57_initfn()
669 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); in aarch64_a57_initfn()
670 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a57_initfn()
671 cpu->gic_num_lrs = 4; in aarch64_a57_initfn()
672 cpu->gic_vpribits = 5; in aarch64_a57_initfn()
673 cpu->gic_vprebits = 5; in aarch64_a57_initfn()
674 cpu->gic_pribits = 5; in aarch64_a57_initfn()
682 cpu->dtb_compatible = "arm,cortex-a53"; in aarch64_a53_initfn()
683 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a53_initfn()
684 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a53_initfn()
685 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a53_initfn()
686 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a53_initfn()
687 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a53_initfn()
688 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a53_initfn()
689 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a53_initfn()
690 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a53_initfn()
691 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a53_initfn()
692 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; in aarch64_a53_initfn()
693 cpu->midr = 0x410fd034; in aarch64_a53_initfn()
694 cpu->revidr = 0x00000100; in aarch64_a53_initfn()
695 cpu->reset_fpsid = 0x41034070; in aarch64_a53_initfn()
696 cpu->isar.mvfr0 = 0x10110222; in aarch64_a53_initfn()
697 cpu->isar.mvfr1 = 0x12111111; in aarch64_a53_initfn()
698 cpu->isar.mvfr2 = 0x00000043; in aarch64_a53_initfn()
699 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ in aarch64_a53_initfn()
700 cpu->reset_sctlr = 0x00c50838; in aarch64_a53_initfn()
701 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a53_initfn()
702 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a53_initfn()
703 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a53_initfn()
704 cpu->id_afr0 = 0x00000000; in aarch64_a53_initfn()
705 cpu->isar.id_mmfr0 = 0x10101105; in aarch64_a53_initfn()
706 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a53_initfn()
707 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a53_initfn()
708 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a53_initfn()
709 cpu->isar.id_isar0 = 0x02101110; in aarch64_a53_initfn()
710 cpu->isar.id_isar1 = 0x13112111; in aarch64_a53_initfn()
711 cpu->isar.id_isar2 = 0x21232042; in aarch64_a53_initfn()
712 cpu->isar.id_isar3 = 0x01112131; in aarch64_a53_initfn()
713 cpu->isar.id_isar4 = 0x00011142; in aarch64_a53_initfn()
714 cpu->isar.id_isar5 = 0x00011121; in aarch64_a53_initfn()
715 cpu->isar.id_isar6 = 0; in aarch64_a53_initfn()
716 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a53_initfn()
717 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a53_initfn()
718 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a53_initfn()
719 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ in aarch64_a53_initfn()
720 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a53_initfn()
721 cpu->isar.dbgdevid = 0x00110f13; in aarch64_a53_initfn()
722 cpu->isar.dbgdevid1 = 0x1; in aarch64_a53_initfn()
723 cpu->isar.reset_pmcr_el0 = 0x41033000; in aarch64_a53_initfn()
724 cpu->clidr = 0x0a200023; in aarch64_a53_initfn()
726 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a53_initfn()
728 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); in aarch64_a53_initfn()
730 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); in aarch64_a53_initfn()
731 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a53_initfn()
732 cpu->gic_num_lrs = 4; in aarch64_a53_initfn()
733 cpu->gic_vpribits = 5; in aarch64_a53_initfn()
734 cpu->gic_vprebits = 5; in aarch64_a53_initfn()
735 cpu->gic_pribits = 5; in aarch64_a53_initfn()
744 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in aarch64_host_initfn()
760 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ in aarch64_max_initfn()
769 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ in aarch64_max_initfn()
776 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
777 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },