#
1eb987a8 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VRHADD
Implement the MVE VRHADD insn, which performs a rounded halving addition.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <ri
target/arm: Implement MVE VRHADD
Implement the MVE VRHADD insn, which performs a rounded halving addition.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-40-peter.maydell@linaro.org
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#
43364321 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMULL (vector)
Implement the vector form of the MVE VQDMULL insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henders
target/arm: Implement MVE VQDMULL (vector)
Implement the vector form of the MVE VQDMULL insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-39-peter.maydell@linaro.org
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#
92f11732 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are like VQDMLADH and VQRDMLADH except that products are subtracted rather than added.
Signed-
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are like VQDMLADH and VQRDMLADH except that products are subtracted rather than added.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-38-peter.maydell@linaro.org
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#
fd677f80 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMLADH and VQRDMLADH
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply elements, and then add pairs of products, double, possibly round, saturate and return
target/arm: Implement MVE VQDMLADH and VQRDMLADH
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply elements, and then add pairs of products, double, possibly round, saturate and return the high half of the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-37-peter.maydell@linaro.org
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#
bb002345 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VRSHL
Implement the MVE VRSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Mes
target/arm: Implement MVE VRSHL
Implement the MVE VRSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-36-peter.maydell@linaro.org
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#
0372cad8 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VSHL insn
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
target/arm: Implement MVE VSHL insn
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-35-peter.maydell@linaro.org
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#
9dc868c4 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQRSHL
Implement the MV VQRSHL (vector) insn. Again, the code to perform the actual shifts is borrowed from neon_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@lin
target/arm: Implement MVE VQRSHL
Implement the MV VQRSHL (vector) insn. Again, the code to perform the actual shifts is borrowed from neon_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-34-peter.maydell@linaro.org
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#
483da661 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQSHL (vector)
Implement the MVE VQSHL insn (encoding T4, which is the vector-shift-by-vector version).
The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from the ne
target/arm: Implement MVE VQSHL (vector)
Implement the MVE VQSHL insn (encoding T4, which is the vector-shift-by-vector version).
The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-33-peter.maydell@linaro.org
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#
f741707b |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQADD, VQSUB (vector)
Implement the vector forms of the MVE VQADD and VQSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <
target/arm: Implement MVE VQADD, VQSUB (vector)
Implement the vector forms of the MVE VQADD and VQSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-32-peter.maydell@linaro.org
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#
380caf6c |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard H
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-31-peter.maydell@linaro.org
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#
a8890353 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMULL scalar
Implement the MVE VQDMULL scalar insn. This multiplies the top or bottom half of each element by the scalar, doubles and saturates to a double-width result.
target/arm: Implement MVE VQDMULL scalar
Implement the MVE VQDMULL scalar insn. This multiplies the top or bottom half of each element by the scalar, doubles and saturates to a double-width result.
Note that this encoding overlaps with VQADD and VQSUB; it uses what in VQADD and VQSUB would be the 'size=0b11' encoding.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-30-peter.maydell@linaro.org
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#
66c05767 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply elements by the scalar, double, possibly round, take the high half and sat
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply elements by the scalar, double, possibly round, take the high half and saturate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-29-peter.maydell@linaro.org
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#
39f2ec85 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating addition of a scalar to each element. Note that individual bytes of each result element a
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating addition of a scalar to each element. Note that individual bytes of each result element are used or discarded according to the predicate mask, but FPSCR.QC is only set if the predicate mask for the lowest byte of the element is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-28-peter.maydell@linaro.org
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#
387debdb |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VPST
Implement the MVE VPST insn, which sets the predicate mask fields in the VPR to the immediate value encoded in the insn.
Signed-off-by: Peter Maydell <peter.maydell@l
target/arm: Implement MVE VPST
Implement the MVE VPST insn, which sets the predicate mask fields in the VPR to the immediate value encoded in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-27-peter.maydell@linaro.org
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#
b050543b |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VBRSR
Implement the MVE VBRSR insn, which reverses a specified number of bits in each element, setting the rest to zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro
target/arm: Implement MVE VBRSR
Implement the MVE VBRSR insn, which reverses a specified number of bits in each element, setting the rest to zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-26-peter.maydell@linaro.org
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#
644f717c |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VHADD, VHSUB (scalar)
Implement the scalar variants of the MVE VHADD and VHSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderso
target/arm: Implement MVE VHADD, VHSUB (scalar)
Implement the scalar variants of the MVE VHADD and VHSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-25-peter.maydell@linaro.org
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#
91a358fd |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VSUB, VMUL (scalar)
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rich
target/arm: Implement MVE VSUB, VMUL (scalar)
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-24-peter.maydell@linaro.org
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#
e51896b3 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VADD (scalar)
Implement the scalar form of the MVE VADD insn. This takes the scalar operand from a general purpose register.
Signed-off-by: Peter Maydell <peter.maydell@li
target/arm: Implement MVE VADD (scalar)
Implement the scalar form of the MVE VADD insn. This takes the scalar operand from a general purpose register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-23-peter.maydell@linaro.org
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#
38548747 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate the results of a rounded multiply of pairs of elements into a 72-bit accumulator,
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate the results of a rounded multiply of pairs of elements into a 72-bit accumulator, returning the top 64 bits in a pair of general purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-22-peter.maydell@linaro.org
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#
181cd971 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VMLSLDAV
Implement the MVE insn VMLSLDAV, which multiplies source elements, alternately adding and subtracting them, and accumulates into a 64-bit result in a pair of gener
target/arm: Implement MVE VMLSLDAV
Implement the MVE insn VMLSLDAV, which multiplies source elements, alternately adding and subtracting them, and accumulates into a 64-bit result in a pair of general purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-21-peter.maydell@linaro.org
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#
1d2386f7 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VMLALDAV
Implement the MVE VMLALDAV insn, which multiplies pairs of integer elements, accumulating them into a 64-bit result in a pair of general-purpose registers.
Signed
target/arm: Implement MVE VMLALDAV
Implement the MVE VMLALDAV insn, which multiplies pairs of integer elements, accumulating them into a 64-bit result in a pair of general-purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-20-peter.maydell@linaro.org
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#
ac6ad1dc |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VMULL
Implement the MVE VMULL insn, which multiplies two single width integer elements to produce a double width result.
Signed-off-by: Peter Maydell <peter.maydell@linaro
target/arm: Implement MVE VMULL
Implement the MVE VMULL insn, which multiplies two single width integer elements to produce a double width result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-19-peter.maydell@linaro.org
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#
abc48e31 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VHADD, VHSUB
Implement MVE VHADD and VHSUB insns, which perform an addition or subtraction and then halve the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.or
target/arm: Implement MVE VHADD, VHSUB
Implement MVE VHADD and VHSUB insns, which perform an addition or subtraction and then halve the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-18-peter.maydell@linaro.org
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#
bc67aa8d |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VABD
Implement the MVE VABD insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 2021061
target/arm: Implement MVE VABD
Implement the MVE VABD insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-17-peter.maydell@linaro.org
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#
cd367ff3 |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement MVE VMAX, VMIN
Implement the MVE VMAX and VMIN insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Mes
target/arm: Implement MVE VMAX, VMIN
Implement the MVE VMAX and VMIN insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-16-peter.maydell@linaro.org
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