1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 /* Include the generated decoder */ 29 #include "decode-mve.c.inc" 30 31 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 32 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 33 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 34 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 35 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 36 37 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 38 static inline long mve_qreg_offset(unsigned reg) 39 { 40 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 41 } 42 43 static TCGv_ptr mve_qreg_ptr(unsigned reg) 44 { 45 TCGv_ptr ret = tcg_temp_new_ptr(); 46 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 47 return ret; 48 } 49 50 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 51 { 52 /* 53 * Check whether Qregs are in range. For v8.1M only Q0..Q7 54 * are supported, see VFPSmallRegisterBank(). 55 */ 56 return qmask < 8; 57 } 58 59 static bool mve_eci_check(DisasContext *s) 60 { 61 /* 62 * This is a beatwise insn: check that ECI is valid (not a 63 * reserved value) and note that we are handling it. 64 * Return true if OK, false if we generated an exception. 65 */ 66 s->eci_handled = true; 67 switch (s->eci) { 68 case ECI_NONE: 69 case ECI_A0: 70 case ECI_A0A1: 71 case ECI_A0A1A2: 72 case ECI_A0A1A2B0: 73 return true; 74 default: 75 /* Reserved value: INVSTATE UsageFault */ 76 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 77 default_exception_el(s)); 78 return false; 79 } 80 } 81 82 static void mve_update_eci(DisasContext *s) 83 { 84 /* 85 * The helper function will always update the CPUState field, 86 * so we only need to update the DisasContext field. 87 */ 88 if (s->eci) { 89 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 90 } 91 } 92 93 static bool mve_skip_first_beat(DisasContext *s) 94 { 95 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 96 switch (s->eci) { 97 case ECI_NONE: 98 return false; 99 case ECI_A0: 100 case ECI_A0A1: 101 case ECI_A0A1A2: 102 case ECI_A0A1A2B0: 103 return true; 104 default: 105 g_assert_not_reached(); 106 } 107 } 108 109 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) 110 { 111 TCGv_i32 addr; 112 uint32_t offset; 113 TCGv_ptr qreg; 114 115 if (!dc_isar_feature(aa32_mve, s) || 116 !mve_check_qreg_bank(s, a->qd) || 117 !fn) { 118 return false; 119 } 120 121 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 122 if (a->rn == 15 || (a->rn == 13 && a->w)) { 123 return false; 124 } 125 126 if (!mve_eci_check(s) || !vfp_access_check(s)) { 127 return true; 128 } 129 130 offset = a->imm << a->size; 131 if (!a->a) { 132 offset = -offset; 133 } 134 addr = load_reg(s, a->rn); 135 if (a->p) { 136 tcg_gen_addi_i32(addr, addr, offset); 137 } 138 139 qreg = mve_qreg_ptr(a->qd); 140 fn(cpu_env, qreg, addr); 141 tcg_temp_free_ptr(qreg); 142 143 /* 144 * Writeback always happens after the last beat of the insn, 145 * regardless of predication 146 */ 147 if (a->w) { 148 if (!a->p) { 149 tcg_gen_addi_i32(addr, addr, offset); 150 } 151 store_reg(s, a->rn, addr); 152 } else { 153 tcg_temp_free_i32(addr); 154 } 155 mve_update_eci(s); 156 return true; 157 } 158 159 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 160 { 161 static MVEGenLdStFn * const ldstfns[4][2] = { 162 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 163 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 164 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 165 { NULL, NULL } 166 }; 167 return do_ldst(s, a, ldstfns[a->size][a->l]); 168 } 169 170 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ 171 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 172 { \ 173 static MVEGenLdStFn * const ldstfns[2][2] = { \ 174 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 175 { NULL, gen_helper_mve_##ULD }, \ 176 }; \ 177 return do_ldst(s, a, ldstfns[a->u][a->l]); \ 178 } 179 180 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) 181 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) 182 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) 183 184 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 185 { 186 TCGv_ptr qd; 187 TCGv_i32 rt; 188 189 if (!dc_isar_feature(aa32_mve, s) || 190 !mve_check_qreg_bank(s, a->qd)) { 191 return false; 192 } 193 if (a->rt == 13 || a->rt == 15) { 194 /* UNPREDICTABLE; we choose to UNDEF */ 195 return false; 196 } 197 if (!mve_eci_check(s) || !vfp_access_check(s)) { 198 return true; 199 } 200 201 qd = mve_qreg_ptr(a->qd); 202 rt = load_reg(s, a->rt); 203 tcg_gen_dup_i32(a->size, rt, rt); 204 gen_helper_mve_vdup(cpu_env, qd, rt); 205 tcg_temp_free_ptr(qd); 206 tcg_temp_free_i32(rt); 207 mve_update_eci(s); 208 return true; 209 } 210 211 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 212 { 213 TCGv_ptr qd, qm; 214 215 if (!dc_isar_feature(aa32_mve, s) || 216 !mve_check_qreg_bank(s, a->qd | a->qm) || 217 !fn) { 218 return false; 219 } 220 221 if (!mve_eci_check(s) || !vfp_access_check(s)) { 222 return true; 223 } 224 225 qd = mve_qreg_ptr(a->qd); 226 qm = mve_qreg_ptr(a->qm); 227 fn(cpu_env, qd, qm); 228 tcg_temp_free_ptr(qd); 229 tcg_temp_free_ptr(qm); 230 mve_update_eci(s); 231 return true; 232 } 233 234 #define DO_1OP(INSN, FN) \ 235 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 236 { \ 237 static MVEGenOneOpFn * const fns[] = { \ 238 gen_helper_mve_##FN##b, \ 239 gen_helper_mve_##FN##h, \ 240 gen_helper_mve_##FN##w, \ 241 NULL, \ 242 }; \ 243 return do_1op(s, a, fns[a->size]); \ 244 } 245 246 DO_1OP(VCLZ, vclz) 247 DO_1OP(VCLS, vcls) 248 DO_1OP(VABS, vabs) 249 DO_1OP(VNEG, vneg) 250 251 static bool trans_VREV16(DisasContext *s, arg_1op *a) 252 { 253 static MVEGenOneOpFn * const fns[] = { 254 gen_helper_mve_vrev16b, 255 NULL, 256 NULL, 257 NULL, 258 }; 259 return do_1op(s, a, fns[a->size]); 260 } 261 262 static bool trans_VREV32(DisasContext *s, arg_1op *a) 263 { 264 static MVEGenOneOpFn * const fns[] = { 265 gen_helper_mve_vrev32b, 266 gen_helper_mve_vrev32h, 267 NULL, 268 NULL, 269 }; 270 return do_1op(s, a, fns[a->size]); 271 } 272 273 static bool trans_VREV64(DisasContext *s, arg_1op *a) 274 { 275 static MVEGenOneOpFn * const fns[] = { 276 gen_helper_mve_vrev64b, 277 gen_helper_mve_vrev64h, 278 gen_helper_mve_vrev64w, 279 NULL, 280 }; 281 return do_1op(s, a, fns[a->size]); 282 } 283 284 static bool trans_VMVN(DisasContext *s, arg_1op *a) 285 { 286 return do_1op(s, a, gen_helper_mve_vmvn); 287 } 288 289 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 290 { 291 static MVEGenOneOpFn * const fns[] = { 292 NULL, 293 gen_helper_mve_vfabsh, 294 gen_helper_mve_vfabss, 295 NULL, 296 }; 297 if (!dc_isar_feature(aa32_mve_fp, s)) { 298 return false; 299 } 300 return do_1op(s, a, fns[a->size]); 301 } 302 303 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 304 { 305 static MVEGenOneOpFn * const fns[] = { 306 NULL, 307 gen_helper_mve_vfnegh, 308 gen_helper_mve_vfnegs, 309 NULL, 310 }; 311 if (!dc_isar_feature(aa32_mve_fp, s)) { 312 return false; 313 } 314 return do_1op(s, a, fns[a->size]); 315 } 316 317 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 318 { 319 TCGv_ptr qd, qn, qm; 320 321 if (!dc_isar_feature(aa32_mve, s) || 322 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 323 !fn) { 324 return false; 325 } 326 if (!mve_eci_check(s) || !vfp_access_check(s)) { 327 return true; 328 } 329 330 qd = mve_qreg_ptr(a->qd); 331 qn = mve_qreg_ptr(a->qn); 332 qm = mve_qreg_ptr(a->qm); 333 fn(cpu_env, qd, qn, qm); 334 tcg_temp_free_ptr(qd); 335 tcg_temp_free_ptr(qn); 336 tcg_temp_free_ptr(qm); 337 mve_update_eci(s); 338 return true; 339 } 340 341 #define DO_LOGIC(INSN, HELPER) \ 342 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 343 { \ 344 return do_2op(s, a, HELPER); \ 345 } 346 347 DO_LOGIC(VAND, gen_helper_mve_vand) 348 DO_LOGIC(VBIC, gen_helper_mve_vbic) 349 DO_LOGIC(VORR, gen_helper_mve_vorr) 350 DO_LOGIC(VORN, gen_helper_mve_vorn) 351 DO_LOGIC(VEOR, gen_helper_mve_veor) 352 353 #define DO_2OP(INSN, FN) \ 354 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 355 { \ 356 static MVEGenTwoOpFn * const fns[] = { \ 357 gen_helper_mve_##FN##b, \ 358 gen_helper_mve_##FN##h, \ 359 gen_helper_mve_##FN##w, \ 360 NULL, \ 361 }; \ 362 return do_2op(s, a, fns[a->size]); \ 363 } 364 365 DO_2OP(VADD, vadd) 366 DO_2OP(VSUB, vsub) 367 DO_2OP(VMUL, vmul) 368 DO_2OP(VMULH_S, vmulhs) 369 DO_2OP(VMULH_U, vmulhu) 370 DO_2OP(VRMULH_S, vrmulhs) 371 DO_2OP(VRMULH_U, vrmulhu) 372 DO_2OP(VMAX_S, vmaxs) 373 DO_2OP(VMAX_U, vmaxu) 374 DO_2OP(VMIN_S, vmins) 375 DO_2OP(VMIN_U, vminu) 376 DO_2OP(VABD_S, vabds) 377 DO_2OP(VABD_U, vabdu) 378 DO_2OP(VHADD_S, vhadds) 379 DO_2OP(VHADD_U, vhaddu) 380 DO_2OP(VHSUB_S, vhsubs) 381 DO_2OP(VHSUB_U, vhsubu) 382 DO_2OP(VMULL_BS, vmullbs) 383 DO_2OP(VMULL_BU, vmullbu) 384 DO_2OP(VMULL_TS, vmullts) 385 DO_2OP(VMULL_TU, vmulltu) 386 387 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 388 MVEGenTwoOpScalarFn fn) 389 { 390 TCGv_ptr qd, qn; 391 TCGv_i32 rm; 392 393 if (!dc_isar_feature(aa32_mve, s) || 394 !mve_check_qreg_bank(s, a->qd | a->qn) || 395 !fn) { 396 return false; 397 } 398 if (a->rm == 13 || a->rm == 15) { 399 /* UNPREDICTABLE */ 400 return false; 401 } 402 if (!mve_eci_check(s) || !vfp_access_check(s)) { 403 return true; 404 } 405 406 qd = mve_qreg_ptr(a->qd); 407 qn = mve_qreg_ptr(a->qn); 408 rm = load_reg(s, a->rm); 409 fn(cpu_env, qd, qn, rm); 410 tcg_temp_free_i32(rm); 411 tcg_temp_free_ptr(qd); 412 tcg_temp_free_ptr(qn); 413 mve_update_eci(s); 414 return true; 415 } 416 417 #define DO_2OP_SCALAR(INSN, FN) \ 418 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 419 { \ 420 static MVEGenTwoOpScalarFn * const fns[] = { \ 421 gen_helper_mve_##FN##b, \ 422 gen_helper_mve_##FN##h, \ 423 gen_helper_mve_##FN##w, \ 424 NULL, \ 425 }; \ 426 return do_2op_scalar(s, a, fns[a->size]); \ 427 } 428 429 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 430 431 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 432 MVEGenDualAccOpFn *fn) 433 { 434 TCGv_ptr qn, qm; 435 TCGv_i64 rda; 436 TCGv_i32 rdalo, rdahi; 437 438 if (!dc_isar_feature(aa32_mve, s) || 439 !mve_check_qreg_bank(s, a->qn | a->qm) || 440 !fn) { 441 return false; 442 } 443 /* 444 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 445 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 446 */ 447 if (a->rdahi == 13 || a->rdahi == 15) { 448 return false; 449 } 450 if (!mve_eci_check(s) || !vfp_access_check(s)) { 451 return true; 452 } 453 454 qn = mve_qreg_ptr(a->qn); 455 qm = mve_qreg_ptr(a->qm); 456 457 /* 458 * This insn is subject to beat-wise execution. Partial execution 459 * of an A=0 (no-accumulate) insn which does not execute the first 460 * beat must start with the current rda value, not 0. 461 */ 462 if (a->a || mve_skip_first_beat(s)) { 463 rda = tcg_temp_new_i64(); 464 rdalo = load_reg(s, a->rdalo); 465 rdahi = load_reg(s, a->rdahi); 466 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 467 tcg_temp_free_i32(rdalo); 468 tcg_temp_free_i32(rdahi); 469 } else { 470 rda = tcg_const_i64(0); 471 } 472 473 fn(rda, cpu_env, qn, qm, rda); 474 tcg_temp_free_ptr(qn); 475 tcg_temp_free_ptr(qm); 476 477 rdalo = tcg_temp_new_i32(); 478 rdahi = tcg_temp_new_i32(); 479 tcg_gen_extrl_i64_i32(rdalo, rda); 480 tcg_gen_extrh_i64_i32(rdahi, rda); 481 store_reg(s, a->rdalo, rdalo); 482 store_reg(s, a->rdahi, rdahi); 483 tcg_temp_free_i64(rda); 484 mve_update_eci(s); 485 return true; 486 } 487 488 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 489 { 490 static MVEGenDualAccOpFn * const fns[4][2] = { 491 { NULL, NULL }, 492 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 493 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 494 { NULL, NULL }, 495 }; 496 return do_long_dual_acc(s, a, fns[a->size][a->x]); 497 } 498 499 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 500 { 501 static MVEGenDualAccOpFn * const fns[4][2] = { 502 { NULL, NULL }, 503 { gen_helper_mve_vmlaldavuh, NULL }, 504 { gen_helper_mve_vmlaldavuw, NULL }, 505 { NULL, NULL }, 506 }; 507 return do_long_dual_acc(s, a, fns[a->size][a->x]); 508 } 509 510 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 511 { 512 static MVEGenDualAccOpFn * const fns[4][2] = { 513 { NULL, NULL }, 514 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 515 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 516 { NULL, NULL }, 517 }; 518 return do_long_dual_acc(s, a, fns[a->size][a->x]); 519 } 520 521 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 522 { 523 static MVEGenDualAccOpFn * const fns[] = { 524 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 525 }; 526 return do_long_dual_acc(s, a, fns[a->x]); 527 } 528 529 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 530 { 531 static MVEGenDualAccOpFn * const fns[] = { 532 gen_helper_mve_vrmlaldavhuw, NULL, 533 }; 534 return do_long_dual_acc(s, a, fns[a->x]); 535 } 536 537 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 538 { 539 static MVEGenDualAccOpFn * const fns[] = { 540 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 541 }; 542 return do_long_dual_acc(s, a, fns[a->x]); 543 } 544