xref: /qemu/target/arm/tcg/translate-mve.c (revision 1eb987a89d944515b05ccd8b913bee7fd0d547ae)
1 /*
2  *  ARM translation: M-profile MVE instructions
3  *
4  *  Copyright (c) 2021 Linaro, Ltd.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/exec-all.h"
24 #include "exec/gen-icount.h"
25 #include "translate.h"
26 #include "translate-a32.h"
27 
28 /* Include the generated decoder */
29 #include "decode-mve.c.inc"
30 
31 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
32 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
33 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
34 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
35 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
36 
37 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
38 static inline long mve_qreg_offset(unsigned reg)
39 {
40     return offsetof(CPUARMState, vfp.zregs[reg].d[0]);
41 }
42 
43 static TCGv_ptr mve_qreg_ptr(unsigned reg)
44 {
45     TCGv_ptr ret = tcg_temp_new_ptr();
46     tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
47     return ret;
48 }
49 
50 static bool mve_check_qreg_bank(DisasContext *s, int qmask)
51 {
52     /*
53      * Check whether Qregs are in range. For v8.1M only Q0..Q7
54      * are supported, see VFPSmallRegisterBank().
55      */
56     return qmask < 8;
57 }
58 
59 static bool mve_eci_check(DisasContext *s)
60 {
61     /*
62      * This is a beatwise insn: check that ECI is valid (not a
63      * reserved value) and note that we are handling it.
64      * Return true if OK, false if we generated an exception.
65      */
66     s->eci_handled = true;
67     switch (s->eci) {
68     case ECI_NONE:
69     case ECI_A0:
70     case ECI_A0A1:
71     case ECI_A0A1A2:
72     case ECI_A0A1A2B0:
73         return true;
74     default:
75         /* Reserved value: INVSTATE UsageFault */
76         gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
77                            default_exception_el(s));
78         return false;
79     }
80 }
81 
82 static void mve_update_eci(DisasContext *s)
83 {
84     /*
85      * The helper function will always update the CPUState field,
86      * so we only need to update the DisasContext field.
87      */
88     if (s->eci) {
89         s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE;
90     }
91 }
92 
93 static void mve_update_and_store_eci(DisasContext *s)
94 {
95     /*
96      * For insns which don't call a helper function that will call
97      * mve_advance_vpt(), this version updates s->eci and also stores
98      * it out to the CPUState field.
99      */
100     if (s->eci) {
101         mve_update_eci(s);
102         store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits);
103     }
104 }
105 
106 static bool mve_skip_first_beat(DisasContext *s)
107 {
108     /* Return true if PSR.ECI says we must skip the first beat of this insn */
109     switch (s->eci) {
110     case ECI_NONE:
111         return false;
112     case ECI_A0:
113     case ECI_A0A1:
114     case ECI_A0A1A2:
115     case ECI_A0A1A2B0:
116         return true;
117     default:
118         g_assert_not_reached();
119     }
120 }
121 
122 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
123 {
124     TCGv_i32 addr;
125     uint32_t offset;
126     TCGv_ptr qreg;
127 
128     if (!dc_isar_feature(aa32_mve, s) ||
129         !mve_check_qreg_bank(s, a->qd) ||
130         !fn) {
131         return false;
132     }
133 
134     /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
135     if (a->rn == 15 || (a->rn == 13 && a->w)) {
136         return false;
137     }
138 
139     if (!mve_eci_check(s) || !vfp_access_check(s)) {
140         return true;
141     }
142 
143     offset = a->imm << a->size;
144     if (!a->a) {
145         offset = -offset;
146     }
147     addr = load_reg(s, a->rn);
148     if (a->p) {
149         tcg_gen_addi_i32(addr, addr, offset);
150     }
151 
152     qreg = mve_qreg_ptr(a->qd);
153     fn(cpu_env, qreg, addr);
154     tcg_temp_free_ptr(qreg);
155 
156     /*
157      * Writeback always happens after the last beat of the insn,
158      * regardless of predication
159      */
160     if (a->w) {
161         if (!a->p) {
162             tcg_gen_addi_i32(addr, addr, offset);
163         }
164         store_reg(s, a->rn, addr);
165     } else {
166         tcg_temp_free_i32(addr);
167     }
168     mve_update_eci(s);
169     return true;
170 }
171 
172 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
173 {
174     static MVEGenLdStFn * const ldstfns[4][2] = {
175         { gen_helper_mve_vstrb, gen_helper_mve_vldrb },
176         { gen_helper_mve_vstrh, gen_helper_mve_vldrh },
177         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
178         { NULL, NULL }
179     };
180     return do_ldst(s, a, ldstfns[a->size][a->l]);
181 }
182 
183 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
184     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
185     {                                                           \
186         static MVEGenLdStFn * const ldstfns[2][2] = {           \
187             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
188             { NULL, gen_helper_mve_##ULD },                     \
189         };                                                      \
190         return do_ldst(s, a, ldstfns[a->u][a->l]);              \
191     }
192 
193 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
194 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
195 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
196 
197 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
198 {
199     TCGv_ptr qd;
200     TCGv_i32 rt;
201 
202     if (!dc_isar_feature(aa32_mve, s) ||
203         !mve_check_qreg_bank(s, a->qd)) {
204         return false;
205     }
206     if (a->rt == 13 || a->rt == 15) {
207         /* UNPREDICTABLE; we choose to UNDEF */
208         return false;
209     }
210     if (!mve_eci_check(s) || !vfp_access_check(s)) {
211         return true;
212     }
213 
214     qd = mve_qreg_ptr(a->qd);
215     rt = load_reg(s, a->rt);
216     tcg_gen_dup_i32(a->size, rt, rt);
217     gen_helper_mve_vdup(cpu_env, qd, rt);
218     tcg_temp_free_ptr(qd);
219     tcg_temp_free_i32(rt);
220     mve_update_eci(s);
221     return true;
222 }
223 
224 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
225 {
226     TCGv_ptr qd, qm;
227 
228     if (!dc_isar_feature(aa32_mve, s) ||
229         !mve_check_qreg_bank(s, a->qd | a->qm) ||
230         !fn) {
231         return false;
232     }
233 
234     if (!mve_eci_check(s) || !vfp_access_check(s)) {
235         return true;
236     }
237 
238     qd = mve_qreg_ptr(a->qd);
239     qm = mve_qreg_ptr(a->qm);
240     fn(cpu_env, qd, qm);
241     tcg_temp_free_ptr(qd);
242     tcg_temp_free_ptr(qm);
243     mve_update_eci(s);
244     return true;
245 }
246 
247 #define DO_1OP(INSN, FN)                                        \
248     static bool trans_##INSN(DisasContext *s, arg_1op *a)       \
249     {                                                           \
250         static MVEGenOneOpFn * const fns[] = {                  \
251             gen_helper_mve_##FN##b,                             \
252             gen_helper_mve_##FN##h,                             \
253             gen_helper_mve_##FN##w,                             \
254             NULL,                                               \
255         };                                                      \
256         return do_1op(s, a, fns[a->size]);                      \
257     }
258 
259 DO_1OP(VCLZ, vclz)
260 DO_1OP(VCLS, vcls)
261 DO_1OP(VABS, vabs)
262 DO_1OP(VNEG, vneg)
263 
264 static bool trans_VREV16(DisasContext *s, arg_1op *a)
265 {
266     static MVEGenOneOpFn * const fns[] = {
267         gen_helper_mve_vrev16b,
268         NULL,
269         NULL,
270         NULL,
271     };
272     return do_1op(s, a, fns[a->size]);
273 }
274 
275 static bool trans_VREV32(DisasContext *s, arg_1op *a)
276 {
277     static MVEGenOneOpFn * const fns[] = {
278         gen_helper_mve_vrev32b,
279         gen_helper_mve_vrev32h,
280         NULL,
281         NULL,
282     };
283     return do_1op(s, a, fns[a->size]);
284 }
285 
286 static bool trans_VREV64(DisasContext *s, arg_1op *a)
287 {
288     static MVEGenOneOpFn * const fns[] = {
289         gen_helper_mve_vrev64b,
290         gen_helper_mve_vrev64h,
291         gen_helper_mve_vrev64w,
292         NULL,
293     };
294     return do_1op(s, a, fns[a->size]);
295 }
296 
297 static bool trans_VMVN(DisasContext *s, arg_1op *a)
298 {
299     return do_1op(s, a, gen_helper_mve_vmvn);
300 }
301 
302 static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
303 {
304     static MVEGenOneOpFn * const fns[] = {
305         NULL,
306         gen_helper_mve_vfabsh,
307         gen_helper_mve_vfabss,
308         NULL,
309     };
310     if (!dc_isar_feature(aa32_mve_fp, s)) {
311         return false;
312     }
313     return do_1op(s, a, fns[a->size]);
314 }
315 
316 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
317 {
318     static MVEGenOneOpFn * const fns[] = {
319         NULL,
320         gen_helper_mve_vfnegh,
321         gen_helper_mve_vfnegs,
322         NULL,
323     };
324     if (!dc_isar_feature(aa32_mve_fp, s)) {
325         return false;
326     }
327     return do_1op(s, a, fns[a->size]);
328 }
329 
330 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
331 {
332     TCGv_ptr qd, qn, qm;
333 
334     if (!dc_isar_feature(aa32_mve, s) ||
335         !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) ||
336         !fn) {
337         return false;
338     }
339     if (!mve_eci_check(s) || !vfp_access_check(s)) {
340         return true;
341     }
342 
343     qd = mve_qreg_ptr(a->qd);
344     qn = mve_qreg_ptr(a->qn);
345     qm = mve_qreg_ptr(a->qm);
346     fn(cpu_env, qd, qn, qm);
347     tcg_temp_free_ptr(qd);
348     tcg_temp_free_ptr(qn);
349     tcg_temp_free_ptr(qm);
350     mve_update_eci(s);
351     return true;
352 }
353 
354 #define DO_LOGIC(INSN, HELPER)                                  \
355     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
356     {                                                           \
357         return do_2op(s, a, HELPER);                            \
358     }
359 
360 DO_LOGIC(VAND, gen_helper_mve_vand)
361 DO_LOGIC(VBIC, gen_helper_mve_vbic)
362 DO_LOGIC(VORR, gen_helper_mve_vorr)
363 DO_LOGIC(VORN, gen_helper_mve_vorn)
364 DO_LOGIC(VEOR, gen_helper_mve_veor)
365 
366 #define DO_2OP(INSN, FN) \
367     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
368     {                                                           \
369         static MVEGenTwoOpFn * const fns[] = {                  \
370             gen_helper_mve_##FN##b,                             \
371             gen_helper_mve_##FN##h,                             \
372             gen_helper_mve_##FN##w,                             \
373             NULL,                                               \
374         };                                                      \
375         return do_2op(s, a, fns[a->size]);                      \
376     }
377 
378 DO_2OP(VADD, vadd)
379 DO_2OP(VSUB, vsub)
380 DO_2OP(VMUL, vmul)
381 DO_2OP(VMULH_S, vmulhs)
382 DO_2OP(VMULH_U, vmulhu)
383 DO_2OP(VRMULH_S, vrmulhs)
384 DO_2OP(VRMULH_U, vrmulhu)
385 DO_2OP(VMAX_S, vmaxs)
386 DO_2OP(VMAX_U, vmaxu)
387 DO_2OP(VMIN_S, vmins)
388 DO_2OP(VMIN_U, vminu)
389 DO_2OP(VABD_S, vabds)
390 DO_2OP(VABD_U, vabdu)
391 DO_2OP(VHADD_S, vhadds)
392 DO_2OP(VHADD_U, vhaddu)
393 DO_2OP(VHSUB_S, vhsubs)
394 DO_2OP(VHSUB_U, vhsubu)
395 DO_2OP(VMULL_BS, vmullbs)
396 DO_2OP(VMULL_BU, vmullbu)
397 DO_2OP(VMULL_TS, vmullts)
398 DO_2OP(VMULL_TU, vmulltu)
399 DO_2OP(VQDMULH, vqdmulh)
400 DO_2OP(VQRDMULH, vqrdmulh)
401 DO_2OP(VQADD_S, vqadds)
402 DO_2OP(VQADD_U, vqaddu)
403 DO_2OP(VQSUB_S, vqsubs)
404 DO_2OP(VQSUB_U, vqsubu)
405 DO_2OP(VSHL_S, vshls)
406 DO_2OP(VSHL_U, vshlu)
407 DO_2OP(VRSHL_S, vrshls)
408 DO_2OP(VRSHL_U, vrshlu)
409 DO_2OP(VQSHL_S, vqshls)
410 DO_2OP(VQSHL_U, vqshlu)
411 DO_2OP(VQRSHL_S, vqrshls)
412 DO_2OP(VQRSHL_U, vqrshlu)
413 DO_2OP(VQDMLADH, vqdmladh)
414 DO_2OP(VQDMLADHX, vqdmladhx)
415 DO_2OP(VQRDMLADH, vqrdmladh)
416 DO_2OP(VQRDMLADHX, vqrdmladhx)
417 DO_2OP(VQDMLSDH, vqdmlsdh)
418 DO_2OP(VQDMLSDHX, vqdmlsdhx)
419 DO_2OP(VQRDMLSDH, vqrdmlsdh)
420 DO_2OP(VQRDMLSDHX, vqrdmlsdhx)
421 DO_2OP(VRHADD_S, vrhadds)
422 DO_2OP(VRHADD_U, vrhaddu)
423 
424 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a)
425 {
426     static MVEGenTwoOpFn * const fns[] = {
427         NULL,
428         gen_helper_mve_vqdmullbh,
429         gen_helper_mve_vqdmullbw,
430         NULL,
431     };
432     if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
433         /* UNPREDICTABLE; we choose to undef */
434         return false;
435     }
436     return do_2op(s, a, fns[a->size]);
437 }
438 
439 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a)
440 {
441     static MVEGenTwoOpFn * const fns[] = {
442         NULL,
443         gen_helper_mve_vqdmullth,
444         gen_helper_mve_vqdmulltw,
445         NULL,
446     };
447     if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
448         /* UNPREDICTABLE; we choose to undef */
449         return false;
450     }
451     return do_2op(s, a, fns[a->size]);
452 }
453 
454 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
455                           MVEGenTwoOpScalarFn fn)
456 {
457     TCGv_ptr qd, qn;
458     TCGv_i32 rm;
459 
460     if (!dc_isar_feature(aa32_mve, s) ||
461         !mve_check_qreg_bank(s, a->qd | a->qn) ||
462         !fn) {
463         return false;
464     }
465     if (a->rm == 13 || a->rm == 15) {
466         /* UNPREDICTABLE */
467         return false;
468     }
469     if (!mve_eci_check(s) || !vfp_access_check(s)) {
470         return true;
471     }
472 
473     qd = mve_qreg_ptr(a->qd);
474     qn = mve_qreg_ptr(a->qn);
475     rm = load_reg(s, a->rm);
476     fn(cpu_env, qd, qn, rm);
477     tcg_temp_free_i32(rm);
478     tcg_temp_free_ptr(qd);
479     tcg_temp_free_ptr(qn);
480     mve_update_eci(s);
481     return true;
482 }
483 
484 #define DO_2OP_SCALAR(INSN, FN) \
485     static bool trans_##INSN(DisasContext *s, arg_2scalar *a)   \
486     {                                                           \
487         static MVEGenTwoOpScalarFn * const fns[] = {            \
488             gen_helper_mve_##FN##b,                             \
489             gen_helper_mve_##FN##h,                             \
490             gen_helper_mve_##FN##w,                             \
491             NULL,                                               \
492         };                                                      \
493         return do_2op_scalar(s, a, fns[a->size]);               \
494     }
495 
496 DO_2OP_SCALAR(VADD_scalar, vadd_scalar)
497 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar)
498 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar)
499 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar)
500 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar)
501 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar)
502 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar)
503 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar)
504 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar)
505 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar)
506 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar)
507 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar)
508 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar)
509 DO_2OP_SCALAR(VBRSR, vbrsr)
510 
511 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a)
512 {
513     static MVEGenTwoOpScalarFn * const fns[] = {
514         NULL,
515         gen_helper_mve_vqdmullb_scalarh,
516         gen_helper_mve_vqdmullb_scalarw,
517         NULL,
518     };
519     if (a->qd == a->qn && a->size == MO_32) {
520         /* UNPREDICTABLE; we choose to undef */
521         return false;
522     }
523     return do_2op_scalar(s, a, fns[a->size]);
524 }
525 
526 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a)
527 {
528     static MVEGenTwoOpScalarFn * const fns[] = {
529         NULL,
530         gen_helper_mve_vqdmullt_scalarh,
531         gen_helper_mve_vqdmullt_scalarw,
532         NULL,
533     };
534     if (a->qd == a->qn && a->size == MO_32) {
535         /* UNPREDICTABLE; we choose to undef */
536         return false;
537     }
538     return do_2op_scalar(s, a, fns[a->size]);
539 }
540 
541 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
542                              MVEGenDualAccOpFn *fn)
543 {
544     TCGv_ptr qn, qm;
545     TCGv_i64 rda;
546     TCGv_i32 rdalo, rdahi;
547 
548     if (!dc_isar_feature(aa32_mve, s) ||
549         !mve_check_qreg_bank(s, a->qn | a->qm) ||
550         !fn) {
551         return false;
552     }
553     /*
554      * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
555      * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
556      */
557     if (a->rdahi == 13 || a->rdahi == 15) {
558         return false;
559     }
560     if (!mve_eci_check(s) || !vfp_access_check(s)) {
561         return true;
562     }
563 
564     qn = mve_qreg_ptr(a->qn);
565     qm = mve_qreg_ptr(a->qm);
566 
567     /*
568      * This insn is subject to beat-wise execution. Partial execution
569      * of an A=0 (no-accumulate) insn which does not execute the first
570      * beat must start with the current rda value, not 0.
571      */
572     if (a->a || mve_skip_first_beat(s)) {
573         rda = tcg_temp_new_i64();
574         rdalo = load_reg(s, a->rdalo);
575         rdahi = load_reg(s, a->rdahi);
576         tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
577         tcg_temp_free_i32(rdalo);
578         tcg_temp_free_i32(rdahi);
579     } else {
580         rda = tcg_const_i64(0);
581     }
582 
583     fn(rda, cpu_env, qn, qm, rda);
584     tcg_temp_free_ptr(qn);
585     tcg_temp_free_ptr(qm);
586 
587     rdalo = tcg_temp_new_i32();
588     rdahi = tcg_temp_new_i32();
589     tcg_gen_extrl_i64_i32(rdalo, rda);
590     tcg_gen_extrh_i64_i32(rdahi, rda);
591     store_reg(s, a->rdalo, rdalo);
592     store_reg(s, a->rdahi, rdahi);
593     tcg_temp_free_i64(rda);
594     mve_update_eci(s);
595     return true;
596 }
597 
598 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a)
599 {
600     static MVEGenDualAccOpFn * const fns[4][2] = {
601         { NULL, NULL },
602         { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh },
603         { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw },
604         { NULL, NULL },
605     };
606     return do_long_dual_acc(s, a, fns[a->size][a->x]);
607 }
608 
609 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a)
610 {
611     static MVEGenDualAccOpFn * const fns[4][2] = {
612         { NULL, NULL },
613         { gen_helper_mve_vmlaldavuh, NULL },
614         { gen_helper_mve_vmlaldavuw, NULL },
615         { NULL, NULL },
616     };
617     return do_long_dual_acc(s, a, fns[a->size][a->x]);
618 }
619 
620 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
621 {
622     static MVEGenDualAccOpFn * const fns[4][2] = {
623         { NULL, NULL },
624         { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh },
625         { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw },
626         { NULL, NULL },
627     };
628     return do_long_dual_acc(s, a, fns[a->size][a->x]);
629 }
630 
631 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a)
632 {
633     static MVEGenDualAccOpFn * const fns[] = {
634         gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw,
635     };
636     return do_long_dual_acc(s, a, fns[a->x]);
637 }
638 
639 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a)
640 {
641     static MVEGenDualAccOpFn * const fns[] = {
642         gen_helper_mve_vrmlaldavhuw, NULL,
643     };
644     return do_long_dual_acc(s, a, fns[a->x]);
645 }
646 
647 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
648 {
649     static MVEGenDualAccOpFn * const fns[] = {
650         gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw,
651     };
652     return do_long_dual_acc(s, a, fns[a->x]);
653 }
654 
655 static bool trans_VPST(DisasContext *s, arg_VPST *a)
656 {
657     TCGv_i32 vpr;
658 
659     /* mask == 0 is a "related encoding" */
660     if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
661         return false;
662     }
663     if (!mve_eci_check(s) || !vfp_access_check(s)) {
664         return true;
665     }
666     /*
667      * Set the VPR mask fields. We take advantage of MASK01 and MASK23
668      * being adjacent fields in the register.
669      *
670      * This insn is not predicated, but it is subject to beat-wise
671      * execution, and the mask is updated on the odd-numbered beats.
672      * So if PSR.ECI says we should skip beat 1, we mustn't update the
673      * 01 mask field.
674      */
675     vpr = load_cpu_field(v7m.vpr);
676     switch (s->eci) {
677     case ECI_NONE:
678     case ECI_A0:
679         /* Update both 01 and 23 fields */
680         tcg_gen_deposit_i32(vpr, vpr,
681                             tcg_constant_i32(a->mask | (a->mask << 4)),
682                             R_V7M_VPR_MASK01_SHIFT,
683                             R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH);
684         break;
685     case ECI_A0A1:
686     case ECI_A0A1A2:
687     case ECI_A0A1A2B0:
688         /* Update only the 23 mask field */
689         tcg_gen_deposit_i32(vpr, vpr,
690                             tcg_constant_i32(a->mask),
691                             R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH);
692         break;
693     default:
694         g_assert_not_reached();
695     }
696     store_cpu_field(vpr, v7m.vpr);
697     mve_update_and_store_eci(s);
698     return true;
699 }
700