1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 /* Include the generated decoder */ 29 #include "decode-mve.c.inc" 30 31 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 32 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 33 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 34 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 35 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 36 37 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 38 static inline long mve_qreg_offset(unsigned reg) 39 { 40 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 41 } 42 43 static TCGv_ptr mve_qreg_ptr(unsigned reg) 44 { 45 TCGv_ptr ret = tcg_temp_new_ptr(); 46 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 47 return ret; 48 } 49 50 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 51 { 52 /* 53 * Check whether Qregs are in range. For v8.1M only Q0..Q7 54 * are supported, see VFPSmallRegisterBank(). 55 */ 56 return qmask < 8; 57 } 58 59 static bool mve_eci_check(DisasContext *s) 60 { 61 /* 62 * This is a beatwise insn: check that ECI is valid (not a 63 * reserved value) and note that we are handling it. 64 * Return true if OK, false if we generated an exception. 65 */ 66 s->eci_handled = true; 67 switch (s->eci) { 68 case ECI_NONE: 69 case ECI_A0: 70 case ECI_A0A1: 71 case ECI_A0A1A2: 72 case ECI_A0A1A2B0: 73 return true; 74 default: 75 /* Reserved value: INVSTATE UsageFault */ 76 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 77 default_exception_el(s)); 78 return false; 79 } 80 } 81 82 static void mve_update_eci(DisasContext *s) 83 { 84 /* 85 * The helper function will always update the CPUState field, 86 * so we only need to update the DisasContext field. 87 */ 88 if (s->eci) { 89 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 90 } 91 } 92 93 static void mve_update_and_store_eci(DisasContext *s) 94 { 95 /* 96 * For insns which don't call a helper function that will call 97 * mve_advance_vpt(), this version updates s->eci and also stores 98 * it out to the CPUState field. 99 */ 100 if (s->eci) { 101 mve_update_eci(s); 102 store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); 103 } 104 } 105 106 static bool mve_skip_first_beat(DisasContext *s) 107 { 108 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 109 switch (s->eci) { 110 case ECI_NONE: 111 return false; 112 case ECI_A0: 113 case ECI_A0A1: 114 case ECI_A0A1A2: 115 case ECI_A0A1A2B0: 116 return true; 117 default: 118 g_assert_not_reached(); 119 } 120 } 121 122 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) 123 { 124 TCGv_i32 addr; 125 uint32_t offset; 126 TCGv_ptr qreg; 127 128 if (!dc_isar_feature(aa32_mve, s) || 129 !mve_check_qreg_bank(s, a->qd) || 130 !fn) { 131 return false; 132 } 133 134 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 135 if (a->rn == 15 || (a->rn == 13 && a->w)) { 136 return false; 137 } 138 139 if (!mve_eci_check(s) || !vfp_access_check(s)) { 140 return true; 141 } 142 143 offset = a->imm << a->size; 144 if (!a->a) { 145 offset = -offset; 146 } 147 addr = load_reg(s, a->rn); 148 if (a->p) { 149 tcg_gen_addi_i32(addr, addr, offset); 150 } 151 152 qreg = mve_qreg_ptr(a->qd); 153 fn(cpu_env, qreg, addr); 154 tcg_temp_free_ptr(qreg); 155 156 /* 157 * Writeback always happens after the last beat of the insn, 158 * regardless of predication 159 */ 160 if (a->w) { 161 if (!a->p) { 162 tcg_gen_addi_i32(addr, addr, offset); 163 } 164 store_reg(s, a->rn, addr); 165 } else { 166 tcg_temp_free_i32(addr); 167 } 168 mve_update_eci(s); 169 return true; 170 } 171 172 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 173 { 174 static MVEGenLdStFn * const ldstfns[4][2] = { 175 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 176 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 177 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 178 { NULL, NULL } 179 }; 180 return do_ldst(s, a, ldstfns[a->size][a->l]); 181 } 182 183 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ 184 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 185 { \ 186 static MVEGenLdStFn * const ldstfns[2][2] = { \ 187 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 188 { NULL, gen_helper_mve_##ULD }, \ 189 }; \ 190 return do_ldst(s, a, ldstfns[a->u][a->l]); \ 191 } 192 193 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) 194 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) 195 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) 196 197 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 198 { 199 TCGv_ptr qd; 200 TCGv_i32 rt; 201 202 if (!dc_isar_feature(aa32_mve, s) || 203 !mve_check_qreg_bank(s, a->qd)) { 204 return false; 205 } 206 if (a->rt == 13 || a->rt == 15) { 207 /* UNPREDICTABLE; we choose to UNDEF */ 208 return false; 209 } 210 if (!mve_eci_check(s) || !vfp_access_check(s)) { 211 return true; 212 } 213 214 qd = mve_qreg_ptr(a->qd); 215 rt = load_reg(s, a->rt); 216 tcg_gen_dup_i32(a->size, rt, rt); 217 gen_helper_mve_vdup(cpu_env, qd, rt); 218 tcg_temp_free_ptr(qd); 219 tcg_temp_free_i32(rt); 220 mve_update_eci(s); 221 return true; 222 } 223 224 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 225 { 226 TCGv_ptr qd, qm; 227 228 if (!dc_isar_feature(aa32_mve, s) || 229 !mve_check_qreg_bank(s, a->qd | a->qm) || 230 !fn) { 231 return false; 232 } 233 234 if (!mve_eci_check(s) || !vfp_access_check(s)) { 235 return true; 236 } 237 238 qd = mve_qreg_ptr(a->qd); 239 qm = mve_qreg_ptr(a->qm); 240 fn(cpu_env, qd, qm); 241 tcg_temp_free_ptr(qd); 242 tcg_temp_free_ptr(qm); 243 mve_update_eci(s); 244 return true; 245 } 246 247 #define DO_1OP(INSN, FN) \ 248 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 249 { \ 250 static MVEGenOneOpFn * const fns[] = { \ 251 gen_helper_mve_##FN##b, \ 252 gen_helper_mve_##FN##h, \ 253 gen_helper_mve_##FN##w, \ 254 NULL, \ 255 }; \ 256 return do_1op(s, a, fns[a->size]); \ 257 } 258 259 DO_1OP(VCLZ, vclz) 260 DO_1OP(VCLS, vcls) 261 DO_1OP(VABS, vabs) 262 DO_1OP(VNEG, vneg) 263 264 static bool trans_VREV16(DisasContext *s, arg_1op *a) 265 { 266 static MVEGenOneOpFn * const fns[] = { 267 gen_helper_mve_vrev16b, 268 NULL, 269 NULL, 270 NULL, 271 }; 272 return do_1op(s, a, fns[a->size]); 273 } 274 275 static bool trans_VREV32(DisasContext *s, arg_1op *a) 276 { 277 static MVEGenOneOpFn * const fns[] = { 278 gen_helper_mve_vrev32b, 279 gen_helper_mve_vrev32h, 280 NULL, 281 NULL, 282 }; 283 return do_1op(s, a, fns[a->size]); 284 } 285 286 static bool trans_VREV64(DisasContext *s, arg_1op *a) 287 { 288 static MVEGenOneOpFn * const fns[] = { 289 gen_helper_mve_vrev64b, 290 gen_helper_mve_vrev64h, 291 gen_helper_mve_vrev64w, 292 NULL, 293 }; 294 return do_1op(s, a, fns[a->size]); 295 } 296 297 static bool trans_VMVN(DisasContext *s, arg_1op *a) 298 { 299 return do_1op(s, a, gen_helper_mve_vmvn); 300 } 301 302 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 303 { 304 static MVEGenOneOpFn * const fns[] = { 305 NULL, 306 gen_helper_mve_vfabsh, 307 gen_helper_mve_vfabss, 308 NULL, 309 }; 310 if (!dc_isar_feature(aa32_mve_fp, s)) { 311 return false; 312 } 313 return do_1op(s, a, fns[a->size]); 314 } 315 316 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 317 { 318 static MVEGenOneOpFn * const fns[] = { 319 NULL, 320 gen_helper_mve_vfnegh, 321 gen_helper_mve_vfnegs, 322 NULL, 323 }; 324 if (!dc_isar_feature(aa32_mve_fp, s)) { 325 return false; 326 } 327 return do_1op(s, a, fns[a->size]); 328 } 329 330 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 331 { 332 TCGv_ptr qd, qn, qm; 333 334 if (!dc_isar_feature(aa32_mve, s) || 335 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 336 !fn) { 337 return false; 338 } 339 if (!mve_eci_check(s) || !vfp_access_check(s)) { 340 return true; 341 } 342 343 qd = mve_qreg_ptr(a->qd); 344 qn = mve_qreg_ptr(a->qn); 345 qm = mve_qreg_ptr(a->qm); 346 fn(cpu_env, qd, qn, qm); 347 tcg_temp_free_ptr(qd); 348 tcg_temp_free_ptr(qn); 349 tcg_temp_free_ptr(qm); 350 mve_update_eci(s); 351 return true; 352 } 353 354 #define DO_LOGIC(INSN, HELPER) \ 355 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 356 { \ 357 return do_2op(s, a, HELPER); \ 358 } 359 360 DO_LOGIC(VAND, gen_helper_mve_vand) 361 DO_LOGIC(VBIC, gen_helper_mve_vbic) 362 DO_LOGIC(VORR, gen_helper_mve_vorr) 363 DO_LOGIC(VORN, gen_helper_mve_vorn) 364 DO_LOGIC(VEOR, gen_helper_mve_veor) 365 366 #define DO_2OP(INSN, FN) \ 367 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 368 { \ 369 static MVEGenTwoOpFn * const fns[] = { \ 370 gen_helper_mve_##FN##b, \ 371 gen_helper_mve_##FN##h, \ 372 gen_helper_mve_##FN##w, \ 373 NULL, \ 374 }; \ 375 return do_2op(s, a, fns[a->size]); \ 376 } 377 378 DO_2OP(VADD, vadd) 379 DO_2OP(VSUB, vsub) 380 DO_2OP(VMUL, vmul) 381 DO_2OP(VMULH_S, vmulhs) 382 DO_2OP(VMULH_U, vmulhu) 383 DO_2OP(VRMULH_S, vrmulhs) 384 DO_2OP(VRMULH_U, vrmulhu) 385 DO_2OP(VMAX_S, vmaxs) 386 DO_2OP(VMAX_U, vmaxu) 387 DO_2OP(VMIN_S, vmins) 388 DO_2OP(VMIN_U, vminu) 389 DO_2OP(VABD_S, vabds) 390 DO_2OP(VABD_U, vabdu) 391 DO_2OP(VHADD_S, vhadds) 392 DO_2OP(VHADD_U, vhaddu) 393 DO_2OP(VHSUB_S, vhsubs) 394 DO_2OP(VHSUB_U, vhsubu) 395 DO_2OP(VMULL_BS, vmullbs) 396 DO_2OP(VMULL_BU, vmullbu) 397 DO_2OP(VMULL_TS, vmullts) 398 DO_2OP(VMULL_TU, vmulltu) 399 DO_2OP(VQDMULH, vqdmulh) 400 DO_2OP(VQRDMULH, vqrdmulh) 401 DO_2OP(VQADD_S, vqadds) 402 DO_2OP(VQADD_U, vqaddu) 403 DO_2OP(VQSUB_S, vqsubs) 404 DO_2OP(VQSUB_U, vqsubu) 405 DO_2OP(VSHL_S, vshls) 406 DO_2OP(VSHL_U, vshlu) 407 DO_2OP(VRSHL_S, vrshls) 408 DO_2OP(VRSHL_U, vrshlu) 409 DO_2OP(VQSHL_S, vqshls) 410 DO_2OP(VQSHL_U, vqshlu) 411 DO_2OP(VQRSHL_S, vqrshls) 412 DO_2OP(VQRSHL_U, vqrshlu) 413 DO_2OP(VQDMLADH, vqdmladh) 414 DO_2OP(VQDMLADHX, vqdmladhx) 415 DO_2OP(VQRDMLADH, vqrdmladh) 416 DO_2OP(VQRDMLADHX, vqrdmladhx) 417 DO_2OP(VQDMLSDH, vqdmlsdh) 418 DO_2OP(VQDMLSDHX, vqdmlsdhx) 419 DO_2OP(VQRDMLSDH, vqrdmlsdh) 420 DO_2OP(VQRDMLSDHX, vqrdmlsdhx) 421 422 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 423 MVEGenTwoOpScalarFn fn) 424 { 425 TCGv_ptr qd, qn; 426 TCGv_i32 rm; 427 428 if (!dc_isar_feature(aa32_mve, s) || 429 !mve_check_qreg_bank(s, a->qd | a->qn) || 430 !fn) { 431 return false; 432 } 433 if (a->rm == 13 || a->rm == 15) { 434 /* UNPREDICTABLE */ 435 return false; 436 } 437 if (!mve_eci_check(s) || !vfp_access_check(s)) { 438 return true; 439 } 440 441 qd = mve_qreg_ptr(a->qd); 442 qn = mve_qreg_ptr(a->qn); 443 rm = load_reg(s, a->rm); 444 fn(cpu_env, qd, qn, rm); 445 tcg_temp_free_i32(rm); 446 tcg_temp_free_ptr(qd); 447 tcg_temp_free_ptr(qn); 448 mve_update_eci(s); 449 return true; 450 } 451 452 #define DO_2OP_SCALAR(INSN, FN) \ 453 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 454 { \ 455 static MVEGenTwoOpScalarFn * const fns[] = { \ 456 gen_helper_mve_##FN##b, \ 457 gen_helper_mve_##FN##h, \ 458 gen_helper_mve_##FN##w, \ 459 NULL, \ 460 }; \ 461 return do_2op_scalar(s, a, fns[a->size]); \ 462 } 463 464 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 465 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) 466 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) 467 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) 468 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) 469 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) 470 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) 471 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) 472 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) 473 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) 474 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) 475 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) 476 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) 477 DO_2OP_SCALAR(VBRSR, vbrsr) 478 479 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) 480 { 481 static MVEGenTwoOpScalarFn * const fns[] = { 482 NULL, 483 gen_helper_mve_vqdmullb_scalarh, 484 gen_helper_mve_vqdmullb_scalarw, 485 NULL, 486 }; 487 if (a->qd == a->qn && a->size == MO_32) { 488 /* UNPREDICTABLE; we choose to undef */ 489 return false; 490 } 491 return do_2op_scalar(s, a, fns[a->size]); 492 } 493 494 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) 495 { 496 static MVEGenTwoOpScalarFn * const fns[] = { 497 NULL, 498 gen_helper_mve_vqdmullt_scalarh, 499 gen_helper_mve_vqdmullt_scalarw, 500 NULL, 501 }; 502 if (a->qd == a->qn && a->size == MO_32) { 503 /* UNPREDICTABLE; we choose to undef */ 504 return false; 505 } 506 return do_2op_scalar(s, a, fns[a->size]); 507 } 508 509 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 510 MVEGenDualAccOpFn *fn) 511 { 512 TCGv_ptr qn, qm; 513 TCGv_i64 rda; 514 TCGv_i32 rdalo, rdahi; 515 516 if (!dc_isar_feature(aa32_mve, s) || 517 !mve_check_qreg_bank(s, a->qn | a->qm) || 518 !fn) { 519 return false; 520 } 521 /* 522 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 523 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 524 */ 525 if (a->rdahi == 13 || a->rdahi == 15) { 526 return false; 527 } 528 if (!mve_eci_check(s) || !vfp_access_check(s)) { 529 return true; 530 } 531 532 qn = mve_qreg_ptr(a->qn); 533 qm = mve_qreg_ptr(a->qm); 534 535 /* 536 * This insn is subject to beat-wise execution. Partial execution 537 * of an A=0 (no-accumulate) insn which does not execute the first 538 * beat must start with the current rda value, not 0. 539 */ 540 if (a->a || mve_skip_first_beat(s)) { 541 rda = tcg_temp_new_i64(); 542 rdalo = load_reg(s, a->rdalo); 543 rdahi = load_reg(s, a->rdahi); 544 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 545 tcg_temp_free_i32(rdalo); 546 tcg_temp_free_i32(rdahi); 547 } else { 548 rda = tcg_const_i64(0); 549 } 550 551 fn(rda, cpu_env, qn, qm, rda); 552 tcg_temp_free_ptr(qn); 553 tcg_temp_free_ptr(qm); 554 555 rdalo = tcg_temp_new_i32(); 556 rdahi = tcg_temp_new_i32(); 557 tcg_gen_extrl_i64_i32(rdalo, rda); 558 tcg_gen_extrh_i64_i32(rdahi, rda); 559 store_reg(s, a->rdalo, rdalo); 560 store_reg(s, a->rdahi, rdahi); 561 tcg_temp_free_i64(rda); 562 mve_update_eci(s); 563 return true; 564 } 565 566 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 567 { 568 static MVEGenDualAccOpFn * const fns[4][2] = { 569 { NULL, NULL }, 570 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 571 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 572 { NULL, NULL }, 573 }; 574 return do_long_dual_acc(s, a, fns[a->size][a->x]); 575 } 576 577 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 578 { 579 static MVEGenDualAccOpFn * const fns[4][2] = { 580 { NULL, NULL }, 581 { gen_helper_mve_vmlaldavuh, NULL }, 582 { gen_helper_mve_vmlaldavuw, NULL }, 583 { NULL, NULL }, 584 }; 585 return do_long_dual_acc(s, a, fns[a->size][a->x]); 586 } 587 588 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 589 { 590 static MVEGenDualAccOpFn * const fns[4][2] = { 591 { NULL, NULL }, 592 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 593 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 594 { NULL, NULL }, 595 }; 596 return do_long_dual_acc(s, a, fns[a->size][a->x]); 597 } 598 599 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 600 { 601 static MVEGenDualAccOpFn * const fns[] = { 602 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 603 }; 604 return do_long_dual_acc(s, a, fns[a->x]); 605 } 606 607 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 608 { 609 static MVEGenDualAccOpFn * const fns[] = { 610 gen_helper_mve_vrmlaldavhuw, NULL, 611 }; 612 return do_long_dual_acc(s, a, fns[a->x]); 613 } 614 615 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 616 { 617 static MVEGenDualAccOpFn * const fns[] = { 618 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 619 }; 620 return do_long_dual_acc(s, a, fns[a->x]); 621 } 622 623 static bool trans_VPST(DisasContext *s, arg_VPST *a) 624 { 625 TCGv_i32 vpr; 626 627 /* mask == 0 is a "related encoding" */ 628 if (!dc_isar_feature(aa32_mve, s) || !a->mask) { 629 return false; 630 } 631 if (!mve_eci_check(s) || !vfp_access_check(s)) { 632 return true; 633 } 634 /* 635 * Set the VPR mask fields. We take advantage of MASK01 and MASK23 636 * being adjacent fields in the register. 637 * 638 * This insn is not predicated, but it is subject to beat-wise 639 * execution, and the mask is updated on the odd-numbered beats. 640 * So if PSR.ECI says we should skip beat 1, we mustn't update the 641 * 01 mask field. 642 */ 643 vpr = load_cpu_field(v7m.vpr); 644 switch (s->eci) { 645 case ECI_NONE: 646 case ECI_A0: 647 /* Update both 01 and 23 fields */ 648 tcg_gen_deposit_i32(vpr, vpr, 649 tcg_constant_i32(a->mask | (a->mask << 4)), 650 R_V7M_VPR_MASK01_SHIFT, 651 R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); 652 break; 653 case ECI_A0A1: 654 case ECI_A0A1A2: 655 case ECI_A0A1A2B0: 656 /* Update only the 23 mask field */ 657 tcg_gen_deposit_i32(vpr, vpr, 658 tcg_constant_i32(a->mask), 659 R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); 660 break; 661 default: 662 g_assert_not_reached(); 663 } 664 store_cpu_field(vpr, v7m.vpr); 665 mve_update_and_store_eci(s); 666 return true; 667 } 668