fix printf warning on 32-bit macOS

uint32_t is "unsigned long" on 32-bit macOS, which causes a warning
if it is passed to printf as %d:

/private/var/folders/tn/f_9sf1xx5t14qm_6f83q3b840000gn/T/cirr

fix printf warning on 32-bit macOS

uint32_t is "unsigned long" on 32-bit macOS, which causes a warning
if it is passed to printf as %d:

/private/var/folders/tn/f_9sf1xx5t14qm_6f83q3b840000gn/T/cirrus-ci-build/lib/libcflat.h:141:24: error: format '%d' expects argument of type int, but argument 6 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=]
141 | printf("%s:%d: assert failed: %s: " fmt "\n", \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
/private/var/folders/tn/f_9sf1xx5t14qm_6f83q3b840000gn/T/cirrus-ci-build/lib/x86/processor.h:460:9: note: in expansion of macro 'assert_msg'
460 | assert_msg(!vector, "Unexpected %s on RDPMC(%d)",
| ^~~~~~~~~~

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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lib: x86: Use portable format macros for uint32_t

Compilation of the files fails on ARCH=i386 with i686-elf gcc on macos_i386
because they use "%d" format specifier that does not match the actual si

lib: x86: Use portable format macros for uint32_t

Compilation of the files fails on ARCH=i386 with i686-elf gcc on macos_i386
because they use "%d" format specifier that does not match the actual size of
uint32_t:

In function 'rdpmc':
lib/libcflat.h:141:24: error: format '%d' expects argument of type 'int',
but argument 6 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=]
141 | printf("%s:%d: assert failed: %s: " fmt "\n", \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~

Use PRId32 instead of "d" to take into account macos_i386 case.

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Message-Id: <20221124123149.91339-1-likexu@tencent.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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x86/pmu: Add AMD Guest PerfMonV2 testcases

Updated test cases to cover KVM enabling code for AMD Guest PerfMonV2.

The Intel-specific PMU helpers were added to check for AMD cpuid, and
some of the s

x86/pmu: Add AMD Guest PerfMonV2 testcases

Updated test cases to cover KVM enabling code for AMD Guest PerfMonV2.

The Intel-specific PMU helpers were added to check for AMD cpuid, and
some of the same semantics of MSRs were assigned during the initialization
phase. The vast majority of pmu test cases are reused seamlessly.

On some x86 machines (AMD only), even with retired events, the same
workload is measured repeatedly and the number of events collected is
erratic, which essentially reflects the details of hardware implementation,
and from a software perspective, the type of event is an unprecise event,
which brings a tolerance check in the counter overflow testcases.

Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221102225110.3023543-28-seanjc@google.com

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x86/pmu: Update testcases to cover AMD PMU

AMD core PMU before Zen4 did not have version numbers, there were
no fixed counters, it had a hard-coded number of generic counters,
bit-width, and only ha

x86/pmu: Update testcases to cover AMD PMU

AMD core PMU before Zen4 did not have version numbers, there were
no fixed counters, it had a hard-coded number of generic counters,
bit-width, and only hardware events common across amd generations
(starting with K7) were added to amd_gp_events[] table.

All above differences are instantiated at the detection step, and it
also covers the K7 PMU registers, which is consistent with bare-metal.

Cc: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Like Xu <likexu@tencent.com>
[sean: set bases to K7 values for !PERFCTR_CORE case (reported by Paolo)]
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221102225110.3023543-27-seanjc@google.com

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x86/pmu: Add lib/x86/pmu.[c.h] and move common code to header files

Given all the PMU stuff coming in, we need e.g. lib/x86/pmu.h to hold all
of the hardware-defined stuff, e.g. #defines, accessors,

x86/pmu: Add lib/x86/pmu.[c.h] and move common code to header files

Given all the PMU stuff coming in, we need e.g. lib/x86/pmu.h to hold all
of the hardware-defined stuff, e.g. #defines, accessors, helpers and structs
that are dictated by hardware. This will greatly help with code reuse and
reduce unnecessary vm-exit.

Opportunistically move lbr msrs definition to header processor.h.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221102225110.3023543-14-seanjc@google.com

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x86/pmu: Update rdpmc testcase to cover #GP path

Specifying an unsupported PMC encoding will cause a #GP(0).

There are multiple reasons RDPMC can #GP, the one that is being relied
on to guarantee #

x86/pmu: Update rdpmc testcase to cover #GP path

Specifying an unsupported PMC encoding will cause a #GP(0).

There are multiple reasons RDPMC can #GP, the one that is being relied
on to guarantee #GP is specifically that the PMC is invalid. The most
extensible solution is to provide a safe variant.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221102225110.3023543-12-seanjc@google.com

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x86/pmu: Add PDCM check before accessing PERF_CAP register

On virtual platforms without PDCM support (e.g. AMD), #GP
failure on MSR_IA32_PERF_CAPABILITIES is completely avoidable.

Suggested-by: Sea

x86/pmu: Add PDCM check before accessing PERF_CAP register

On virtual platforms without PDCM support (e.g. AMD), #GP
failure on MSR_IA32_PERF_CAPABILITIES is completely avoidable.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221102225110.3023543-2-seanjc@google.com

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x86/apic: Add test to verify aliased xAPIC IDs both receive IPI

Verify that multiple vCPUs with the same physical xAPIC ID receive an
IPI sent to said ID. Note, on_cpu() maintains its own CPU=>ID m

x86/apic: Add test to verify aliased xAPIC IDs both receive IPI

Verify that multiple vCPUs with the same physical xAPIC ID receive an
IPI sent to said ID. Note, on_cpu() maintains its own CPU=>ID map and
is effectively unusuable after changing the xAPIC ID. Update each vCPU's
xAPIC ID from within the IRQ handler so as to avoid having to send
yet another IPI from vCPU0 to tell vCPU1 to update its ID.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221001011301.2077437-10-seanjc@google.com

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x86: nSVM: Move part of #NM test to exception test framework

Remove the boiler plate code for #NM test and move #NM exception test
into the exception test framework.

Keep the test case for the cond

x86: nSVM: Move part of #NM test to exception test framework

Remove the boiler plate code for #NM test and move #NM exception test
into the exception test framework.

Keep the test case for the condition where #NM exception is not
generated, but drop the #NM handler entirely and rely on an unexpected
exception being reported as such (the VMMCALL assertion would also fail).

Signed-off-by: Manali Shukla <manali.shukla@amd.com>
Co-developed-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221005235212.57836-9-seanjc@google.com

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nVMX: Move #OF test to generic exceptions test

Move the INTO=>#OF test, along with its more precise checking of the
exit interrupt info, to the generic nVMX exceptions test.

Move the helper that g

nVMX: Move #OF test to generic exceptions test

Move the INTO=>#OF test, along with its more precise checking of the
exit interrupt info, to the generic nVMX exceptions test.

Move the helper that generates #OF to processor.h so that it can be
reused by nSVM for an identical test.

Note, this effectively adds new checks for all other vectors, i.e.
affects more vectors than just #OF.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221005235212.57836-4-seanjc@google.com

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x86: Move helpers to generate misc exceptions to processor.h

Move nested VMX's helpers to generate miscellaenous exceptions, e.g. #DE,
to processor.h so that they can be used for nearly-identical ne

x86: Move helpers to generate misc exceptions to processor.h

Move nested VMX's helpers to generate miscellaenous exceptions, e.g. #DE,
to processor.h so that they can be used for nearly-identical nested SVM
tests.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221005235212.57836-3-seanjc@google.com

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x86: add and use *_BIT constants for CR0, CR4, EFLAGS

The "BIT" macro cannot be used in top-level assembly statements
(it can be used in functions through the "i" constraint), because
old binutils s

x86: add and use *_BIT constants for CR0, CR4, EFLAGS

The "BIT" macro cannot be used in top-level assembly statements
(it can be used in functions through the "i" constraint), because
old binutils such as the one in CentOS 7 do not support the "1UL"
syntax for numerals.

To avoid having to hard-code EFLAGS.AC being bit 18, define the constants
for CR0, CR4 and EFLAGS bits in terms of new macros for just the bit
number.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new sub-tests:

- Bug fix for the VMX-preemption timer expiration test
- Refactor SVM tests

Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new sub-tests:

- Bug fix for the VMX-preemption timer expiration test
- Refactor SVM tests to split out NPT tests
- Add tests for MCE banks to MSR test
- Add SMP Support for x86 UEFI tests
- x86: nVMX: Add VMXON #UD test (and exception cleanup)
- PMU cleanup and related nVMX bug fixes

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x86: Check platform pmu capabilities before run lbr tests

Use new helper to check whether pmu is available and Perfmon/Debug
capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to
avoid

x86: Check platform pmu capabilities before run lbr tests

Use new helper to check whether pmu is available and Perfmon/Debug
capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to
avoid test failure. The issue can be captured when enable_pmu=0.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Link: https://lore.kernel.org/r/20220711041841.126648-5-weijiang.yang@intel.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86: Skip perf related tests when platform cannot support

Add helpers to check whether MSR_CORE_PERF_GLOBAL_CTRL and rdpmc are
supported in KVM. When pmu is disabled with enable_pmu=0, reading
MSR_C

x86: Skip perf related tests when platform cannot support

Add helpers to check whether MSR_CORE_PERF_GLOBAL_CTRL and rdpmc are
supported in KVM. When pmu is disabled with enable_pmu=0, reading
MSR_CORE_PERF_GLOBAL_CTRL or executing rdpmc leads to #GP, so skip
related tests in this case to avoid test failure.

Opportunistically hoist mwait support check function as helper and
change related code.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Link: https://lore.kernel.org/r/20220711041841.126648-4-weijiang.yang@intel.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86: Use helpers to fetch supported perf capabilities

Add helpers to query PMU info from CPUID(0xA) and use them instead of
caching the information in global (to the PMU test) unions. Other tests
c

x86: Use helpers to fetch supported perf capabilities

Add helpers to query PMU info from CPUID(0xA) and use them instead of
caching the information in global (to the PMU test) unions. Other tests
can also use the helpers to check PMU capabilities.

No functional change intended.

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Link: https://lore.kernel.org/r/20220711041841.126648-3-weijiang.yang@intel.com
Co-developed-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>

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nVMX: Move wrappers of this_cpu_has() to nVMX's VM-Exit test

Move wrappers of this_cpu_has() whose sole purpose is to be queried as a
callback in VM-Exit tests into vmxexit.c in order to discourage

nVMX: Move wrappers of this_cpu_has() to nVMX's VM-Exit test

Move wrappers of this_cpu_has() whose sole purpose is to be queried as a
callback in VM-Exit tests into vmxexit.c in order to discourage general
use, i.e. force tests to use this_cpu_has().

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86: Drop cpuid_osxsave(), just use this_cpu_has(X86_FEATURE_OSXSAVE)

Drop cpuid_osxsave(), which is just an open coded implementation of
this_cpu_has(X86_FEATURE_OSXSAVE).

Signed-off-by: Sean Chri

x86: Drop cpuid_osxsave(), just use this_cpu_has(X86_FEATURE_OSXSAVE)

Drop cpuid_osxsave(), which is just an open coded implementation of
this_cpu_has(X86_FEATURE_OSXSAVE).

Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86: Provide result of RDMSR from "safe" variant

Provide the result of RDMSR from rdmsr_safe() so that it can be used by
tests that are unsure whether or not RDMSR will fault, but want the value
if

x86: Provide result of RDMSR from "safe" variant

Provide the result of RDMSR from rdmsr_safe() so that it can be used by
tests that are unsure whether or not RDMSR will fault, but want the value
if it doesn't fault.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220608235238.3881916-6-seanjc@google.com

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x86: Use "safe" helpers to implement unsafe CRs accessors

Use the "safe" helpers to read and write CR0, CR3, and CR4, so that an
unexpected fault results in a detailed message instead of an generic

x86: Use "safe" helpers to implement unsafe CRs accessors

Use the "safe" helpers to read and write CR0, CR3, and CR4, so that an
unexpected fault results in a detailed message instead of an generic
"unexpected fault" explosion.

Do not give RDMSR/WRMSR the same treatment. KUT's exception fixup uses
per-CPU data and thus needs a stable GS.base. Various tests modify
MSR_GS_BASE and routing them through the safe variants will cause
fireworks when trying to clear/read the exception vector with a garbage
GS.base.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220608235238.3881916-5-seanjc@google.com

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x86: Use "safe" terminology instead of "checking"

Rename all helpers that eat (and return) exceptions to use "safe" instead
of "checking". This aligns KUT with the kernel and KVM selftests.

Signed

x86: Use "safe" terminology instead of "checking"

Rename all helpers that eat (and return) exceptions to use "safe" instead
of "checking". This aligns KUT with the kernel and KVM selftests.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220608235238.3881916-4-seanjc@google.com

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x86: Replace spaces with tables in processor.h

Fix the myriad instances of using spaces instead of tabs in processor.h.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@go

x86: Replace spaces with tables in processor.h

Fix the myriad instances of using spaces instead of tabs in processor.h.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220608235238.3881916-3-seanjc@google.com

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x86: Use BIT() to define architectural bits

Use BIT() to define bits in EFLAGS, CR0, and CR4. Intel's SDM and AMD's
APM reference flags/features by the bit number, not by their mask, making
it absu

x86: Use BIT() to define architectural bits

Use BIT() to define bits in EFLAGS, CR0, and CR4. Intel's SDM and AMD's
APM reference flags/features by the bit number, not by their mask, making
it absurdly difficult to audit and/or add definitions.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220608235238.3881916-2-seanjc@google.com

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svm: add test for pause filter and threshold

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220322205613.250925-10-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@red

svm: add test for pause filter and threshold

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220322205613.250925-10-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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svm: add test for nested tsc scaling

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220322205613.250925-9-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>