1 #ifndef _X86_PROCESSOR_H_ 2 #define _X86_PROCESSOR_H_ 3 4 #include "libcflat.h" 5 #include "desc.h" 6 #include "msr.h" 7 #include <bitops.h> 8 #include <stdint.h> 9 10 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 11 12 #ifdef __x86_64__ 13 # define R "r" 14 # define W "q" 15 # define S "8" 16 #else 17 # define R "e" 18 # define W "l" 19 # define S "4" 20 #endif 21 22 #define DB_VECTOR 1 23 #define BP_VECTOR 3 24 #define UD_VECTOR 6 25 #define DF_VECTOR 8 26 #define TS_VECTOR 10 27 #define NP_VECTOR 11 28 #define SS_VECTOR 12 29 #define GP_VECTOR 13 30 #define PF_VECTOR 14 31 #define AC_VECTOR 17 32 #define CP_VECTOR 21 33 34 #define X86_CR0_PE_BIT (0) 35 #define X86_CR0_PE BIT(X86_CR0_PE_BIT) 36 #define X86_CR0_MP_BIT (1) 37 #define X86_CR0_MP BIT(X86_CR0_MP_BIT) 38 #define X86_CR0_EM_BIT (2) 39 #define X86_CR0_EM BIT(X86_CR0_EM_BIT) 40 #define X86_CR0_TS_BIT (3) 41 #define X86_CR0_TS BIT(X86_CR0_TS_BIT) 42 #define X86_CR0_ET_BIT (4) 43 #define X86_CR0_ET BIT(X86_CR0_ET_BIT) 44 #define X86_CR0_NE_BIT (5) 45 #define X86_CR0_NE BIT(X86_CR0_NE_BIT) 46 #define X86_CR0_WP_BIT (16) 47 #define X86_CR0_WP BIT(X86_CR0_WP_BIT) 48 #define X86_CR0_AM_BIT (18) 49 #define X86_CR0_AM BIT(X86_CR0_AM_BIT) 50 #define X86_CR0_NW_BIT (29) 51 #define X86_CR0_NW BIT(X86_CR0_NW_BIT) 52 #define X86_CR0_CD_BIT (30) 53 #define X86_CR0_CD BIT(X86_CR0_CD_BIT) 54 #define X86_CR0_PG_BIT (31) 55 #define X86_CR0_PG BIT(X86_CR0_PG_BIT) 56 57 #define X86_CR3_PCID_MASK GENMASK(11, 0) 58 59 #define X86_CR4_VME_BIT (0) 60 #define X86_CR4_VME BIT(X86_CR4_VME_BIT) 61 #define X86_CR4_PVI_BIT (1) 62 #define X86_CR4_PVI BIT(X86_CR4_PVI_BIT) 63 #define X86_CR4_TSD_BIT (2) 64 #define X86_CR4_TSD BIT(X86_CR4_TSD_BIT) 65 #define X86_CR4_DE_BIT (3) 66 #define X86_CR4_DE BIT(X86_CR4_DE_BIT) 67 #define X86_CR4_PSE_BIT (4) 68 #define X86_CR4_PSE BIT(X86_CR4_PSE_BIT) 69 #define X86_CR4_PAE_BIT (5) 70 #define X86_CR4_PAE BIT(X86_CR4_PAE_BIT) 71 #define X86_CR4_MCE_BIT (6) 72 #define X86_CR4_MCE BIT(X86_CR4_MCE_BIT) 73 #define X86_CR4_PGE_BIT (7) 74 #define X86_CR4_PGE BIT(X86_CR4_PGE_BIT) 75 #define X86_CR4_PCE_BIT (8) 76 #define X86_CR4_PCE BIT(X86_CR4_PCE_BIT) 77 #define X86_CR4_OSFXSR_BIT (9) 78 #define X86_CR4_OSFXSR BIT(X86_CR4_OSFXSR_BIT) 79 #define X86_CR4_OSXMMEXCPT_BIT (10) 80 #define X86_CR4_OSXMMEXCPT BIT(X86_CR4_OSXMMEXCPT_BIT) 81 #define X86_CR4_UMIP_BIT (11) 82 #define X86_CR4_UMIP BIT(X86_CR4_UMIP_BIT) 83 #define X86_CR4_LA57_BIT (12) 84 #define X86_CR4_LA57 BIT(X86_CR4_LA57_BIT) 85 #define X86_CR4_VMXE_BIT (13) 86 #define X86_CR4_VMXE BIT(X86_CR4_VMXE_BIT) 87 #define X86_CR4_SMXE_BIT (14) 88 #define X86_CR4_SMXE BIT(X86_CR4_SMXE_BIT) 89 /* UNUSED (15) */ 90 #define X86_CR4_FSGSBASE_BIT (16) 91 #define X86_CR4_FSGSBASE BIT(X86_CR4_FSGSBASE_BIT) 92 #define X86_CR4_PCIDE_BIT (17) 93 #define X86_CR4_PCIDE BIT(X86_CR4_PCIDE_BIT) 94 #define X86_CR4_OSXSAVE_BIT (18) 95 #define X86_CR4_OSXSAVE BIT(X86_CR4_OSXSAVE_BIT) 96 #define X86_CR4_KL_BIT (19) 97 #define X86_CR4_KL BIT(X86_CR4_KL_BIT) 98 #define X86_CR4_SMEP_BIT (20) 99 #define X86_CR4_SMEP BIT(X86_CR4_SMEP_BIT) 100 #define X86_CR4_SMAP_BIT (21) 101 #define X86_CR4_SMAP BIT(X86_CR4_SMAP_BIT) 102 #define X86_CR4_PKE_BIT (22) 103 #define X86_CR4_PKE BIT(X86_CR4_PKE_BIT) 104 #define X86_CR4_CET_BIT (23) 105 #define X86_CR4_CET BIT(X86_CR4_CET_BIT) 106 #define X86_CR4_PKS_BIT (24) 107 #define X86_CR4_PKS BIT(X86_CR4_PKS_BIT) 108 109 #define X86_EFLAGS_CF_BIT (0) 110 #define X86_EFLAGS_CF BIT(X86_EFLAGS_CF_BIT) 111 #define X86_EFLAGS_FIXED_BIT (1) 112 #define X86_EFLAGS_FIXED BIT(X86_EFLAGS_FIXED_BIT) 113 #define X86_EFLAGS_PF_BIT (2) 114 #define X86_EFLAGS_PF BIT(X86_EFLAGS_PF_BIT) 115 /* RESERVED 0 (3) */ 116 #define X86_EFLAGS_AF_BIT (4) 117 #define X86_EFLAGS_AF BIT(X86_EFLAGS_AF_BIT) 118 /* RESERVED 0 (5) */ 119 #define X86_EFLAGS_ZF_BIT (6) 120 #define X86_EFLAGS_ZF BIT(X86_EFLAGS_ZF_BIT) 121 #define X86_EFLAGS_SF_BIT (7) 122 #define X86_EFLAGS_SF BIT(X86_EFLAGS_SF_BIT) 123 #define X86_EFLAGS_TF_BIT (8) 124 #define X86_EFLAGS_TF BIT(X86_EFLAGS_TF_BIT) 125 #define X86_EFLAGS_IF_BIT (9) 126 #define X86_EFLAGS_IF BIT(X86_EFLAGS_IF_BIT) 127 #define X86_EFLAGS_DF_BIT (10) 128 #define X86_EFLAGS_DF BIT(X86_EFLAGS_DF_BIT) 129 #define X86_EFLAGS_OF_BIT (11) 130 #define X86_EFLAGS_OF BIT(X86_EFLAGS_OF_BIT) 131 #define X86_EFLAGS_IOPL GENMASK(13, 12) 132 #define X86_EFLAGS_NT_BIT (14) 133 #define X86_EFLAGS_NT BIT(X86_EFLAGS_NT_BIT) 134 /* RESERVED 0 (15) */ 135 #define X86_EFLAGS_RF_BIT (16) 136 #define X86_EFLAGS_RF BIT(X86_EFLAGS_RF_BIT) 137 #define X86_EFLAGS_VM_BIT (17) 138 #define X86_EFLAGS_VM BIT(X86_EFLAGS_VM_BIT) 139 #define X86_EFLAGS_AC_BIT (18) 140 #define X86_EFLAGS_AC BIT(X86_EFLAGS_AC_BIT) 141 #define X86_EFLAGS_VIF_BIT (19) 142 #define X86_EFLAGS_VIF BIT(X86_EFLAGS_VIF_BIT) 143 #define X86_EFLAGS_VIP_BIT (20) 144 #define X86_EFLAGS_VIP BIT(X86_EFLAGS_VIP_BIT) 145 #define X86_EFLAGS_ID_BIT (21) 146 #define X86_EFLAGS_ID BIT(X86_EFLAGS_ID_BIT) 147 148 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 149 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 150 151 152 /* 153 * CPU features 154 */ 155 156 enum cpuid_output_regs { 157 EAX, 158 EBX, 159 ECX, 160 EDX 161 }; 162 163 struct cpuid { u32 a, b, c, d; }; 164 165 static inline struct cpuid raw_cpuid(u32 function, u32 index) 166 { 167 struct cpuid r; 168 asm volatile ("cpuid" 169 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 170 : "0"(function), "2"(index)); 171 return r; 172 } 173 174 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 175 { 176 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 177 if (level < function) 178 return (struct cpuid) { 0, 0, 0, 0 }; 179 return raw_cpuid(function, index); 180 } 181 182 static inline struct cpuid cpuid(u32 function) 183 { 184 return cpuid_indexed(function, 0); 185 } 186 187 static inline u8 cpuid_maxphyaddr(void) 188 { 189 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 190 return 36; 191 return raw_cpuid(0x80000008, 0).a & 0xff; 192 } 193 194 static inline bool is_intel(void) 195 { 196 struct cpuid c = cpuid(0); 197 u32 name[4] = {c.b, c.d, c.c }; 198 199 return strcmp((char *)name, "GenuineIntel") == 0; 200 } 201 202 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 203 (c << 8) | d) 204 205 /* 206 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 207 * CPUID meta-data: 208 * 209 * [63:32] : input value for EAX 210 * [31:16] : input value for ECX 211 * [15:8] : output register 212 * [7:0] : bit position in output register 213 */ 214 215 /* 216 * Basic Leafs, a.k.a. Intel defined 217 */ 218 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 219 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 220 #define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) 221 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 222 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 223 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 224 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 225 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 226 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 227 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 228 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 229 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 230 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 231 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 232 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 233 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 234 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 235 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 236 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 237 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 238 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 239 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 240 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 241 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 242 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 243 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 244 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 245 #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) 246 #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) 247 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 248 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 249 #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) 250 251 /* 252 * Extended Leafs, a.k.a. AMD defined 253 */ 254 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 255 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 256 #define X86_FEATURE_GBPAGES (CPUID(0x80000001, 0, EDX, 26)) 257 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 258 #define X86_FEATURE_LM (CPUID(0x80000001, 0, EDX, 29)) 259 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 260 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 261 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 262 #define X86_FEATURE_LBRV (CPUID(0x8000000A, 0, EDX, 1)) 263 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 264 #define X86_FEATURE_TSCRATEMSR (CPUID(0x8000000A, 0, EDX, 4)) 265 #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) 266 #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) 267 #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) 268 269 270 static inline bool this_cpu_has(u64 feature) 271 { 272 u32 input_eax = feature >> 32; 273 u32 input_ecx = (feature >> 16) & 0xffff; 274 u32 output_reg = (feature >> 8) & 0xff; 275 u8 bit = feature & 0xff; 276 struct cpuid c; 277 u32 *tmp; 278 279 c = cpuid_indexed(input_eax, input_ecx); 280 tmp = (u32 *)&c; 281 282 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 283 } 284 285 struct far_pointer32 { 286 u32 offset; 287 u16 selector; 288 } __attribute__((packed)); 289 290 struct descriptor_table_ptr { 291 u16 limit; 292 ulong base; 293 } __attribute__((packed)); 294 295 static inline void clac(void) 296 { 297 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 298 } 299 300 static inline void stac(void) 301 { 302 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 303 } 304 305 static inline u16 read_cs(void) 306 { 307 unsigned val; 308 309 asm volatile ("mov %%cs, %0" : "=mr"(val)); 310 return val; 311 } 312 313 static inline u16 read_ds(void) 314 { 315 unsigned val; 316 317 asm volatile ("mov %%ds, %0" : "=mr"(val)); 318 return val; 319 } 320 321 static inline u16 read_es(void) 322 { 323 unsigned val; 324 325 asm volatile ("mov %%es, %0" : "=mr"(val)); 326 return val; 327 } 328 329 static inline u16 read_ss(void) 330 { 331 unsigned val; 332 333 asm volatile ("mov %%ss, %0" : "=mr"(val)); 334 return val; 335 } 336 337 static inline u16 read_fs(void) 338 { 339 unsigned val; 340 341 asm volatile ("mov %%fs, %0" : "=mr"(val)); 342 return val; 343 } 344 345 static inline u16 read_gs(void) 346 { 347 unsigned val; 348 349 asm volatile ("mov %%gs, %0" : "=mr"(val)); 350 return val; 351 } 352 353 static inline unsigned long read_rflags(void) 354 { 355 unsigned long f; 356 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 357 return f; 358 } 359 360 static inline void write_ds(unsigned val) 361 { 362 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 363 } 364 365 static inline void write_es(unsigned val) 366 { 367 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 368 } 369 370 static inline void write_ss(unsigned val) 371 { 372 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 373 } 374 375 static inline void write_fs(unsigned val) 376 { 377 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 378 } 379 380 static inline void write_gs(unsigned val) 381 { 382 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 383 } 384 385 static inline void write_rflags(unsigned long f) 386 { 387 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 388 } 389 390 static inline void set_iopl(int iopl) 391 { 392 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 393 flags |= iopl * (X86_EFLAGS_IOPL / 3); 394 write_rflags(flags); 395 } 396 397 /* 398 * Don't use the safe variants for rdmsr() or wrmsr(). The exception fixup 399 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests 400 * temporarily modify MSR_GS_BASE and will explode when trying to determine 401 * whether or not RDMSR/WRMSR faulted. 402 */ 403 static inline u64 rdmsr(u32 index) 404 { 405 u32 a, d; 406 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 407 return a | ((u64)d << 32); 408 } 409 410 static inline void wrmsr(u32 index, u64 val) 411 { 412 u32 a = val, d = val >> 32; 413 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 414 } 415 416 static inline int rdmsr_safe(u32 index, uint64_t *val) 417 { 418 uint32_t a, d; 419 420 asm volatile (ASM_TRY("1f") 421 "rdmsr\n\t" 422 "1:" 423 : "=a"(a), "=d"(d) 424 : "c"(index) : "memory"); 425 426 *val = (uint64_t)a | ((uint64_t)d << 32); 427 return exception_vector(); 428 } 429 430 static inline int wrmsr_safe(u32 index, u64 val) 431 { 432 u32 a = val, d = val >> 32; 433 434 asm volatile (ASM_TRY("1f") 435 "wrmsr\n\t" 436 "1:" 437 : : "a"(a), "d"(d), "c"(index) : "memory"); 438 return exception_vector(); 439 } 440 441 static inline uint64_t rdpmc(uint32_t index) 442 { 443 uint32_t a, d; 444 asm volatile ("rdpmc" : "=a"(a), "=d"(d) : "c"(index)); 445 return a | ((uint64_t)d << 32); 446 } 447 448 static inline int write_cr0_safe(ulong val) 449 { 450 asm volatile(ASM_TRY("1f") 451 "mov %0,%%cr0\n\t" 452 "1:": : "r" (val)); 453 return exception_vector(); 454 } 455 456 static inline void write_cr0(ulong val) 457 { 458 int vector = write_cr0_safe(val); 459 460 assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx", 461 vector, val); 462 } 463 464 static inline ulong read_cr0(void) 465 { 466 ulong val; 467 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 468 return val; 469 } 470 471 static inline void write_cr2(ulong val) 472 { 473 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 474 } 475 476 static inline ulong read_cr2(void) 477 { 478 ulong val; 479 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 480 return val; 481 } 482 483 static inline int write_cr3_safe(ulong val) 484 { 485 asm volatile(ASM_TRY("1f") 486 "mov %0,%%cr3\n\t" 487 "1:": : "r" (val)); 488 return exception_vector(); 489 } 490 491 static inline void write_cr3(ulong val) 492 { 493 int vector = write_cr3_safe(val); 494 495 assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx", 496 vector, val); 497 } 498 499 static inline ulong read_cr3(void) 500 { 501 ulong val; 502 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 503 return val; 504 } 505 506 static inline void update_cr3(void *cr3) 507 { 508 write_cr3((ulong)cr3); 509 } 510 511 static inline int write_cr4_safe(ulong val) 512 { 513 asm volatile(ASM_TRY("1f") 514 "mov %0,%%cr4\n\t" 515 "1:": : "r" (val)); 516 return exception_vector(); 517 } 518 519 static inline void write_cr4(ulong val) 520 { 521 int vector = write_cr4_safe(val); 522 523 assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx", 524 vector, val); 525 } 526 527 static inline ulong read_cr4(void) 528 { 529 ulong val; 530 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 531 return val; 532 } 533 534 static inline void write_cr8(ulong val) 535 { 536 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 537 } 538 539 static inline ulong read_cr8(void) 540 { 541 ulong val; 542 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 543 return val; 544 } 545 546 static inline void lgdt(const struct descriptor_table_ptr *ptr) 547 { 548 asm volatile ("lgdt %0" : : "m"(*ptr)); 549 } 550 551 static inline void sgdt(struct descriptor_table_ptr *ptr) 552 { 553 asm volatile ("sgdt %0" : "=m"(*ptr)); 554 } 555 556 static inline void lidt(const struct descriptor_table_ptr *ptr) 557 { 558 asm volatile ("lidt %0" : : "m"(*ptr)); 559 } 560 561 static inline void sidt(struct descriptor_table_ptr *ptr) 562 { 563 asm volatile ("sidt %0" : "=m"(*ptr)); 564 } 565 566 static inline void lldt(u16 val) 567 { 568 asm volatile ("lldt %0" : : "rm"(val)); 569 } 570 571 static inline u16 sldt(void) 572 { 573 u16 val; 574 asm volatile ("sldt %0" : "=rm"(val)); 575 return val; 576 } 577 578 static inline void ltr(u16 val) 579 { 580 asm volatile ("ltr %0" : : "rm"(val)); 581 } 582 583 static inline u16 str(void) 584 { 585 u16 val; 586 asm volatile ("str %0" : "=rm"(val)); 587 return val; 588 } 589 590 static inline void write_dr0(void *val) 591 { 592 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); 593 } 594 595 static inline void write_dr1(void *val) 596 { 597 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); 598 } 599 600 static inline void write_dr2(void *val) 601 { 602 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); 603 } 604 605 static inline void write_dr3(void *val) 606 { 607 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); 608 } 609 610 static inline void write_dr6(ulong val) 611 { 612 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 613 } 614 615 static inline ulong read_dr6(void) 616 { 617 ulong val; 618 asm volatile ("mov %%dr6, %0" : "=r"(val)); 619 return val; 620 } 621 622 static inline void write_dr7(ulong val) 623 { 624 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 625 } 626 627 static inline ulong read_dr7(void) 628 { 629 ulong val; 630 asm volatile ("mov %%dr7, %0" : "=r"(val)); 631 return val; 632 } 633 634 static inline void pause(void) 635 { 636 asm volatile ("pause"); 637 } 638 639 static inline void cli(void) 640 { 641 asm volatile ("cli"); 642 } 643 644 static inline void sti(void) 645 { 646 asm volatile ("sti"); 647 } 648 649 static inline unsigned long long rdrand(void) 650 { 651 long long r; 652 653 asm volatile("rdrand %0\n\t" 654 "jc 1f\n\t" 655 "mov $0, %0\n\t" 656 "1:\n\t" : "=r" (r)); 657 return r; 658 } 659 660 static inline unsigned long long rdtsc(void) 661 { 662 long long r; 663 664 #ifdef __x86_64__ 665 unsigned a, d; 666 667 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 668 r = a | ((long long)d << 32); 669 #else 670 asm volatile ("rdtsc" : "=A"(r)); 671 #endif 672 return r; 673 } 674 675 /* 676 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 677 * executed immediately before rdtsc ensures that rdtsc will be 678 * executed only after all previous instructions have executed and all 679 * previous loads and stores are globally visible. In addition, the 680 * lfence immediately after rdtsc ensures that rdtsc will be executed 681 * prior to the execution of any subsequent instruction. 682 */ 683 static inline unsigned long long fenced_rdtsc(void) 684 { 685 unsigned long long tsc; 686 687 #ifdef __x86_64__ 688 unsigned int eax, edx; 689 690 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 691 tsc = eax | ((unsigned long long)edx << 32); 692 #else 693 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 694 #endif 695 return tsc; 696 } 697 698 static inline unsigned long long rdtscp(u32 *aux) 699 { 700 long long r; 701 702 #ifdef __x86_64__ 703 unsigned a, d; 704 705 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 706 r = a | ((long long)d << 32); 707 #else 708 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 709 #endif 710 return r; 711 } 712 713 static inline void wrtsc(u64 tsc) 714 { 715 wrmsr(MSR_IA32_TSC, tsc); 716 } 717 718 static inline void irq_disable(void) 719 { 720 asm volatile("cli"); 721 } 722 723 /* Note that irq_enable() does not ensure an interrupt shadow due 724 * to the vagaries of compiler optimizations. If you need the 725 * shadow, use a single asm with "sti" and the instruction after it. 726 */ 727 static inline void irq_enable(void) 728 { 729 asm volatile("sti"); 730 } 731 732 static inline void invlpg(volatile void *va) 733 { 734 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 735 } 736 737 static inline void safe_halt(void) 738 { 739 asm volatile("sti; hlt"); 740 } 741 742 static inline u32 read_pkru(void) 743 { 744 unsigned int eax, edx; 745 unsigned int ecx = 0; 746 unsigned int pkru; 747 748 asm volatile(".byte 0x0f,0x01,0xee\n\t" 749 : "=a" (eax), "=d" (edx) 750 : "c" (ecx)); 751 pkru = eax; 752 return pkru; 753 } 754 755 static inline void write_pkru(u32 pkru) 756 { 757 unsigned int eax = pkru; 758 unsigned int ecx = 0; 759 unsigned int edx = 0; 760 761 asm volatile(".byte 0x0f,0x01,0xef\n\t" 762 : : "a" (eax), "c" (ecx), "d" (edx)); 763 } 764 765 static inline bool is_canonical(u64 addr) 766 { 767 int va_width = (raw_cpuid(0x80000008, 0).a & 0xff00) >> 8; 768 int shift_amt = 64 - va_width; 769 770 return (s64)(addr << shift_amt) >> shift_amt == addr; 771 } 772 773 static inline void clear_bit(int bit, u8 *addr) 774 { 775 __asm__ __volatile__("btr %1, %0" 776 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 777 } 778 779 static inline void set_bit(int bit, u8 *addr) 780 { 781 __asm__ __volatile__("bts %1, %0" 782 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 783 } 784 785 static inline void flush_tlb(void) 786 { 787 ulong cr4; 788 789 cr4 = read_cr4(); 790 write_cr4(cr4 ^ X86_CR4_PGE); 791 write_cr4(cr4); 792 } 793 794 static inline void generate_non_canonical_gp(void) 795 { 796 *(volatile u64 *)NONCANONICAL = 0; 797 } 798 799 static inline void generate_ud(void) 800 { 801 asm volatile ("ud2"); 802 } 803 804 static inline void generate_de(void) 805 { 806 asm volatile ( 807 "xor %%eax, %%eax\n\t" 808 "xor %%ebx, %%ebx\n\t" 809 "xor %%edx, %%edx\n\t" 810 "idiv %%ebx\n\t" 811 ::: "eax", "ebx", "edx"); 812 } 813 814 static inline void generate_bp(void) 815 { 816 asm volatile ("int3"); 817 } 818 819 static inline void generate_single_step_db(void) 820 { 821 write_rflags(read_rflags() | X86_EFLAGS_TF); 822 asm volatile("nop"); 823 } 824 825 static inline uint64_t generate_usermode_ac(void) 826 { 827 /* 828 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 829 * Disclaimer: It is assumed that the stack pointer is aligned 830 * on a 16-byte boundary as x86_64 stacks should be. 831 */ 832 asm volatile("movq $0, -0x4(%rsp)"); 833 834 return 0; 835 } 836 837 static inline u8 pmu_version(void) 838 { 839 return cpuid(10).a & 0xff; 840 } 841 842 static inline bool this_cpu_has_pmu(void) 843 { 844 return !!pmu_version(); 845 } 846 847 static inline bool this_cpu_has_perf_global_ctrl(void) 848 { 849 return pmu_version() > 1; 850 } 851 852 static inline u8 pmu_nr_gp_counters(void) 853 { 854 return (cpuid(10).a >> 8) & 0xff; 855 } 856 857 static inline u8 pmu_gp_counter_width(void) 858 { 859 return (cpuid(10).a >> 16) & 0xff; 860 } 861 862 static inline u8 pmu_gp_counter_mask_length(void) 863 { 864 return (cpuid(10).a >> 24) & 0xff; 865 } 866 867 static inline u8 pmu_nr_fixed_counters(void) 868 { 869 struct cpuid id = cpuid(10); 870 871 if ((id.a & 0xff) > 1) 872 return id.d & 0x1f; 873 else 874 return 0; 875 } 876 877 static inline u8 pmu_fixed_counter_width(void) 878 { 879 struct cpuid id = cpuid(10); 880 881 if ((id.a & 0xff) > 1) 882 return (id.d >> 5) & 0xff; 883 else 884 return 0; 885 } 886 887 static inline bool pmu_gp_counter_is_available(int i) 888 { 889 /* CPUID.0xA.EBX bit is '1 if they counter is NOT available. */ 890 return !(cpuid(10).b & BIT(i)); 891 } 892 893 #endif 894