1 #ifndef _X86_PROCESSOR_H_ 2 #define _X86_PROCESSOR_H_ 3 4 #include "libcflat.h" 5 #include "desc.h" 6 #include "msr.h" 7 #include <bitops.h> 8 #include <stdint.h> 9 10 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 11 12 #ifdef __x86_64__ 13 # define R "r" 14 # define W "q" 15 # define S "8" 16 #else 17 # define R "e" 18 # define W "l" 19 # define S "4" 20 #endif 21 22 #define DB_VECTOR 1 23 #define BP_VECTOR 3 24 #define UD_VECTOR 6 25 #define DF_VECTOR 8 26 #define TS_VECTOR 10 27 #define NP_VECTOR 11 28 #define SS_VECTOR 12 29 #define GP_VECTOR 13 30 #define PF_VECTOR 14 31 #define AC_VECTOR 17 32 #define CP_VECTOR 21 33 34 #define X86_CR0_PE_BIT (0) 35 #define X86_CR0_PE BIT(X86_CR0_PE_BIT) 36 #define X86_CR0_MP_BIT (1) 37 #define X86_CR0_MP BIT(X86_CR0_MP_BIT) 38 #define X86_CR0_EM_BIT (2) 39 #define X86_CR0_EM BIT(X86_CR0_EM_BIT) 40 #define X86_CR0_TS_BIT (3) 41 #define X86_CR0_TS BIT(X86_CR0_TS_BIT) 42 #define X86_CR0_ET_BIT (4) 43 #define X86_CR0_ET BIT(X86_CR0_ET_BIT) 44 #define X86_CR0_NE_BIT (5) 45 #define X86_CR0_NE BIT(X86_CR0_NE_BIT) 46 #define X86_CR0_WP_BIT (16) 47 #define X86_CR0_WP BIT(X86_CR0_WP_BIT) 48 #define X86_CR0_AM_BIT (18) 49 #define X86_CR0_AM BIT(X86_CR0_AM_BIT) 50 #define X86_CR0_NW_BIT (29) 51 #define X86_CR0_NW BIT(X86_CR0_NW_BIT) 52 #define X86_CR0_CD_BIT (30) 53 #define X86_CR0_CD BIT(X86_CR0_CD_BIT) 54 #define X86_CR0_PG_BIT (31) 55 #define X86_CR0_PG BIT(X86_CR0_PG_BIT) 56 57 #define X86_CR3_PCID_MASK GENMASK(11, 0) 58 59 #define X86_CR4_VME_BIT (0) 60 #define X86_CR4_VME BIT(X86_CR4_VME_BIT) 61 #define X86_CR4_PVI_BIT (1) 62 #define X86_CR4_PVI BIT(X86_CR4_PVI_BIT) 63 #define X86_CR4_TSD_BIT (2) 64 #define X86_CR4_TSD BIT(X86_CR4_TSD_BIT) 65 #define X86_CR4_DE_BIT (3) 66 #define X86_CR4_DE BIT(X86_CR4_DE_BIT) 67 #define X86_CR4_PSE_BIT (4) 68 #define X86_CR4_PSE BIT(X86_CR4_PSE_BIT) 69 #define X86_CR4_PAE_BIT (5) 70 #define X86_CR4_PAE BIT(X86_CR4_PAE_BIT) 71 #define X86_CR4_MCE_BIT (6) 72 #define X86_CR4_MCE BIT(X86_CR4_MCE_BIT) 73 #define X86_CR4_PGE_BIT (7) 74 #define X86_CR4_PGE BIT(X86_CR4_PGE_BIT) 75 #define X86_CR4_PCE_BIT (8) 76 #define X86_CR4_PCE BIT(X86_CR4_PCE_BIT) 77 #define X86_CR4_OSFXSR_BIT (9) 78 #define X86_CR4_OSFXSR BIT(X86_CR4_OSFXSR_BIT) 79 #define X86_CR4_OSXMMEXCPT_BIT (10) 80 #define X86_CR4_OSXMMEXCPT BIT(X86_CR4_OSXMMEXCPT_BIT) 81 #define X86_CR4_UMIP_BIT (11) 82 #define X86_CR4_UMIP BIT(X86_CR4_UMIP_BIT) 83 #define X86_CR4_LA57_BIT (12) 84 #define X86_CR4_LA57 BIT(X86_CR4_LA57_BIT) 85 #define X86_CR4_VMXE_BIT (13) 86 #define X86_CR4_VMXE BIT(X86_CR4_VMXE_BIT) 87 #define X86_CR4_SMXE_BIT (14) 88 #define X86_CR4_SMXE BIT(X86_CR4_SMXE_BIT) 89 /* UNUSED (15) */ 90 #define X86_CR4_FSGSBASE_BIT (16) 91 #define X86_CR4_FSGSBASE BIT(X86_CR4_FSGSBASE_BIT) 92 #define X86_CR4_PCIDE_BIT (17) 93 #define X86_CR4_PCIDE BIT(X86_CR4_PCIDE_BIT) 94 #define X86_CR4_OSXSAVE_BIT (18) 95 #define X86_CR4_OSXSAVE BIT(X86_CR4_OSXSAVE_BIT) 96 #define X86_CR4_KL_BIT (19) 97 #define X86_CR4_KL BIT(X86_CR4_KL_BIT) 98 #define X86_CR4_SMEP_BIT (20) 99 #define X86_CR4_SMEP BIT(X86_CR4_SMEP_BIT) 100 #define X86_CR4_SMAP_BIT (21) 101 #define X86_CR4_SMAP BIT(X86_CR4_SMAP_BIT) 102 #define X86_CR4_PKE_BIT (22) 103 #define X86_CR4_PKE BIT(X86_CR4_PKE_BIT) 104 #define X86_CR4_CET_BIT (23) 105 #define X86_CR4_CET BIT(X86_CR4_CET_BIT) 106 #define X86_CR4_PKS_BIT (24) 107 #define X86_CR4_PKS BIT(X86_CR4_PKS_BIT) 108 109 #define X86_EFLAGS_CF_BIT (0) 110 #define X86_EFLAGS_CF BIT(X86_EFLAGS_CF_BIT) 111 #define X86_EFLAGS_FIXED_BIT (1) 112 #define X86_EFLAGS_FIXED BIT(X86_EFLAGS_FIXED_BIT) 113 #define X86_EFLAGS_PF_BIT (2) 114 #define X86_EFLAGS_PF BIT(X86_EFLAGS_PF_BIT) 115 /* RESERVED 0 (3) */ 116 #define X86_EFLAGS_AF_BIT (4) 117 #define X86_EFLAGS_AF BIT(X86_EFLAGS_AF_BIT) 118 /* RESERVED 0 (5) */ 119 #define X86_EFLAGS_ZF_BIT (6) 120 #define X86_EFLAGS_ZF BIT(X86_EFLAGS_ZF_BIT) 121 #define X86_EFLAGS_SF_BIT (7) 122 #define X86_EFLAGS_SF BIT(X86_EFLAGS_SF_BIT) 123 #define X86_EFLAGS_TF_BIT (8) 124 #define X86_EFLAGS_TF BIT(X86_EFLAGS_TF_BIT) 125 #define X86_EFLAGS_IF_BIT (9) 126 #define X86_EFLAGS_IF BIT(X86_EFLAGS_IF_BIT) 127 #define X86_EFLAGS_DF_BIT (10) 128 #define X86_EFLAGS_DF BIT(X86_EFLAGS_DF_BIT) 129 #define X86_EFLAGS_OF_BIT (11) 130 #define X86_EFLAGS_OF BIT(X86_EFLAGS_OF_BIT) 131 #define X86_EFLAGS_IOPL GENMASK(13, 12) 132 #define X86_EFLAGS_NT_BIT (14) 133 #define X86_EFLAGS_NT BIT(X86_EFLAGS_NT_BIT) 134 /* RESERVED 0 (15) */ 135 #define X86_EFLAGS_RF_BIT (16) 136 #define X86_EFLAGS_RF BIT(X86_EFLAGS_RF_BIT) 137 #define X86_EFLAGS_VM_BIT (17) 138 #define X86_EFLAGS_VM BIT(X86_EFLAGS_VM_BIT) 139 #define X86_EFLAGS_AC_BIT (18) 140 #define X86_EFLAGS_AC BIT(X86_EFLAGS_AC_BIT) 141 #define X86_EFLAGS_VIF_BIT (19) 142 #define X86_EFLAGS_VIF BIT(X86_EFLAGS_VIF_BIT) 143 #define X86_EFLAGS_VIP_BIT (20) 144 #define X86_EFLAGS_VIP BIT(X86_EFLAGS_VIP_BIT) 145 #define X86_EFLAGS_ID_BIT (21) 146 #define X86_EFLAGS_ID BIT(X86_EFLAGS_ID_BIT) 147 148 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 149 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 150 151 152 /* 153 * CPU features 154 */ 155 156 enum cpuid_output_regs { 157 EAX, 158 EBX, 159 ECX, 160 EDX 161 }; 162 163 struct cpuid { u32 a, b, c, d; }; 164 165 static inline struct cpuid raw_cpuid(u32 function, u32 index) 166 { 167 struct cpuid r; 168 asm volatile ("cpuid" 169 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 170 : "0"(function), "2"(index)); 171 return r; 172 } 173 174 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 175 { 176 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 177 if (level < function) 178 return (struct cpuid) { 0, 0, 0, 0 }; 179 return raw_cpuid(function, index); 180 } 181 182 static inline struct cpuid cpuid(u32 function) 183 { 184 return cpuid_indexed(function, 0); 185 } 186 187 static inline u8 cpuid_maxphyaddr(void) 188 { 189 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 190 return 36; 191 return raw_cpuid(0x80000008, 0).a & 0xff; 192 } 193 194 static inline bool is_intel(void) 195 { 196 struct cpuid c = cpuid(0); 197 u32 name[4] = {c.b, c.d, c.c }; 198 199 return strcmp((char *)name, "GenuineIntel") == 0; 200 } 201 202 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 203 (c << 8) | d) 204 205 /* 206 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 207 * CPUID meta-data: 208 * 209 * [63:32] : input value for EAX 210 * [31:16] : input value for ECX 211 * [15:8] : output register 212 * [7:0] : bit position in output register 213 */ 214 215 /* 216 * Basic Leafs, a.k.a. Intel defined 217 */ 218 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 219 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 220 #define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) 221 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 222 #define X86_FEATURE_X2APIC (CPUID(0x1, 0, ECX, 21)) 223 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 224 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 225 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 226 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 227 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 228 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 229 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 230 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 231 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 232 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 233 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 234 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 235 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 236 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 237 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 238 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 239 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 240 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 241 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 242 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 243 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 244 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 245 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 246 #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) 247 #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) 248 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 249 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 250 #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) 251 252 /* 253 * Extended Leafs, a.k.a. AMD defined 254 */ 255 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 256 #define X86_FEATURE_PERFCTR_CORE (CPUID(0x80000001, 0, ECX, 23)) 257 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 258 #define X86_FEATURE_GBPAGES (CPUID(0x80000001, 0, EDX, 26)) 259 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 260 #define X86_FEATURE_LM (CPUID(0x80000001, 0, EDX, 29)) 261 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 262 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 263 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 264 #define X86_FEATURE_LBRV (CPUID(0x8000000A, 0, EDX, 1)) 265 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 266 #define X86_FEATURE_TSCRATEMSR (CPUID(0x8000000A, 0, EDX, 4)) 267 #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) 268 #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) 269 #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) 270 #define X86_FEATURE_AMD_PMU_V2 (CPUID(0x80000022, 0, EAX, 0)) 271 272 static inline bool this_cpu_has(u64 feature) 273 { 274 u32 input_eax = feature >> 32; 275 u32 input_ecx = (feature >> 16) & 0xffff; 276 u32 output_reg = (feature >> 8) & 0xff; 277 u8 bit = feature & 0xff; 278 struct cpuid c; 279 u32 *tmp; 280 281 c = cpuid_indexed(input_eax, input_ecx); 282 tmp = (u32 *)&c; 283 284 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 285 } 286 287 struct far_pointer32 { 288 u32 offset; 289 u16 selector; 290 } __attribute__((packed)); 291 292 struct descriptor_table_ptr { 293 u16 limit; 294 ulong base; 295 } __attribute__((packed)); 296 297 static inline void clac(void) 298 { 299 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 300 } 301 302 static inline void stac(void) 303 { 304 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 305 } 306 307 static inline u16 read_cs(void) 308 { 309 unsigned val; 310 311 asm volatile ("mov %%cs, %0" : "=mr"(val)); 312 return val; 313 } 314 315 static inline u16 read_ds(void) 316 { 317 unsigned val; 318 319 asm volatile ("mov %%ds, %0" : "=mr"(val)); 320 return val; 321 } 322 323 static inline u16 read_es(void) 324 { 325 unsigned val; 326 327 asm volatile ("mov %%es, %0" : "=mr"(val)); 328 return val; 329 } 330 331 static inline u16 read_ss(void) 332 { 333 unsigned val; 334 335 asm volatile ("mov %%ss, %0" : "=mr"(val)); 336 return val; 337 } 338 339 static inline u16 read_fs(void) 340 { 341 unsigned val; 342 343 asm volatile ("mov %%fs, %0" : "=mr"(val)); 344 return val; 345 } 346 347 static inline u16 read_gs(void) 348 { 349 unsigned val; 350 351 asm volatile ("mov %%gs, %0" : "=mr"(val)); 352 return val; 353 } 354 355 static inline unsigned long read_rflags(void) 356 { 357 unsigned long f; 358 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 359 return f; 360 } 361 362 static inline void write_ds(unsigned val) 363 { 364 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 365 } 366 367 static inline void write_es(unsigned val) 368 { 369 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 370 } 371 372 static inline void write_ss(unsigned val) 373 { 374 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 375 } 376 377 static inline void write_fs(unsigned val) 378 { 379 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 380 } 381 382 static inline void write_gs(unsigned val) 383 { 384 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 385 } 386 387 static inline void write_rflags(unsigned long f) 388 { 389 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 390 } 391 392 static inline void set_iopl(int iopl) 393 { 394 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 395 flags |= iopl * (X86_EFLAGS_IOPL / 3); 396 write_rflags(flags); 397 } 398 399 /* 400 * Don't use the safe variants for rdmsr() or wrmsr(). The exception fixup 401 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests 402 * temporarily modify MSR_GS_BASE and will explode when trying to determine 403 * whether or not RDMSR/WRMSR faulted. 404 */ 405 static inline u64 rdmsr(u32 index) 406 { 407 u32 a, d; 408 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 409 return a | ((u64)d << 32); 410 } 411 412 static inline void wrmsr(u32 index, u64 val) 413 { 414 u32 a = val, d = val >> 32; 415 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 416 } 417 418 static inline int rdmsr_safe(u32 index, uint64_t *val) 419 { 420 uint32_t a, d; 421 422 asm volatile (ASM_TRY("1f") 423 "rdmsr\n\t" 424 "1:" 425 : "=a"(a), "=d"(d) 426 : "c"(index) : "memory"); 427 428 *val = (uint64_t)a | ((uint64_t)d << 32); 429 return exception_vector(); 430 } 431 432 static inline int wrmsr_safe(u32 index, u64 val) 433 { 434 u32 a = val, d = val >> 32; 435 436 asm volatile (ASM_TRY("1f") 437 "wrmsr\n\t" 438 "1:" 439 : : "a"(a), "d"(d), "c"(index) : "memory"); 440 return exception_vector(); 441 } 442 443 static inline int rdpmc_safe(u32 index, uint64_t *val) 444 { 445 uint32_t a, d; 446 447 asm volatile (ASM_TRY("1f") 448 "rdpmc\n\t" 449 "1:" 450 : "=a"(a), "=d"(d) : "c"(index) : "memory"); 451 *val = (uint64_t)a | ((uint64_t)d << 32); 452 return exception_vector(); 453 } 454 455 static inline uint64_t rdpmc(unsigned int index) 456 { 457 uint64_t val; 458 int vector = rdpmc_safe(index, &val); 459 460 assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")", 461 exception_mnemonic(vector), index); 462 return val; 463 } 464 465 static inline int write_cr0_safe(ulong val) 466 { 467 asm volatile(ASM_TRY("1f") 468 "mov %0,%%cr0\n\t" 469 "1:": : "r" (val)); 470 return exception_vector(); 471 } 472 473 static inline void write_cr0(ulong val) 474 { 475 int vector = write_cr0_safe(val); 476 477 assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx", 478 vector, val); 479 } 480 481 static inline ulong read_cr0(void) 482 { 483 ulong val; 484 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 485 return val; 486 } 487 488 static inline void write_cr2(ulong val) 489 { 490 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 491 } 492 493 static inline ulong read_cr2(void) 494 { 495 ulong val; 496 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 497 return val; 498 } 499 500 static inline int write_cr3_safe(ulong val) 501 { 502 asm volatile(ASM_TRY("1f") 503 "mov %0,%%cr3\n\t" 504 "1:": : "r" (val)); 505 return exception_vector(); 506 } 507 508 static inline void write_cr3(ulong val) 509 { 510 int vector = write_cr3_safe(val); 511 512 assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx", 513 vector, val); 514 } 515 516 static inline ulong read_cr3(void) 517 { 518 ulong val; 519 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 520 return val; 521 } 522 523 static inline void update_cr3(void *cr3) 524 { 525 write_cr3((ulong)cr3); 526 } 527 528 static inline int write_cr4_safe(ulong val) 529 { 530 asm volatile(ASM_TRY("1f") 531 "mov %0,%%cr4\n\t" 532 "1:": : "r" (val)); 533 return exception_vector(); 534 } 535 536 static inline void write_cr4(ulong val) 537 { 538 int vector = write_cr4_safe(val); 539 540 assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx", 541 vector, val); 542 } 543 544 static inline ulong read_cr4(void) 545 { 546 ulong val; 547 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 548 return val; 549 } 550 551 static inline void write_cr8(ulong val) 552 { 553 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 554 } 555 556 static inline ulong read_cr8(void) 557 { 558 ulong val; 559 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 560 return val; 561 } 562 563 static inline void lgdt(const struct descriptor_table_ptr *ptr) 564 { 565 asm volatile ("lgdt %0" : : "m"(*ptr)); 566 } 567 568 static inline void sgdt(struct descriptor_table_ptr *ptr) 569 { 570 asm volatile ("sgdt %0" : "=m"(*ptr)); 571 } 572 573 static inline void lidt(const struct descriptor_table_ptr *ptr) 574 { 575 asm volatile ("lidt %0" : : "m"(*ptr)); 576 } 577 578 static inline void sidt(struct descriptor_table_ptr *ptr) 579 { 580 asm volatile ("sidt %0" : "=m"(*ptr)); 581 } 582 583 static inline void lldt(u16 val) 584 { 585 asm volatile ("lldt %0" : : "rm"(val)); 586 } 587 588 static inline u16 sldt(void) 589 { 590 u16 val; 591 asm volatile ("sldt %0" : "=rm"(val)); 592 return val; 593 } 594 595 static inline void ltr(u16 val) 596 { 597 asm volatile ("ltr %0" : : "rm"(val)); 598 } 599 600 static inline u16 str(void) 601 { 602 u16 val; 603 asm volatile ("str %0" : "=rm"(val)); 604 return val; 605 } 606 607 static inline void write_dr0(void *val) 608 { 609 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); 610 } 611 612 static inline void write_dr1(void *val) 613 { 614 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); 615 } 616 617 static inline void write_dr2(void *val) 618 { 619 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); 620 } 621 622 static inline void write_dr3(void *val) 623 { 624 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); 625 } 626 627 static inline void write_dr6(ulong val) 628 { 629 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 630 } 631 632 static inline ulong read_dr6(void) 633 { 634 ulong val; 635 asm volatile ("mov %%dr6, %0" : "=r"(val)); 636 return val; 637 } 638 639 static inline void write_dr7(ulong val) 640 { 641 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 642 } 643 644 static inline ulong read_dr7(void) 645 { 646 ulong val; 647 asm volatile ("mov %%dr7, %0" : "=r"(val)); 648 return val; 649 } 650 651 static inline void pause(void) 652 { 653 asm volatile ("pause"); 654 } 655 656 static inline void cli(void) 657 { 658 asm volatile ("cli"); 659 } 660 661 static inline void sti(void) 662 { 663 asm volatile ("sti"); 664 } 665 666 static inline unsigned long long rdrand(void) 667 { 668 long long r; 669 670 asm volatile("rdrand %0\n\t" 671 "jc 1f\n\t" 672 "mov $0, %0\n\t" 673 "1:\n\t" : "=r" (r)); 674 return r; 675 } 676 677 static inline unsigned long long rdtsc(void) 678 { 679 long long r; 680 681 #ifdef __x86_64__ 682 unsigned a, d; 683 684 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 685 r = a | ((long long)d << 32); 686 #else 687 asm volatile ("rdtsc" : "=A"(r)); 688 #endif 689 return r; 690 } 691 692 /* 693 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 694 * executed immediately before rdtsc ensures that rdtsc will be 695 * executed only after all previous instructions have executed and all 696 * previous loads and stores are globally visible. In addition, the 697 * lfence immediately after rdtsc ensures that rdtsc will be executed 698 * prior to the execution of any subsequent instruction. 699 */ 700 static inline unsigned long long fenced_rdtsc(void) 701 { 702 unsigned long long tsc; 703 704 #ifdef __x86_64__ 705 unsigned int eax, edx; 706 707 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 708 tsc = eax | ((unsigned long long)edx << 32); 709 #else 710 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 711 #endif 712 return tsc; 713 } 714 715 static inline unsigned long long rdtscp(u32 *aux) 716 { 717 long long r; 718 719 #ifdef __x86_64__ 720 unsigned a, d; 721 722 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 723 r = a | ((long long)d << 32); 724 #else 725 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 726 #endif 727 return r; 728 } 729 730 static inline void wrtsc(u64 tsc) 731 { 732 wrmsr(MSR_IA32_TSC, tsc); 733 } 734 735 static inline void irq_disable(void) 736 { 737 asm volatile("cli"); 738 } 739 740 /* Note that irq_enable() does not ensure an interrupt shadow due 741 * to the vagaries of compiler optimizations. If you need the 742 * shadow, use a single asm with "sti" and the instruction after it. 743 */ 744 static inline void irq_enable(void) 745 { 746 asm volatile("sti"); 747 } 748 749 static inline void invlpg(volatile void *va) 750 { 751 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 752 } 753 754 static inline void safe_halt(void) 755 { 756 asm volatile("sti; hlt"); 757 } 758 759 static inline u32 read_pkru(void) 760 { 761 unsigned int eax, edx; 762 unsigned int ecx = 0; 763 unsigned int pkru; 764 765 asm volatile(".byte 0x0f,0x01,0xee\n\t" 766 : "=a" (eax), "=d" (edx) 767 : "c" (ecx)); 768 pkru = eax; 769 return pkru; 770 } 771 772 static inline void write_pkru(u32 pkru) 773 { 774 unsigned int eax = pkru; 775 unsigned int ecx = 0; 776 unsigned int edx = 0; 777 778 asm volatile(".byte 0x0f,0x01,0xef\n\t" 779 : : "a" (eax), "c" (ecx), "d" (edx)); 780 } 781 782 static inline bool is_canonical(u64 addr) 783 { 784 int va_width = (raw_cpuid(0x80000008, 0).a & 0xff00) >> 8; 785 int shift_amt = 64 - va_width; 786 787 return (s64)(addr << shift_amt) >> shift_amt == addr; 788 } 789 790 static inline void clear_bit(int bit, u8 *addr) 791 { 792 __asm__ __volatile__("btr %1, %0" 793 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 794 } 795 796 static inline void set_bit(int bit, u8 *addr) 797 { 798 __asm__ __volatile__("bts %1, %0" 799 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 800 } 801 802 static inline void flush_tlb(void) 803 { 804 ulong cr4; 805 806 cr4 = read_cr4(); 807 write_cr4(cr4 ^ X86_CR4_PGE); 808 write_cr4(cr4); 809 } 810 811 static inline void generate_non_canonical_gp(void) 812 { 813 *(volatile u64 *)NONCANONICAL = 0; 814 } 815 816 static inline void generate_ud(void) 817 { 818 asm volatile ("ud2"); 819 } 820 821 static inline void generate_de(void) 822 { 823 asm volatile ( 824 "xor %%eax, %%eax\n\t" 825 "xor %%ebx, %%ebx\n\t" 826 "xor %%edx, %%edx\n\t" 827 "idiv %%ebx\n\t" 828 ::: "eax", "ebx", "edx"); 829 } 830 831 static inline void generate_bp(void) 832 { 833 asm volatile ("int3"); 834 } 835 836 static inline void generate_single_step_db(void) 837 { 838 write_rflags(read_rflags() | X86_EFLAGS_TF); 839 asm volatile("nop"); 840 } 841 842 static inline uint64_t generate_usermode_ac(void) 843 { 844 /* 845 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 846 * Disclaimer: It is assumed that the stack pointer is aligned 847 * on a 16-byte boundary as x86_64 stacks should be. 848 */ 849 asm volatile("movq $0, -0x4(%rsp)"); 850 851 return 0; 852 } 853 854 /* 855 * Switch from 64-bit to 32-bit mode and generate #OF via INTO. Note, if RIP 856 * or RSP holds a 64-bit value, this helper will NOT generate #OF. 857 */ 858 static inline void generate_of(void) 859 { 860 struct far_pointer32 fp = { 861 .offset = (uintptr_t)&&into, 862 .selector = KERNEL_CS32, 863 }; 864 uintptr_t rsp; 865 866 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 867 868 if (fp.offset != (uintptr_t)&&into) { 869 printf("Code address too high.\n"); 870 return; 871 } 872 if ((u32)rsp != rsp) { 873 printf("Stack address too high.\n"); 874 return; 875 } 876 877 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 878 return; 879 into: 880 asm volatile (".code32;" 881 "movl $0x7fffffff, %eax;" 882 "addl %eax, %eax;" 883 "into;" 884 "lret;" 885 ".code64"); 886 __builtin_unreachable(); 887 } 888 889 static inline void fnop(void) 890 { 891 asm volatile("fnop"); 892 } 893 894 /* If CR0.TS is set in L2, #NM is generated. */ 895 static inline void generate_cr0_ts_nm(void) 896 { 897 write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS); 898 fnop(); 899 } 900 901 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */ 902 static inline void generate_cr0_em_nm(void) 903 { 904 write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM); 905 fnop(); 906 } 907 908 #endif 909