header guards: clean up some stragglers

Some headers had been missed during the initial header guard
standardization.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Laurent Vivier <l

header guards: clean up some stragglers

Some headers had been missed during the initial header guard
standardization.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210610135937.94375-2-cohuck@redhat.com>

show more ...

Merge branch 'arm/queue' into 'master'

arm/arm64: target-efi prep

This series mostly prepares kvm-unit-tests/arm for targeting EFI
platforms. The actually EFI support will come in another series,
b

Merge branch 'arm/queue' into 'master'

arm/arm64: target-efi prep

This series mostly prepares kvm-unit-tests/arm for targeting EFI
platforms. The actually EFI support will come in another series,
but these patches are good for removing assumptions from our memory
maps and about our PSCI conduit, even if we never merge EFI support.

See merge request kvm-unit-tests/kvm-unit-tests!8

show more ...

arm/arm64: mmu: Stop mapping an assumed IO region

By providing a proper ioremap function, we can just rely on devices
calling it for each region they need (as they already do) instead of
mapping a b

arm/arm64: mmu: Stop mapping an assumed IO region

By providing a proper ioremap function, we can just rely on devices
calling it for each region they need (as they already do) instead of
mapping a big assumed I/O range. We don't require the MMU to be
enabled at the time of the ioremap. In that case, we add the mapping
to the identity map anyway. This allows us to call setup_vm after
io_init. Why don't we just call setup_vm before io_init, I hear you
ask? Well, that's because tests like sieve want to start with the MMU
off, later call setup_vm, and all the while have working I/O. Some
unit tests are just really demanding...

While at it, ensure we map the I/O regions with XN (execute never),
as suggested by Alexandru Elisei.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

Merge branch 'arm/queue' of https://github.com/rhdrjones/kvm-unit-tests into HEAD

lib: arm: Implement flush_tlb_all

flush_tlb_all performs a TLBIALL, which invalidates the entire TLB and
affects only the executing PE; translation table walks are now Inner
Shareable, so execute a

lib: arm: Implement flush_tlb_all

flush_tlb_all performs a TLBIALL, which invalidates the entire TLB and
affects only the executing PE; translation table walks are now Inner
Shareable, so execute a TLBIALLIS (invalidate TLB Inner Shareable) instead.
TLBIALLIS is the equivalent of TLBIALL [1] when the multiprocessing
extensions are implemented, which are mandated by the virtualization
extensions.

Also add the necessary barriers to tlb_flush_all and a comment to
flush_dcache_addr stating what instruction is uses (unsurprisingly, it's
DCCIMVAC, which does a dcache clean and invalidate by VA to PoC).

[1] ARM DDI 0406C.d, section B3.10.6

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

lib: arm: Add proper data synchronization barriers for TLBIs

We need to issue a DSB before doing TLB invalidation to make sure that the
table walker sees the new VA mapping after the TLBI finishes.

lib: arm: Add proper data synchronization barriers for TLBIs

We need to issue a DSB before doing TLB invalidation to make sure that the
table walker sees the new VA mapping after the TLBI finishes. For
flush_tlb_page, we do a DSB ISHST (synchronization barrier for writes in
the Inner Shareable domain) because translation table walks are now
coherent for arm. For local_flush_tlb_all, we only need to affect the
Non-shareable domain, and we do a DSB NSHST. We need a synchronization
barrier here, and not a memory ordering barrier, because a table walk is
not a memory operation and therefore not affected by the DMB.

For the same reasons, we downgrade the full system DSB after the TLBI to a
DSB ISH (synchronization barrier for reads and writes in the Inner
Shareable domain), and, respectively, DSB NSH (in the Non-shareable
domain).

With these two changes, our TLB maintenance functions now match what Linux
does in __flush_tlb_kernel_page, and, respectively, in local_flush_tlb_all.

A similar change was implemented in Linux commit 62cbbc42e001 ("ARM: tlb:
reduce scope of barrier domains for TLB invalidation").

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

lib: arm/arm64: Remove unnecessary dcache maintenance operations

On ARMv7 with multiprocessing extensions (which are mandated by the
virtualization extensions [1]), and on ARMv8, translation table w

lib: arm/arm64: Remove unnecessary dcache maintenance operations

On ARMv7 with multiprocessing extensions (which are mandated by the
virtualization extensions [1]), and on ARMv8, translation table walks are
coherent [2, 3], which means that no dcache maintenance operations are
required when changing the tables. Remove the maintenance operations so
that we do only the minimum required to ensure correctness.

Translation table walks are coherent if the memory where the tables
themselves reside have the same shareability and cacheability attributes
as the translation table walks. For ARMv8, this is already the case, and
it is only a matter of removing the cache operations.

However, for ARMv7, translation table walks were being configured as
Non-shareable (TTBCR.SH0 = 0b00) and Non-cacheable
(TTBCR.{I,O}RGN0 = 0b00). Fix that by marking them as Inner Shareable,
Normal memory, Inner and Outer Write-Back Write-Allocate Cacheable.

Because translation table walks are now coherent on arm, replace the
TLBIMVAA operation with TLBIMVAAIS in flush_tlb_page, which acts on the
Inner Shareable domain instead of being private to the PE.

The functions that update the translation table are called when the MMU
is off, or to modify permissions, in the case of the cache test, so
break-before-make is not necessary.

[1] ARM DDI 0406C.d, section B1.7
[2] ARM DDI 0406C.d, section B3.3.1
[3] ARM DDI 0487E.a, section D13.2.72
[4] ARM DDI 0487E.a, section K11.5.3

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm/arm64: flush page table cache when installing entries

This fixes the use of non-identity mapped page table entries for
arm32 and AArch32 unit tests.

Signed-off-by: Andrew Jones <drjones@redhat.

arm/arm64: flush page table cache when installing entries

This fixes the use of non-identity mapped page table entries for
arm32 and AArch32 unit tests.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>

show more ...

arm: make pgtable.h private to mmu.c

The pgd/pmd/pud definitions are not needed outside the architecture-
dependent MMU functions. In fact, it probably would be simpler to
have completely different

arm: make pgtable.h private to mmu.c

The pgd/pmd/pud definitions are not needed outside the architecture-
dependent MMU functions. In fact, it probably would be simpler to
have completely different files for 32-bit and 64-bit ARM. However,
as a first and possibly less controversial step, hide them inside
that file.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

lib/arm: add flush_tlb_page mmu function

This introduces a new flush_tlb_page function which does exactly what
you expect. It's going to be useful for the future TLB torture test.

Signed-off-by: Al

lib/arm: add flush_tlb_page mmu function

This introduces a new flush_tlb_page function which does exactly what
you expect. It's going to be useful for the future TLB torture test.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-Id: <1446769483-21586-13-git-send-email-drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm64: enable mmu

Implement asm_mmu_enable and flush_tlb_all, and then make a final
change to mmu.c in order to link it into arm64. The final change
is to map the code read-only. This is necessary b

arm64: enable mmu

Implement asm_mmu_enable and flush_tlb_all, and then make a final
change to mmu.c in order to link it into arm64. The final change
is to map the code read-only. This is necessary because armv8
forces all writable code shared between EL1 and EL0 to be PXN.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: prepare mmu code for arm64

* don't assume 1G PGDIR_SIZE or L1_CACHE_BYTES pgd alignment
* use page level descriptors for non-I/O memory
* apply new pgd/pud/pmd/pte methods
* split mmu.h to shar

arm: prepare mmu code for arm64

* don't assume 1G PGDIR_SIZE or L1_CACHE_BYTES pgd alignment
* use page level descriptors for non-I/O memory
* apply new pgd/pud/pmd/pte methods
* split mmu.h to share function declarations
* use more generic flag names in mmu.c

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: import more linux page table api

To use page level descriptors we need some pgd/pud/pmd/pte
methods, and a few more flags defined.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-b

arm: import more linux page table api

To use page level descriptors we need some pgd/pud/pmd/pte
methods, and a few more flags defined.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: get PHYS_MASK from pgtable-hwdef.h

This allows it to be different for arm64, even with setup.h
shared.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@r

arm: get PHYS_MASK from pgtable-hwdef.h

This allows it to be different for arm64, even with setup.h
shared.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: use absolute headers

Files in lib/arm including "asm/someheader.h" will get
lib/arm/asm/someheader.h, not lib/asm/someheader.h. So we
need to use <> instead of "" in order to prepare for header

arm: use absolute headers

Files in lib/arm including "asm/someheader.h" will get
lib/arm/asm/someheader.h, not lib/asm/someheader.h. So we
need to use <> instead of "" in order to prepare for headers
of the same name, but for a different arch. We change all
'#include's of all arm files, as consistency looks better.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: turn on the MMU

We should probably always run with the mmu on, so let's
enable it from setup with an identity map.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini

arm: turn on the MMU

We should probably always run with the mmu on, so let's
enable it from setup with an identity map.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm: fix crash on cubietruck

Cubietruck seems to be more sensitive than my Midway when
attempting to use [ldr|str]ex instructions without caches
enabled (mmu disabled). Fix this by making the spinlo

arm: fix crash on cubietruck

Cubietruck seems to be more sensitive than my Midway when
attempting to use [ldr|str]ex instructions without caches
enabled (mmu disabled). Fix this by making the spinlock
implementation (currently the only user of *ex instructions)
conditional on the mmu being enabled.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...