1 #ifndef _ASMARM_MMU_H_
2 #define _ASMARM_MMU_H_
3 /*
4 * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com>
5 *
6 * This work is licensed under the terms of the GNU LGPL, version 2.
7 */
8 #include <asm/barrier.h>
9
10 #define PTE_USER L_PTE_USER
11 #define PTE_UXN L_PTE_XN
12 #define PTE_PXN L_PTE_PXN
13 #define PTE_RDONLY PTE_AP2
14 #define PTE_SHARED L_PTE_SHARED
15 #define PTE_AF PTE_EXT_AF
16 #define PTE_WBWA L_PTE_MT_WRITEALLOC
17 #define PTE_UNCACHED L_PTE_MT_UNCACHED
18
19 /* See B3.18.7 TLB maintenance operations */
20
local_flush_tlb_all(void)21 static inline void local_flush_tlb_all(void)
22 {
23 dsb(nshst);
24 /* TLBIALL */
25 asm volatile("mcr p15, 0, %0, c8, c7, 0" :: "r" (0));
26 dsb(nsh);
27 isb();
28 }
29
flush_tlb_all(void)30 static inline void flush_tlb_all(void)
31 {
32 dsb(ishst);
33 /* TLBIALLIS */
34 asm volatile("mcr p15, 0, %0, c8, c3, 0" :: "r" (0));
35 dsb(ish);
36 isb();
37 }
38
flush_tlb_page(unsigned long vaddr)39 static inline void flush_tlb_page(unsigned long vaddr)
40 {
41 dsb(ishst);
42 /* TLBIMVAAIS */
43 asm volatile("mcr p15, 0, %0, c8, c3, 3" :: "r" (vaddr));
44 dsb(ish);
45 isb();
46 }
47
flush_dcache_addr(unsigned long vaddr)48 static inline void flush_dcache_addr(unsigned long vaddr)
49 {
50 /* DCCIMVAC */
51 asm volatile("mcr p15, 0, %0, c7, c14, 1" :: "r" (vaddr));
52 }
53
54 #include <asm/mmu-api.h>
55
56 #endif /* _ASMARM_MMU_H_ */
57