1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial-mm.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/iommu.h" 36 #include "hw/riscv/riscv-iommu-bits.h" 37 #include "hw/riscv/virt.h" 38 #include "hw/riscv/boot.h" 39 #include "hw/riscv/numa.h" 40 #include "kvm/kvm_riscv.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/intc/riscv_aclint.h" 43 #include "hw/intc/riscv_aplic.h" 44 #include "hw/intc/sifive_plic.h" 45 #include "hw/misc/sifive_test.h" 46 #include "hw/platform-bus.h" 47 #include "chardev/char.h" 48 #include "system/device_tree.h" 49 #include "system/system.h" 50 #include "system/tcg.h" 51 #include "system/kvm.h" 52 #include "system/tpm.h" 53 #include "system/qtest.h" 54 #include "hw/pci/pci.h" 55 #include "hw/pci-host/gpex.h" 56 #include "hw/display/ramfb.h" 57 #include "hw/acpi/aml-build.h" 58 #include "qapi/qapi-visit-common.h" 59 #include "hw/virtio/virtio-iommu.h" 60 61 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 62 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) 63 { 64 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 65 66 return riscv_is_kvm_aia_aplic_imsic(msimode); 67 } 68 69 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) 70 { 71 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 72 73 return riscv_use_emulated_aplic(msimode); 74 } 75 76 static bool virt_aclint_allowed(void) 77 { 78 return tcg_enabled() || qtest_enabled(); 79 } 80 81 static const MemMapEntry virt_memmap[] = { 82 [VIRT_DEBUG] = { 0x0, 0x100 }, 83 [VIRT_MROM] = { 0x1000, 0xf000 }, 84 [VIRT_TEST] = { 0x100000, 0x1000 }, 85 [VIRT_RTC] = { 0x101000, 0x1000 }, 86 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 87 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 88 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 89 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, 90 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 91 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 92 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 93 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 94 [VIRT_UART0] = { 0x10000000, 0x100 }, 95 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 96 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 97 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 98 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 99 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 100 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 101 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 102 [VIRT_DRAM] = { 0x80000000, 0x0 }, 103 }; 104 105 /* PCIe high mmio is fixed for RV32 */ 106 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 107 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 108 109 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 110 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 111 112 static MemMapEntry virt_high_pcie_memmap; 113 114 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 115 116 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 117 const char *name, 118 const char *alias_prop_name) 119 { 120 /* 121 * Create a single flash device. We use the same parameters as 122 * the flash devices on the ARM virt board. 123 */ 124 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 125 126 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 127 qdev_prop_set_uint8(dev, "width", 4); 128 qdev_prop_set_uint8(dev, "device-width", 2); 129 qdev_prop_set_bit(dev, "big-endian", false); 130 qdev_prop_set_uint16(dev, "id0", 0x89); 131 qdev_prop_set_uint16(dev, "id1", 0x18); 132 qdev_prop_set_uint16(dev, "id2", 0x00); 133 qdev_prop_set_uint16(dev, "id3", 0x00); 134 qdev_prop_set_string(dev, "name", name); 135 136 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 137 object_property_add_alias(OBJECT(s), alias_prop_name, 138 OBJECT(dev), "drive"); 139 140 return PFLASH_CFI01(dev); 141 } 142 143 static void virt_flash_create(RISCVVirtState *s) 144 { 145 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 146 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 147 } 148 149 static void virt_flash_map1(PFlashCFI01 *flash, 150 hwaddr base, hwaddr size, 151 MemoryRegion *sysmem) 152 { 153 DeviceState *dev = DEVICE(flash); 154 155 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 156 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 157 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 158 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 159 160 memory_region_add_subregion(sysmem, base, 161 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 162 0)); 163 } 164 165 static void virt_flash_map(RISCVVirtState *s, 166 MemoryRegion *sysmem) 167 { 168 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 169 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 170 171 virt_flash_map1(s->flash[0], flashbase, flashsize, 172 sysmem); 173 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 174 sysmem); 175 } 176 177 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 178 uint32_t irqchip_phandle) 179 { 180 int pin, dev; 181 uint32_t irq_map_stride = 0; 182 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 183 FDT_MAX_INT_MAP_WIDTH] = {}; 184 uint32_t *irq_map = full_irq_map; 185 186 /* This code creates a standard swizzle of interrupts such that 187 * each device's first interrupt is based on it's PCI_SLOT number. 188 * (See pci_swizzle_map_irq_fn()) 189 * 190 * We only need one entry per interrupt in the table (not one per 191 * possible slot) seeing the interrupt-map-mask will allow the table 192 * to wrap to any number of devices. 193 */ 194 for (dev = 0; dev < PCI_NUM_PINS; dev++) { 195 int devfn = dev * 0x8; 196 197 for (pin = 0; pin < PCI_NUM_PINS; pin++) { 198 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 199 int i = 0; 200 201 /* Fill PCI address cells */ 202 irq_map[i] = cpu_to_be32(devfn << 8); 203 i += FDT_PCI_ADDR_CELLS; 204 205 /* Fill PCI Interrupt cells */ 206 irq_map[i] = cpu_to_be32(pin + 1); 207 i += FDT_PCI_INT_CELLS; 208 209 /* Fill interrupt controller phandle and cells */ 210 irq_map[i++] = cpu_to_be32(irqchip_phandle); 211 irq_map[i++] = cpu_to_be32(irq_nr); 212 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 213 irq_map[i++] = cpu_to_be32(0x4); 214 } 215 216 if (!irq_map_stride) { 217 irq_map_stride = i; 218 } 219 irq_map += irq_map_stride; 220 } 221 } 222 223 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 224 PCI_NUM_PINS * PCI_NUM_PINS * 225 irq_map_stride * sizeof(uint32_t)); 226 227 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 228 0x1800, 0, 0, 0x7); 229 } 230 231 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 232 char *clust_name, uint32_t *phandle, 233 uint32_t *intc_phandles) 234 { 235 int cpu; 236 uint32_t cpu_phandle; 237 MachineState *ms = MACHINE(s); 238 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 239 uint8_t satp_mode_max; 240 241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 242 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 243 g_autofree char *cpu_name = NULL; 244 g_autofree char *core_name = NULL; 245 g_autofree char *intc_name = NULL; 246 g_autofree char *sv_name = NULL; 247 248 cpu_phandle = (*phandle)++; 249 250 cpu_name = g_strdup_printf("/cpus/cpu@%d", 251 s->soc[socket].hartid_base + cpu); 252 qemu_fdt_add_subnode(ms->fdt, cpu_name); 253 254 if (cpu_ptr->cfg.satp_mode.supported != 0) { 255 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 256 sv_name = g_strdup_printf("riscv,%s", 257 satp_mode_str(satp_mode_max, is_32_bit)); 258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 259 } 260 261 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 262 263 if (cpu_ptr->cfg.ext_zicbom) { 264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 265 cpu_ptr->cfg.cbom_blocksize); 266 } 267 268 if (cpu_ptr->cfg.ext_zicboz) { 269 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 270 cpu_ptr->cfg.cboz_blocksize); 271 } 272 273 if (cpu_ptr->cfg.ext_zicbop) { 274 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 275 cpu_ptr->cfg.cbop_blocksize); 276 } 277 278 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 280 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 281 s->soc[socket].hartid_base + cpu); 282 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 283 riscv_socket_fdt_write_id(ms, cpu_name, socket); 284 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 285 286 intc_phandles[cpu] = (*phandle)++; 287 288 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 289 qemu_fdt_add_subnode(ms->fdt, intc_name); 290 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 291 intc_phandles[cpu]); 292 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 293 "riscv,cpu-intc"); 294 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 295 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 296 297 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 298 qemu_fdt_add_subnode(ms->fdt, core_name); 299 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 300 } 301 } 302 303 static void create_fdt_socket_memory(RISCVVirtState *s, 304 const MemMapEntry *memmap, int socket) 305 { 306 g_autofree char *mem_name = NULL; 307 uint64_t addr, size; 308 MachineState *ms = MACHINE(s); 309 310 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 311 size = riscv_socket_mem_size(ms, socket); 312 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 313 qemu_fdt_add_subnode(ms->fdt, mem_name); 314 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 315 addr >> 32, addr, size >> 32, size); 316 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 317 riscv_socket_fdt_write_id(ms, mem_name, socket); 318 } 319 320 static void create_fdt_socket_clint(RISCVVirtState *s, 321 const MemMapEntry *memmap, int socket, 322 uint32_t *intc_phandles) 323 { 324 int cpu; 325 g_autofree char *clint_name = NULL; 326 g_autofree uint32_t *clint_cells = NULL; 327 unsigned long clint_addr; 328 MachineState *ms = MACHINE(s); 329 static const char * const clint_compat[2] = { 330 "sifive,clint0", "riscv,clint0" 331 }; 332 333 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 334 335 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 336 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 337 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 338 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 339 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 340 } 341 342 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 343 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 344 qemu_fdt_add_subnode(ms->fdt, clint_name); 345 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 346 (char **)&clint_compat, 347 ARRAY_SIZE(clint_compat)); 348 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 349 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 350 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 351 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 352 riscv_socket_fdt_write_id(ms, clint_name, socket); 353 } 354 355 static void create_fdt_socket_aclint(RISCVVirtState *s, 356 const MemMapEntry *memmap, int socket, 357 uint32_t *intc_phandles) 358 { 359 int cpu; 360 char *name; 361 unsigned long addr, size; 362 uint32_t aclint_cells_size; 363 g_autofree uint32_t *aclint_mswi_cells = NULL; 364 g_autofree uint32_t *aclint_sswi_cells = NULL; 365 g_autofree uint32_t *aclint_mtimer_cells = NULL; 366 MachineState *ms = MACHINE(s); 367 368 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 369 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 370 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 371 372 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 373 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 374 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 375 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 376 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 377 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 378 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 379 } 380 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 381 382 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 383 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 384 name = g_strdup_printf("/soc/mswi@%lx", addr); 385 qemu_fdt_add_subnode(ms->fdt, name); 386 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 387 "riscv,aclint-mswi"); 388 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 389 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 390 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 391 aclint_mswi_cells, aclint_cells_size); 392 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 393 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 394 riscv_socket_fdt_write_id(ms, name, socket); 395 g_free(name); 396 } 397 398 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 399 addr = memmap[VIRT_CLINT].base + 400 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 401 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 402 } else { 403 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 404 (memmap[VIRT_CLINT].size * socket); 405 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 406 } 407 name = g_strdup_printf("/soc/mtimer@%lx", addr); 408 qemu_fdt_add_subnode(ms->fdt, name); 409 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 410 "riscv,aclint-mtimer"); 411 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 412 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 413 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 414 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 415 0x0, RISCV_ACLINT_DEFAULT_MTIME); 416 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 417 aclint_mtimer_cells, aclint_cells_size); 418 riscv_socket_fdt_write_id(ms, name, socket); 419 g_free(name); 420 421 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 422 addr = memmap[VIRT_ACLINT_SSWI].base + 423 (memmap[VIRT_ACLINT_SSWI].size * socket); 424 name = g_strdup_printf("/soc/sswi@%lx", addr); 425 qemu_fdt_add_subnode(ms->fdt, name); 426 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 427 "riscv,aclint-sswi"); 428 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 429 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 430 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 431 aclint_sswi_cells, aclint_cells_size); 432 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 433 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 434 riscv_socket_fdt_write_id(ms, name, socket); 435 g_free(name); 436 } 437 } 438 439 static void create_fdt_socket_plic(RISCVVirtState *s, 440 const MemMapEntry *memmap, int socket, 441 uint32_t *phandle, uint32_t *intc_phandles, 442 uint32_t *plic_phandles) 443 { 444 int cpu; 445 g_autofree char *plic_name = NULL; 446 g_autofree uint32_t *plic_cells; 447 unsigned long plic_addr; 448 MachineState *ms = MACHINE(s); 449 static const char * const plic_compat[2] = { 450 "sifive,plic-1.0.0", "riscv,plic0" 451 }; 452 453 plic_phandles[socket] = (*phandle)++; 454 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 455 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 456 qemu_fdt_add_subnode(ms->fdt, plic_name); 457 qemu_fdt_setprop_cell(ms->fdt, plic_name, 458 "#interrupt-cells", FDT_PLIC_INT_CELLS); 459 qemu_fdt_setprop_cell(ms->fdt, plic_name, 460 "#address-cells", FDT_PLIC_ADDR_CELLS); 461 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 462 (char **)&plic_compat, 463 ARRAY_SIZE(plic_compat)); 464 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 465 466 if (kvm_enabled()) { 467 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 468 469 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 470 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 471 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 472 } 473 474 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 475 plic_cells, 476 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 477 } else { 478 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 479 480 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 481 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 482 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 483 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 484 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 485 } 486 487 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 488 plic_cells, 489 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 490 } 491 492 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 493 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 494 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 495 VIRT_IRQCHIP_NUM_SOURCES - 1); 496 riscv_socket_fdt_write_id(ms, plic_name, socket); 497 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 498 plic_phandles[socket]); 499 500 if (!socket) { 501 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 502 memmap[VIRT_PLATFORM_BUS].base, 503 memmap[VIRT_PLATFORM_BUS].size, 504 VIRT_PLATFORM_BUS_IRQ); 505 } 506 } 507 508 uint32_t imsic_num_bits(uint32_t count) 509 { 510 uint32_t ret = 0; 511 512 while (BIT(ret) < count) { 513 ret++; 514 } 515 516 return ret; 517 } 518 519 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 520 uint32_t *intc_phandles, uint32_t msi_phandle, 521 bool m_mode, uint32_t imsic_guest_bits) 522 { 523 int cpu, socket; 524 g_autofree char *imsic_name = NULL; 525 MachineState *ms = MACHINE(s); 526 int socket_count = riscv_socket_count(ms); 527 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 528 g_autofree uint32_t *imsic_cells = NULL; 529 g_autofree uint32_t *imsic_regs = NULL; 530 static const char * const imsic_compat[2] = { 531 "qemu,imsics", "riscv,imsics" 532 }; 533 534 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 535 imsic_regs = g_new0(uint32_t, socket_count * 4); 536 537 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 538 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 539 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 540 } 541 542 imsic_max_hart_per_socket = 0; 543 for (socket = 0; socket < socket_count; socket++) { 544 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 545 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 546 s->soc[socket].num_harts; 547 imsic_regs[socket * 4 + 0] = 0; 548 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 549 imsic_regs[socket * 4 + 2] = 0; 550 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 551 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 552 imsic_max_hart_per_socket = s->soc[socket].num_harts; 553 } 554 } 555 556 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 557 (unsigned long)base_addr); 558 qemu_fdt_add_subnode(ms->fdt, imsic_name); 559 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 560 (char **)&imsic_compat, 561 ARRAY_SIZE(imsic_compat)); 562 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 564 FDT_IMSIC_INT_CELLS); 565 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 566 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 567 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 568 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 569 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 570 socket_count * sizeof(uint32_t) * 4); 571 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 572 VIRT_IRQCHIP_NUM_MSIS); 573 574 if (imsic_guest_bits) { 575 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 576 imsic_guest_bits); 577 } 578 579 if (socket_count > 1) { 580 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 581 imsic_num_bits(imsic_max_hart_per_socket)); 582 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 583 imsic_num_bits(socket_count)); 584 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 585 IMSIC_MMIO_GROUP_MIN_SHIFT); 586 } 587 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 588 } 589 590 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 591 uint32_t *phandle, uint32_t *intc_phandles, 592 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 593 { 594 *msi_m_phandle = (*phandle)++; 595 *msi_s_phandle = (*phandle)++; 596 597 if (!kvm_enabled()) { 598 /* M-level IMSIC node */ 599 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 600 *msi_m_phandle, true, 0); 601 } 602 603 /* S-level IMSIC node */ 604 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 605 *msi_s_phandle, false, 606 imsic_num_bits(s->aia_guests + 1)); 607 608 } 609 610 /* Caller must free string after use */ 611 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 612 { 613 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 614 } 615 616 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 617 unsigned long aplic_addr, uint32_t aplic_size, 618 uint32_t msi_phandle, 619 uint32_t *intc_phandles, 620 uint32_t aplic_phandle, 621 uint32_t aplic_child_phandle, 622 bool m_mode, int num_harts) 623 { 624 int cpu; 625 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 626 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 627 MachineState *ms = MACHINE(s); 628 static const char * const aplic_compat[2] = { 629 "qemu,aplic", "riscv,aplic" 630 }; 631 632 for (cpu = 0; cpu < num_harts; cpu++) { 633 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 634 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 635 } 636 637 qemu_fdt_add_subnode(ms->fdt, aplic_name); 638 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 639 (char **)&aplic_compat, 640 ARRAY_SIZE(aplic_compat)); 641 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 642 FDT_APLIC_ADDR_CELLS); 643 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 644 "#interrupt-cells", FDT_APLIC_INT_CELLS); 645 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 646 647 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 648 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 649 aplic_cells, num_harts * sizeof(uint32_t) * 2); 650 } else { 651 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 652 } 653 654 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 655 0x0, aplic_addr, 0x0, aplic_size); 656 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 657 VIRT_IRQCHIP_NUM_SOURCES); 658 659 if (aplic_child_phandle) { 660 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 661 aplic_child_phandle); 662 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 663 aplic_child_phandle, 0x1, 664 VIRT_IRQCHIP_NUM_SOURCES); 665 /* 666 * DEPRECATED_9.1: Compat property kept temporarily 667 * to allow old firmwares to work with AIA. Do *not* 668 * use 'riscv,delegate' in new code: use 669 * 'riscv,delegation' instead. 670 */ 671 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 672 aplic_child_phandle, 0x1, 673 VIRT_IRQCHIP_NUM_SOURCES); 674 } 675 676 riscv_socket_fdt_write_id(ms, aplic_name, socket); 677 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 678 } 679 680 static void create_fdt_socket_aplic(RISCVVirtState *s, 681 const MemMapEntry *memmap, int socket, 682 uint32_t msi_m_phandle, 683 uint32_t msi_s_phandle, 684 uint32_t *phandle, 685 uint32_t *intc_phandles, 686 uint32_t *aplic_phandles, 687 int num_harts) 688 { 689 unsigned long aplic_addr; 690 MachineState *ms = MACHINE(s); 691 uint32_t aplic_m_phandle, aplic_s_phandle; 692 693 aplic_m_phandle = (*phandle)++; 694 aplic_s_phandle = (*phandle)++; 695 696 if (!kvm_enabled()) { 697 /* M-level APLIC node */ 698 aplic_addr = memmap[VIRT_APLIC_M].base + 699 (memmap[VIRT_APLIC_M].size * socket); 700 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 701 msi_m_phandle, intc_phandles, 702 aplic_m_phandle, aplic_s_phandle, 703 true, num_harts); 704 } 705 706 /* S-level APLIC node */ 707 aplic_addr = memmap[VIRT_APLIC_S].base + 708 (memmap[VIRT_APLIC_S].size * socket); 709 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 710 msi_s_phandle, intc_phandles, 711 aplic_s_phandle, 0, 712 false, num_harts); 713 714 if (!socket) { 715 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 716 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 717 memmap[VIRT_PLATFORM_BUS].base, 718 memmap[VIRT_PLATFORM_BUS].size, 719 VIRT_PLATFORM_BUS_IRQ); 720 } 721 722 aplic_phandles[socket] = aplic_s_phandle; 723 } 724 725 static void create_fdt_pmu(RISCVVirtState *s) 726 { 727 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 728 MachineState *ms = MACHINE(s); 729 RISCVCPU hart = s->soc[0].harts[0]; 730 731 qemu_fdt_add_subnode(ms->fdt, pmu_name); 732 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 733 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 734 } 735 736 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 737 uint32_t *phandle, 738 uint32_t *irq_mmio_phandle, 739 uint32_t *irq_pcie_phandle, 740 uint32_t *irq_virtio_phandle, 741 uint32_t *msi_pcie_phandle) 742 { 743 int socket, phandle_pos; 744 MachineState *ms = MACHINE(s); 745 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 746 uint32_t xplic_phandles[MAX_NODES]; 747 g_autofree uint32_t *intc_phandles = NULL; 748 int socket_count = riscv_socket_count(ms); 749 750 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 751 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 752 kvm_enabled() ? 753 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : 754 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 755 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 756 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 757 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 758 759 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 760 761 phandle_pos = ms->smp.cpus; 762 for (socket = (socket_count - 1); socket >= 0; socket--) { 763 g_autofree char *clust_name = NULL; 764 phandle_pos -= s->soc[socket].num_harts; 765 766 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 767 qemu_fdt_add_subnode(ms->fdt, clust_name); 768 769 create_fdt_socket_cpus(s, socket, clust_name, phandle, 770 &intc_phandles[phandle_pos]); 771 772 create_fdt_socket_memory(s, memmap, socket); 773 774 if (virt_aclint_allowed() && s->have_aclint) { 775 create_fdt_socket_aclint(s, memmap, socket, 776 &intc_phandles[phandle_pos]); 777 } else if (tcg_enabled()) { 778 create_fdt_socket_clint(s, memmap, socket, 779 &intc_phandles[phandle_pos]); 780 } 781 } 782 783 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 784 create_fdt_imsic(s, memmap, phandle, intc_phandles, 785 &msi_m_phandle, &msi_s_phandle); 786 *msi_pcie_phandle = msi_s_phandle; 787 } 788 789 /* 790 * With KVM AIA aplic-imsic, using an irqchip without split 791 * mode, we'll use only one APLIC instance. 792 */ 793 if (!virt_use_emulated_aplic(s->aia_type)) { 794 create_fdt_socket_aplic(s, memmap, 0, 795 msi_m_phandle, msi_s_phandle, phandle, 796 &intc_phandles[0], xplic_phandles, 797 ms->smp.cpus); 798 799 *irq_mmio_phandle = xplic_phandles[0]; 800 *irq_virtio_phandle = xplic_phandles[0]; 801 *irq_pcie_phandle = xplic_phandles[0]; 802 } else { 803 phandle_pos = ms->smp.cpus; 804 for (socket = (socket_count - 1); socket >= 0; socket--) { 805 phandle_pos -= s->soc[socket].num_harts; 806 807 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 808 create_fdt_socket_plic(s, memmap, socket, phandle, 809 &intc_phandles[phandle_pos], 810 xplic_phandles); 811 } else { 812 create_fdt_socket_aplic(s, memmap, socket, 813 msi_m_phandle, msi_s_phandle, phandle, 814 &intc_phandles[phandle_pos], 815 xplic_phandles, 816 s->soc[socket].num_harts); 817 } 818 } 819 820 for (socket = 0; socket < socket_count; socket++) { 821 if (socket == 0) { 822 *irq_mmio_phandle = xplic_phandles[socket]; 823 *irq_virtio_phandle = xplic_phandles[socket]; 824 *irq_pcie_phandle = xplic_phandles[socket]; 825 } 826 if (socket == 1) { 827 *irq_virtio_phandle = xplic_phandles[socket]; 828 *irq_pcie_phandle = xplic_phandles[socket]; 829 } 830 if (socket == 2) { 831 *irq_pcie_phandle = xplic_phandles[socket]; 832 } 833 } 834 } 835 836 riscv_socket_fdt_write_distance_matrix(ms); 837 } 838 839 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 840 uint32_t irq_virtio_phandle) 841 { 842 int i; 843 MachineState *ms = MACHINE(s); 844 845 for (i = 0; i < VIRTIO_COUNT; i++) { 846 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 847 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 848 849 qemu_fdt_add_subnode(ms->fdt, name); 850 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 851 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 852 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 853 0x0, memmap[VIRT_VIRTIO].size); 854 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 855 irq_virtio_phandle); 856 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 857 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 858 VIRTIO_IRQ + i); 859 } else { 860 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 861 VIRTIO_IRQ + i, 0x4); 862 } 863 } 864 } 865 866 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 867 uint32_t irq_pcie_phandle, 868 uint32_t msi_pcie_phandle, 869 uint32_t iommu_sys_phandle) 870 { 871 g_autofree char *name = NULL; 872 MachineState *ms = MACHINE(s); 873 874 name = g_strdup_printf("/soc/pci@%lx", 875 (long) memmap[VIRT_PCIE_ECAM].base); 876 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 877 FDT_PCI_ADDR_CELLS); 878 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 879 FDT_PCI_INT_CELLS); 880 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 881 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 882 "pci-host-ecam-generic"); 883 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 884 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 885 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 886 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 887 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 888 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 889 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 890 } 891 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 892 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 893 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 894 1, FDT_PCI_RANGE_IOPORT, 2, 0, 895 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 896 1, FDT_PCI_RANGE_MMIO, 897 2, memmap[VIRT_PCIE_MMIO].base, 898 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 899 1, FDT_PCI_RANGE_MMIO_64BIT, 900 2, virt_high_pcie_memmap.base, 901 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 902 903 if (virt_is_iommu_sys_enabled(s)) { 904 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", 905 0, iommu_sys_phandle, 0, 0, 0, 906 iommu_sys_phandle, 0, 0xffff); 907 } 908 909 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 910 } 911 912 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 913 uint32_t *phandle) 914 { 915 char *name; 916 uint32_t test_phandle; 917 MachineState *ms = MACHINE(s); 918 919 test_phandle = (*phandle)++; 920 name = g_strdup_printf("/soc/test@%lx", 921 (long)memmap[VIRT_TEST].base); 922 qemu_fdt_add_subnode(ms->fdt, name); 923 { 924 static const char * const compat[3] = { 925 "sifive,test1", "sifive,test0", "syscon" 926 }; 927 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 928 (char **)&compat, ARRAY_SIZE(compat)); 929 } 930 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 931 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 932 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 933 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 934 g_free(name); 935 936 name = g_strdup_printf("/reboot"); 937 qemu_fdt_add_subnode(ms->fdt, name); 938 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 939 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 940 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 941 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 942 g_free(name); 943 944 name = g_strdup_printf("/poweroff"); 945 qemu_fdt_add_subnode(ms->fdt, name); 946 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 947 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 948 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 949 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 950 g_free(name); 951 } 952 953 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 954 uint32_t irq_mmio_phandle) 955 { 956 g_autofree char *name = NULL; 957 MachineState *ms = MACHINE(s); 958 959 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 960 qemu_fdt_add_subnode(ms->fdt, name); 961 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 962 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 963 0x0, memmap[VIRT_UART0].base, 964 0x0, memmap[VIRT_UART0].size); 965 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 966 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 967 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 968 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 969 } else { 970 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 971 } 972 973 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 974 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); 975 } 976 977 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 978 uint32_t irq_mmio_phandle) 979 { 980 g_autofree char *name = NULL; 981 MachineState *ms = MACHINE(s); 982 983 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 984 qemu_fdt_add_subnode(ms->fdt, name); 985 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 986 "google,goldfish-rtc"); 987 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 988 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 989 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 990 irq_mmio_phandle); 991 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 992 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 993 } else { 994 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 995 } 996 } 997 998 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 999 { 1000 MachineState *ms = MACHINE(s); 1001 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 1002 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 1003 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 1004 1005 qemu_fdt_add_subnode(ms->fdt, name); 1006 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 1007 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 1008 2, flashbase, 2, flashsize, 1009 2, flashbase + flashsize, 2, flashsize); 1010 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 1011 } 1012 1013 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 1014 { 1015 MachineState *ms = MACHINE(s); 1016 hwaddr base = memmap[VIRT_FW_CFG].base; 1017 hwaddr size = memmap[VIRT_FW_CFG].size; 1018 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1019 1020 qemu_fdt_add_subnode(ms->fdt, nodename); 1021 qemu_fdt_setprop_string(ms->fdt, nodename, 1022 "compatible", "qemu,fw-cfg-mmio"); 1023 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1024 2, base, 2, size); 1025 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1026 } 1027 1028 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1029 { 1030 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1031 void *fdt = MACHINE(s)->fdt; 1032 uint32_t iommu_phandle; 1033 g_autofree char *iommu_node = NULL; 1034 g_autofree char *pci_node = NULL; 1035 1036 pci_node = g_strdup_printf("/soc/pci@%lx", 1037 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1038 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1039 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1040 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1041 1042 qemu_fdt_add_subnode(fdt, iommu_node); 1043 1044 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1045 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1046 1, bdf << 8, 1, 0, 1, 0, 1047 1, 0, 1, 0); 1048 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1049 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1050 1051 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1052 0, iommu_phandle, 0, bdf, 1053 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1054 } 1055 1056 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, 1057 uint32_t msi_phandle, 1058 uint32_t *iommu_sys_phandle) 1059 { 1060 const char comp[] = "riscv,iommu"; 1061 void *fdt = MACHINE(s)->fdt; 1062 uint32_t iommu_phandle; 1063 g_autofree char *iommu_node = NULL; 1064 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; 1065 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; 1066 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { 1067 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, 1068 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, 1069 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, 1070 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, 1071 }; 1072 1073 iommu_node = g_strdup_printf("/soc/iommu@%x", 1074 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); 1075 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1076 qemu_fdt_add_subnode(fdt, iommu_node); 1077 1078 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1079 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1080 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1081 1082 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1083 addr >> 32, addr, size >> 32, size); 1084 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); 1085 1086 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", 1087 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, 1088 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, 1089 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, 1090 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); 1091 1092 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); 1093 1094 *iommu_sys_phandle = iommu_phandle; 1095 } 1096 1097 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) 1098 { 1099 const char comp[] = "riscv,pci-iommu"; 1100 void *fdt = MACHINE(s)->fdt; 1101 uint32_t iommu_phandle; 1102 g_autofree char *iommu_node = NULL; 1103 g_autofree char *pci_node = NULL; 1104 1105 pci_node = g_strdup_printf("/soc/pci@%lx", 1106 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1107 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); 1108 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1109 qemu_fdt_add_subnode(fdt, iommu_node); 1110 1111 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1112 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1113 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1114 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1115 bdf << 8, 0, 0, 0, 0); 1116 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1117 0, iommu_phandle, 0, bdf, 1118 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1119 } 1120 1121 static void finalize_fdt(RISCVVirtState *s) 1122 { 1123 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1124 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1125 uint32_t iommu_sys_phandle = 1; 1126 1127 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1128 &irq_pcie_phandle, &irq_virtio_phandle, 1129 &msi_pcie_phandle); 1130 1131 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1132 1133 if (virt_is_iommu_sys_enabled(s)) { 1134 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, 1135 &iommu_sys_phandle); 1136 } 1137 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, 1138 iommu_sys_phandle); 1139 1140 create_fdt_reset(s, virt_memmap, &phandle); 1141 1142 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1143 1144 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1145 } 1146 1147 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1148 { 1149 MachineState *ms = MACHINE(s); 1150 uint8_t rng_seed[32]; 1151 g_autofree char *name = NULL; 1152 1153 ms->fdt = create_device_tree(&s->fdt_size); 1154 if (!ms->fdt) { 1155 error_report("create_device_tree() failed"); 1156 exit(1); 1157 } 1158 1159 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1160 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1161 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1162 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1163 1164 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1165 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1166 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1167 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1168 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1169 1170 /* 1171 * The "/soc/pci@..." node is needed for PCIE hotplugs 1172 * that might happen before finalize_fdt(). 1173 */ 1174 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1175 qemu_fdt_add_subnode(ms->fdt, name); 1176 1177 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1178 1179 /* Pass seed to RNG */ 1180 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1181 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1182 rng_seed, sizeof(rng_seed)); 1183 1184 qemu_fdt_add_subnode(ms->fdt, "/aliases"); 1185 1186 create_fdt_flash(s, memmap); 1187 create_fdt_fw_cfg(s, memmap); 1188 create_fdt_pmu(s); 1189 } 1190 1191 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1192 DeviceState *irqchip, 1193 RISCVVirtState *s) 1194 { 1195 DeviceState *dev; 1196 MemoryRegion *ecam_alias, *ecam_reg; 1197 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1198 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1199 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1200 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1201 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1202 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1203 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1204 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1205 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1206 qemu_irq irq; 1207 int i; 1208 1209 dev = qdev_new(TYPE_GPEX_HOST); 1210 1211 /* Set GPEX object properties for the virt machine */ 1212 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, 1213 ecam_base, NULL); 1214 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, 1215 ecam_size, NULL); 1216 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, 1217 mmio_base, NULL); 1218 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, 1219 mmio_size, NULL); 1220 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, 1221 high_mmio_base, NULL); 1222 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1223 high_mmio_size, NULL); 1224 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, 1225 pio_base, NULL); 1226 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, 1227 pio_size, NULL); 1228 1229 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1230 1231 ecam_alias = g_new0(MemoryRegion, 1); 1232 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1233 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1234 ecam_reg, 0, ecam_size); 1235 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1236 1237 mmio_alias = g_new0(MemoryRegion, 1); 1238 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1239 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1240 mmio_reg, mmio_base, mmio_size); 1241 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1242 1243 /* Map high MMIO space */ 1244 high_mmio_alias = g_new0(MemoryRegion, 1); 1245 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1246 mmio_reg, high_mmio_base, high_mmio_size); 1247 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1248 high_mmio_alias); 1249 1250 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1251 1252 for (i = 0; i < PCI_NUM_PINS; i++) { 1253 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1254 1255 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1256 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1257 } 1258 1259 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; 1260 return dev; 1261 } 1262 1263 static FWCfgState *create_fw_cfg(const MachineState *ms) 1264 { 1265 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1266 FWCfgState *fw_cfg; 1267 1268 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1269 &address_space_memory); 1270 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1271 1272 return fw_cfg; 1273 } 1274 1275 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1276 int base_hartid, int hart_count) 1277 { 1278 DeviceState *ret; 1279 g_autofree char *plic_hart_config = NULL; 1280 1281 /* Per-socket PLIC hart topology configuration string */ 1282 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1283 1284 /* Per-socket PLIC */ 1285 ret = sifive_plic_create( 1286 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1287 plic_hart_config, hart_count, base_hartid, 1288 VIRT_IRQCHIP_NUM_SOURCES, 1289 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1290 VIRT_PLIC_PRIORITY_BASE, 1291 VIRT_PLIC_PENDING_BASE, 1292 VIRT_PLIC_ENABLE_BASE, 1293 VIRT_PLIC_ENABLE_STRIDE, 1294 VIRT_PLIC_CONTEXT_BASE, 1295 VIRT_PLIC_CONTEXT_STRIDE, 1296 memmap[VIRT_PLIC].size); 1297 1298 return ret; 1299 } 1300 1301 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1302 const MemMapEntry *memmap, int socket, 1303 int base_hartid, int hart_count) 1304 { 1305 int i; 1306 hwaddr addr = 0; 1307 uint32_t guest_bits; 1308 DeviceState *aplic_s = NULL; 1309 DeviceState *aplic_m = NULL; 1310 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1311 1312 if (msimode) { 1313 if (!kvm_enabled()) { 1314 /* Per-socket M-level IMSICs */ 1315 addr = memmap[VIRT_IMSIC_M].base + 1316 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1317 for (i = 0; i < hart_count; i++) { 1318 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1319 base_hartid + i, true, 1, 1320 VIRT_IRQCHIP_NUM_MSIS); 1321 } 1322 } 1323 1324 /* Per-socket S-level IMSICs */ 1325 guest_bits = imsic_num_bits(aia_guests + 1); 1326 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1327 for (i = 0; i < hart_count; i++) { 1328 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1329 base_hartid + i, false, 1 + aia_guests, 1330 VIRT_IRQCHIP_NUM_MSIS); 1331 } 1332 } 1333 1334 if (!kvm_enabled()) { 1335 /* Per-socket M-level APLIC */ 1336 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1337 socket * memmap[VIRT_APLIC_M].size, 1338 memmap[VIRT_APLIC_M].size, 1339 (msimode) ? 0 : base_hartid, 1340 (msimode) ? 0 : hart_count, 1341 VIRT_IRQCHIP_NUM_SOURCES, 1342 VIRT_IRQCHIP_NUM_PRIO_BITS, 1343 msimode, true, NULL); 1344 } 1345 1346 /* Per-socket S-level APLIC */ 1347 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1348 socket * memmap[VIRT_APLIC_S].size, 1349 memmap[VIRT_APLIC_S].size, 1350 (msimode) ? 0 : base_hartid, 1351 (msimode) ? 0 : hart_count, 1352 VIRT_IRQCHIP_NUM_SOURCES, 1353 VIRT_IRQCHIP_NUM_PRIO_BITS, 1354 msimode, false, aplic_m); 1355 1356 if (kvm_enabled() && msimode) { 1357 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); 1358 } 1359 1360 return kvm_enabled() ? aplic_s : aplic_m; 1361 } 1362 1363 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1364 { 1365 DeviceState *dev; 1366 SysBusDevice *sysbus; 1367 const MemMapEntry *memmap = virt_memmap; 1368 int i; 1369 MemoryRegion *sysmem = get_system_memory(); 1370 1371 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1372 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1373 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1374 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1375 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1376 s->platform_bus_dev = dev; 1377 1378 sysbus = SYS_BUS_DEVICE(dev); 1379 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1380 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1381 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1382 } 1383 1384 memory_region_add_subregion(sysmem, 1385 memmap[VIRT_PLATFORM_BUS].base, 1386 sysbus_mmio_get_region(sysbus, 0)); 1387 } 1388 1389 static void virt_build_smbios(RISCVVirtState *s) 1390 { 1391 MachineClass *mc = MACHINE_GET_CLASS(s); 1392 MachineState *ms = MACHINE(s); 1393 uint8_t *smbios_tables, *smbios_anchor; 1394 size_t smbios_tables_len, smbios_anchor_len; 1395 struct smbios_phys_mem_area mem_array; 1396 const char *product = "QEMU Virtual Machine"; 1397 1398 if (kvm_enabled()) { 1399 product = "KVM Virtual Machine"; 1400 } 1401 1402 smbios_set_defaults("QEMU", product, mc->name); 1403 1404 if (riscv_is_32bit(&s->soc[0])) { 1405 smbios_set_default_processor_family(0x200); 1406 } else { 1407 smbios_set_default_processor_family(0x201); 1408 } 1409 1410 /* build the array of physical mem area from base_memmap */ 1411 mem_array.address = s->memmap[VIRT_DRAM].base; 1412 mem_array.length = ms->ram_size; 1413 1414 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1415 &mem_array, 1, 1416 &smbios_tables, &smbios_tables_len, 1417 &smbios_anchor, &smbios_anchor_len, 1418 &error_fatal); 1419 1420 if (smbios_anchor) { 1421 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1422 smbios_tables, smbios_tables_len); 1423 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1424 smbios_anchor, smbios_anchor_len); 1425 } 1426 } 1427 1428 static void virt_machine_done(Notifier *notifier, void *data) 1429 { 1430 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1431 machine_done); 1432 const MemMapEntry *memmap = virt_memmap; 1433 MachineState *machine = MACHINE(s); 1434 hwaddr start_addr = memmap[VIRT_DRAM].base; 1435 target_ulong firmware_end_addr, kernel_start_addr; 1436 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1437 uint64_t fdt_load_addr; 1438 uint64_t kernel_entry = 0; 1439 BlockBackend *pflash_blk0; 1440 RISCVBootInfo boot_info; 1441 1442 /* 1443 * An user provided dtb must include everything, including 1444 * dynamic sysbus devices. Our FDT needs to be finalized. 1445 */ 1446 if (machine->dtb == NULL) { 1447 finalize_fdt(s); 1448 } 1449 1450 /* 1451 * Only direct boot kernel is currently supported for KVM VM, 1452 * so the "-bios" parameter is not supported when KVM is enabled. 1453 */ 1454 if (kvm_enabled()) { 1455 if (machine->firmware) { 1456 if (strcmp(machine->firmware, "none")) { 1457 error_report("Machine mode firmware is not supported in " 1458 "combination with KVM."); 1459 exit(1); 1460 } 1461 } else { 1462 machine->firmware = g_strdup("none"); 1463 } 1464 } 1465 1466 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1467 &start_addr, NULL); 1468 1469 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1470 if (pflash_blk0) { 1471 if (machine->firmware && !strcmp(machine->firmware, "none") && 1472 !kvm_enabled()) { 1473 /* 1474 * Pflash was supplied but bios is none and not KVM guest, 1475 * let's overwrite the address we jump to after reset to 1476 * the base of the flash. 1477 */ 1478 start_addr = virt_memmap[VIRT_FLASH].base; 1479 } else { 1480 /* 1481 * Pflash was supplied but either KVM guest or bios is not none. 1482 * In this case, base of the flash would contain S-mode payload. 1483 */ 1484 riscv_setup_firmware_boot(machine); 1485 kernel_entry = virt_memmap[VIRT_FLASH].base; 1486 } 1487 } 1488 1489 riscv_boot_info_init(&boot_info, &s->soc[0]); 1490 1491 if (machine->kernel_filename && !kernel_entry) { 1492 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, 1493 firmware_end_addr); 1494 riscv_load_kernel(machine, &boot_info, kernel_start_addr, 1495 true, NULL); 1496 kernel_entry = boot_info.image_low_addr; 1497 } 1498 1499 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1500 memmap[VIRT_DRAM].size, 1501 machine, &boot_info); 1502 riscv_load_fdt(fdt_load_addr, machine->fdt); 1503 1504 /* load the reset vector */ 1505 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1506 virt_memmap[VIRT_MROM].base, 1507 virt_memmap[VIRT_MROM].size, kernel_entry, 1508 fdt_load_addr); 1509 1510 /* 1511 * Only direct boot kernel is currently supported for KVM VM, 1512 * So here setup kernel start address and fdt address. 1513 * TODO:Support firmware loading and integrate to TCG start 1514 */ 1515 if (kvm_enabled()) { 1516 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1517 } 1518 1519 virt_build_smbios(s); 1520 1521 if (virt_is_acpi_enabled(s)) { 1522 virt_acpi_setup(s); 1523 } 1524 } 1525 1526 static void virt_machine_init(MachineState *machine) 1527 { 1528 const MemMapEntry *memmap = virt_memmap; 1529 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1530 MemoryRegion *system_memory = get_system_memory(); 1531 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1532 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1533 int i, base_hartid, hart_count; 1534 int socket_count = riscv_socket_count(machine); 1535 1536 /* Check socket count limit */ 1537 if (VIRT_SOCKETS_MAX < socket_count) { 1538 error_report("number of sockets/nodes should be less than %d", 1539 VIRT_SOCKETS_MAX); 1540 exit(1); 1541 } 1542 1543 if (!virt_aclint_allowed() && s->have_aclint) { 1544 error_report("'aclint' is only available with TCG acceleration"); 1545 exit(1); 1546 } 1547 1548 /* Initialize sockets */ 1549 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1550 for (i = 0; i < socket_count; i++) { 1551 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1552 1553 if (!riscv_socket_check_hartids(machine, i)) { 1554 error_report("discontinuous hartids in socket%d", i); 1555 exit(1); 1556 } 1557 1558 base_hartid = riscv_socket_first_hartid(machine, i); 1559 if (base_hartid < 0) { 1560 error_report("can't find hartid base for socket%d", i); 1561 exit(1); 1562 } 1563 1564 hart_count = riscv_socket_hart_count(machine, i); 1565 if (hart_count < 0) { 1566 error_report("can't find hart count for socket%d", i); 1567 exit(1); 1568 } 1569 1570 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1571 TYPE_RISCV_HART_ARRAY); 1572 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1573 machine->cpu_type, &error_abort); 1574 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1575 base_hartid, &error_abort); 1576 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1577 hart_count, &error_abort); 1578 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1579 1580 if (virt_aclint_allowed() && s->have_aclint) { 1581 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1582 /* Per-socket ACLINT MTIMER */ 1583 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1584 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1585 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1586 base_hartid, hart_count, 1587 RISCV_ACLINT_DEFAULT_MTIMECMP, 1588 RISCV_ACLINT_DEFAULT_MTIME, 1589 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1590 } else { 1591 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1592 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1593 i * memmap[VIRT_CLINT].size, 1594 base_hartid, hart_count, false); 1595 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1596 i * memmap[VIRT_CLINT].size + 1597 RISCV_ACLINT_SWI_SIZE, 1598 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1599 base_hartid, hart_count, 1600 RISCV_ACLINT_DEFAULT_MTIMECMP, 1601 RISCV_ACLINT_DEFAULT_MTIME, 1602 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1603 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1604 i * memmap[VIRT_ACLINT_SSWI].size, 1605 base_hartid, hart_count, true); 1606 } 1607 } else if (tcg_enabled()) { 1608 /* Per-socket SiFive CLINT */ 1609 riscv_aclint_swi_create( 1610 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1611 base_hartid, hart_count, false); 1612 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1613 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1614 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1615 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1616 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1617 } 1618 1619 /* Per-socket interrupt controller */ 1620 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1621 s->irqchip[i] = virt_create_plic(memmap, i, 1622 base_hartid, hart_count); 1623 } else { 1624 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1625 memmap, i, base_hartid, 1626 hart_count); 1627 } 1628 1629 /* Try to use different IRQCHIP instance based device type */ 1630 if (i == 0) { 1631 mmio_irqchip = s->irqchip[i]; 1632 virtio_irqchip = s->irqchip[i]; 1633 pcie_irqchip = s->irqchip[i]; 1634 } 1635 if (i == 1) { 1636 virtio_irqchip = s->irqchip[i]; 1637 pcie_irqchip = s->irqchip[i]; 1638 } 1639 if (i == 2) { 1640 pcie_irqchip = s->irqchip[i]; 1641 } 1642 } 1643 1644 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { 1645 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1646 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1647 memmap[VIRT_APLIC_S].base, 1648 memmap[VIRT_IMSIC_S].base, 1649 s->aia_guests); 1650 } 1651 1652 if (riscv_is_32bit(&s->soc[0])) { 1653 #if HOST_LONG_BITS == 64 1654 /* limit RAM size in a 32-bit system */ 1655 if (machine->ram_size > 10 * GiB) { 1656 machine->ram_size = 10 * GiB; 1657 error_report("Limiting RAM size to 10 GiB"); 1658 } 1659 #endif 1660 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1661 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1662 } else { 1663 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1664 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1665 virt_high_pcie_memmap.base = 1666 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1667 } 1668 1669 s->memmap = virt_memmap; 1670 1671 /* register system main memory (actual RAM) */ 1672 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1673 machine->ram); 1674 1675 /* boot rom */ 1676 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1677 memmap[VIRT_MROM].size, &error_fatal); 1678 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1679 mask_rom); 1680 1681 /* 1682 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1683 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1684 */ 1685 s->fw_cfg = create_fw_cfg(machine); 1686 rom_set_fw(s->fw_cfg); 1687 1688 /* SiFive Test MMIO device */ 1689 sifive_test_create(memmap[VIRT_TEST].base); 1690 1691 /* VirtIO MMIO devices */ 1692 for (i = 0; i < VIRTIO_COUNT; i++) { 1693 sysbus_create_simple("virtio-mmio", 1694 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1695 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1696 } 1697 1698 gpex_pcie_init(system_memory, pcie_irqchip, s); 1699 1700 create_platform_bus(s, mmio_irqchip); 1701 1702 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1703 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1704 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1705 1706 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1707 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1708 1709 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1710 /* Map legacy -drive if=pflash to machine properties */ 1711 pflash_cfi01_legacy_drive(s->flash[i], 1712 drive_get(IF_PFLASH, 0, i)); 1713 } 1714 virt_flash_map(s, system_memory); 1715 1716 /* load/create device tree */ 1717 if (machine->dtb) { 1718 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1719 if (!machine->fdt) { 1720 error_report("load_device_tree() failed"); 1721 exit(1); 1722 } 1723 } else { 1724 create_fdt(s, memmap); 1725 } 1726 1727 if (virt_is_iommu_sys_enabled(s)) { 1728 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); 1729 1730 object_property_set_uint(OBJECT(iommu_sys), "addr", 1731 s->memmap[VIRT_IOMMU_SYS].base, 1732 &error_fatal); 1733 object_property_set_uint(OBJECT(iommu_sys), "base-irq", 1734 IOMMU_SYS_IRQ, 1735 &error_fatal); 1736 object_property_set_link(OBJECT(iommu_sys), "irqchip", 1737 OBJECT(mmio_irqchip), 1738 &error_fatal); 1739 1740 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); 1741 } 1742 1743 s->machine_done.notify = virt_machine_done; 1744 qemu_add_machine_init_done_notifier(&s->machine_done); 1745 } 1746 1747 static void virt_machine_instance_init(Object *obj) 1748 { 1749 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1750 1751 virt_flash_create(s); 1752 1753 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1754 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1755 s->acpi = ON_OFF_AUTO_AUTO; 1756 s->iommu_sys = ON_OFF_AUTO_AUTO; 1757 } 1758 1759 static char *virt_get_aia_guests(Object *obj, Error **errp) 1760 { 1761 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1762 1763 return g_strdup_printf("%d", s->aia_guests); 1764 } 1765 1766 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1767 { 1768 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1769 1770 s->aia_guests = atoi(val); 1771 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1772 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1773 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1774 VIRT_IRQCHIP_MAX_GUESTS); 1775 } 1776 } 1777 1778 static char *virt_get_aia(Object *obj, Error **errp) 1779 { 1780 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1781 const char *val; 1782 1783 switch (s->aia_type) { 1784 case VIRT_AIA_TYPE_APLIC: 1785 val = "aplic"; 1786 break; 1787 case VIRT_AIA_TYPE_APLIC_IMSIC: 1788 val = "aplic-imsic"; 1789 break; 1790 default: 1791 val = "none"; 1792 break; 1793 }; 1794 1795 return g_strdup(val); 1796 } 1797 1798 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1799 { 1800 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1801 1802 if (!strcmp(val, "none")) { 1803 s->aia_type = VIRT_AIA_TYPE_NONE; 1804 } else if (!strcmp(val, "aplic")) { 1805 s->aia_type = VIRT_AIA_TYPE_APLIC; 1806 } else if (!strcmp(val, "aplic-imsic")) { 1807 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1808 } else { 1809 error_setg(errp, "Invalid AIA interrupt controller type"); 1810 error_append_hint(errp, "Valid values are none, aplic, and " 1811 "aplic-imsic.\n"); 1812 } 1813 } 1814 1815 static bool virt_get_aclint(Object *obj, Error **errp) 1816 { 1817 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1818 1819 return s->have_aclint; 1820 } 1821 1822 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1823 { 1824 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1825 1826 s->have_aclint = value; 1827 } 1828 1829 bool virt_is_iommu_sys_enabled(RISCVVirtState *s) 1830 { 1831 return s->iommu_sys == ON_OFF_AUTO_ON; 1832 } 1833 1834 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, 1835 void *opaque, Error **errp) 1836 { 1837 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1838 OnOffAuto iommu_sys = s->iommu_sys; 1839 1840 visit_type_OnOffAuto(v, name, &iommu_sys, errp); 1841 } 1842 1843 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, 1844 void *opaque, Error **errp) 1845 { 1846 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1847 1848 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); 1849 } 1850 1851 bool virt_is_acpi_enabled(RISCVVirtState *s) 1852 { 1853 return s->acpi != ON_OFF_AUTO_OFF; 1854 } 1855 1856 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1857 void *opaque, Error **errp) 1858 { 1859 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1860 OnOffAuto acpi = s->acpi; 1861 1862 visit_type_OnOffAuto(v, name, &acpi, errp); 1863 } 1864 1865 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1866 void *opaque, Error **errp) 1867 { 1868 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1869 1870 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1871 } 1872 1873 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1874 DeviceState *dev) 1875 { 1876 MachineClass *mc = MACHINE_GET_CLASS(machine); 1877 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1878 1879 if (device_is_dynamic_sysbus(mc, dev) || 1880 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1881 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1882 s->iommu_sys = ON_OFF_AUTO_OFF; 1883 return HOTPLUG_HANDLER(machine); 1884 } 1885 1886 return NULL; 1887 } 1888 1889 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1890 DeviceState *dev, Error **errp) 1891 { 1892 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1893 1894 if (s->platform_bus_dev) { 1895 MachineClass *mc = MACHINE_GET_CLASS(s); 1896 1897 if (device_is_dynamic_sysbus(mc, dev)) { 1898 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1899 SYS_BUS_DEVICE(dev)); 1900 } 1901 } 1902 1903 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1904 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1905 } 1906 1907 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1908 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1909 s->iommu_sys = ON_OFF_AUTO_OFF; 1910 } 1911 } 1912 1913 static void virt_machine_class_init(ObjectClass *oc, void *data) 1914 { 1915 MachineClass *mc = MACHINE_CLASS(oc); 1916 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1917 1918 mc->desc = "RISC-V VirtIO board"; 1919 mc->init = virt_machine_init; 1920 mc->max_cpus = VIRT_CPUS_MAX; 1921 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1922 mc->block_default_type = IF_VIRTIO; 1923 mc->no_cdrom = 1; 1924 mc->pci_allow_0_address = true; 1925 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1926 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1927 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1928 mc->numa_mem_supported = true; 1929 /* platform instead of architectural choice */ 1930 mc->cpu_cluster_has_numa_boundary = true; 1931 mc->default_ram_id = "riscv_virt_board.ram"; 1932 assert(!mc->get_hotplug_handler); 1933 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1934 1935 hc->plug = virt_machine_device_plug_cb; 1936 1937 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1938 #ifdef CONFIG_TPM 1939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1940 #endif 1941 1942 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1943 virt_set_aclint); 1944 object_class_property_set_description(oc, "aclint", 1945 "(TCG only) Set on/off to " 1946 "enable/disable emulating " 1947 "ACLINT devices"); 1948 1949 object_class_property_add_str(oc, "aia", virt_get_aia, 1950 virt_set_aia); 1951 object_class_property_set_description(oc, "aia", 1952 "Set type of AIA interrupt " 1953 "controller. Valid values are " 1954 "none, aplic, and aplic-imsic."); 1955 1956 object_class_property_add_str(oc, "aia-guests", 1957 virt_get_aia_guests, 1958 virt_set_aia_guests); 1959 { 1960 g_autofree char *str = 1961 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1962 "Valid value should be between 0 and %d.", 1963 VIRT_IRQCHIP_MAX_GUESTS); 1964 object_class_property_set_description(oc, "aia-guests", str); 1965 } 1966 1967 object_class_property_add(oc, "acpi", "OnOffAuto", 1968 virt_get_acpi, virt_set_acpi, 1969 NULL, NULL); 1970 object_class_property_set_description(oc, "acpi", 1971 "Enable ACPI"); 1972 1973 object_class_property_add(oc, "iommu-sys", "OnOffAuto", 1974 virt_get_iommu_sys, virt_set_iommu_sys, 1975 NULL, NULL); 1976 object_class_property_set_description(oc, "iommu-sys", 1977 "Enable IOMMU platform device"); 1978 } 1979 1980 static const TypeInfo virt_machine_typeinfo = { 1981 .name = MACHINE_TYPE_NAME("virt"), 1982 .parent = TYPE_MACHINE, 1983 .class_init = virt_machine_class_init, 1984 .instance_init = virt_machine_instance_init, 1985 .instance_size = sizeof(RISCVVirtState), 1986 .interfaces = (InterfaceInfo[]) { 1987 { TYPE_HOTPLUG_HANDLER }, 1988 { } 1989 }, 1990 }; 1991 1992 static void virt_machine_init_register_types(void) 1993 { 1994 type_register_static(&virt_machine_typeinfo); 1995 } 1996 1997 type_init(virt_machine_init_register_types) 1998