1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial-mm.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/iommu.h" 36 #include "hw/riscv/riscv-iommu-bits.h" 37 #include "hw/riscv/virt.h" 38 #include "hw/riscv/boot.h" 39 #include "hw/riscv/numa.h" 40 #include "kvm/kvm_riscv.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/intc/riscv_aclint.h" 43 #include "hw/intc/riscv_aplic.h" 44 #include "hw/intc/sifive_plic.h" 45 #include "hw/misc/sifive_test.h" 46 #include "hw/platform-bus.h" 47 #include "chardev/char.h" 48 #include "system/device_tree.h" 49 #include "system/system.h" 50 #include "system/tcg.h" 51 #include "system/kvm.h" 52 #include "system/tpm.h" 53 #include "system/qtest.h" 54 #include "hw/pci/pci.h" 55 #include "hw/pci-host/gpex.h" 56 #include "hw/display/ramfb.h" 57 #include "hw/acpi/aml-build.h" 58 #include "qapi/qapi-visit-common.h" 59 #include "hw/virtio/virtio-iommu.h" 60 #include "hw/uefi/var-service-api.h" 61 62 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 63 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) 64 { 65 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 66 67 return riscv_is_kvm_aia_aplic_imsic(msimode); 68 } 69 70 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) 71 { 72 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 73 74 return riscv_use_emulated_aplic(msimode); 75 } 76 77 static bool virt_aclint_allowed(void) 78 { 79 return tcg_enabled() || qtest_enabled(); 80 } 81 82 static const MemMapEntry virt_memmap[] = { 83 [VIRT_DEBUG] = { 0x0, 0x100 }, 84 [VIRT_MROM] = { 0x1000, 0xf000 }, 85 [VIRT_TEST] = { 0x100000, 0x1000 }, 86 [VIRT_RTC] = { 0x101000, 0x1000 }, 87 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, 91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 95 [VIRT_UART0] = { 0x10000000, 0x100 }, 96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 97 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 98 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 103 [VIRT_DRAM] = { 0x80000000, 0x0 }, 104 }; 105 106 /* PCIe high mmio is fixed for RV32 */ 107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 108 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 109 110 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 111 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 112 113 static MemMapEntry virt_high_pcie_memmap; 114 115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 116 117 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 118 const char *name, 119 const char *alias_prop_name) 120 { 121 /* 122 * Create a single flash device. We use the same parameters as 123 * the flash devices on the ARM virt board. 124 */ 125 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 126 127 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 128 qdev_prop_set_uint8(dev, "width", 4); 129 qdev_prop_set_uint8(dev, "device-width", 2); 130 qdev_prop_set_bit(dev, "big-endian", false); 131 qdev_prop_set_uint16(dev, "id0", 0x89); 132 qdev_prop_set_uint16(dev, "id1", 0x18); 133 qdev_prop_set_uint16(dev, "id2", 0x00); 134 qdev_prop_set_uint16(dev, "id3", 0x00); 135 qdev_prop_set_string(dev, "name", name); 136 137 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 138 object_property_add_alias(OBJECT(s), alias_prop_name, 139 OBJECT(dev), "drive"); 140 141 return PFLASH_CFI01(dev); 142 } 143 144 static void virt_flash_create(RISCVVirtState *s) 145 { 146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 147 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 148 } 149 150 static void virt_flash_map1(PFlashCFI01 *flash, 151 hwaddr base, hwaddr size, 152 MemoryRegion *sysmem) 153 { 154 DeviceState *dev = DEVICE(flash); 155 156 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 157 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 158 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 160 161 memory_region_add_subregion(sysmem, base, 162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 163 0)); 164 } 165 166 static void virt_flash_map(RISCVVirtState *s, 167 MemoryRegion *sysmem) 168 { 169 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 170 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 171 172 virt_flash_map1(s->flash[0], flashbase, flashsize, 173 sysmem); 174 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 175 sysmem); 176 } 177 178 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 179 uint32_t irqchip_phandle) 180 { 181 int pin, dev; 182 uint32_t irq_map_stride = 0; 183 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 184 FDT_MAX_INT_MAP_WIDTH] = {}; 185 uint32_t *irq_map = full_irq_map; 186 187 /* This code creates a standard swizzle of interrupts such that 188 * each device's first interrupt is based on it's PCI_SLOT number. 189 * (See pci_swizzle_map_irq_fn()) 190 * 191 * We only need one entry per interrupt in the table (not one per 192 * possible slot) seeing the interrupt-map-mask will allow the table 193 * to wrap to any number of devices. 194 */ 195 for (dev = 0; dev < PCI_NUM_PINS; dev++) { 196 int devfn = dev * 0x8; 197 198 for (pin = 0; pin < PCI_NUM_PINS; pin++) { 199 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 200 int i = 0; 201 202 /* Fill PCI address cells */ 203 irq_map[i] = cpu_to_be32(devfn << 8); 204 i += FDT_PCI_ADDR_CELLS; 205 206 /* Fill PCI Interrupt cells */ 207 irq_map[i] = cpu_to_be32(pin + 1); 208 i += FDT_PCI_INT_CELLS; 209 210 /* Fill interrupt controller phandle and cells */ 211 irq_map[i++] = cpu_to_be32(irqchip_phandle); 212 irq_map[i++] = cpu_to_be32(irq_nr); 213 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 214 irq_map[i++] = cpu_to_be32(0x4); 215 } 216 217 if (!irq_map_stride) { 218 irq_map_stride = i; 219 } 220 irq_map += irq_map_stride; 221 } 222 } 223 224 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 225 PCI_NUM_PINS * PCI_NUM_PINS * 226 irq_map_stride * sizeof(uint32_t)); 227 228 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 229 0x1800, 0, 0, 0x7); 230 } 231 232 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 233 char *clust_name, uint32_t *phandle, 234 uint32_t *intc_phandles) 235 { 236 int cpu; 237 uint32_t cpu_phandle; 238 MachineState *ms = MACHINE(s); 239 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 240 uint8_t satp_mode_max; 241 242 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 243 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 244 g_autofree char *cpu_name = NULL; 245 g_autofree char *core_name = NULL; 246 g_autofree char *intc_name = NULL; 247 g_autofree char *sv_name = NULL; 248 249 cpu_phandle = (*phandle)++; 250 251 cpu_name = g_strdup_printf("/cpus/cpu@%d", 252 s->soc[socket].hartid_base + cpu); 253 qemu_fdt_add_subnode(ms->fdt, cpu_name); 254 255 if (cpu_ptr->cfg.satp_mode.supported != 0) { 256 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 257 sv_name = g_strdup_printf("riscv,%s", 258 satp_mode_str(satp_mode_max, is_32_bit)); 259 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 260 } 261 262 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 263 264 if (cpu_ptr->cfg.ext_zicbom) { 265 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 266 cpu_ptr->cfg.cbom_blocksize); 267 } 268 269 if (cpu_ptr->cfg.ext_zicboz) { 270 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 271 cpu_ptr->cfg.cboz_blocksize); 272 } 273 274 if (cpu_ptr->cfg.ext_zicbop) { 275 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 276 cpu_ptr->cfg.cbop_blocksize); 277 } 278 279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 280 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 281 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 282 s->soc[socket].hartid_base + cpu); 283 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 284 riscv_socket_fdt_write_id(ms, cpu_name, socket); 285 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 286 287 intc_phandles[cpu] = (*phandle)++; 288 289 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 290 qemu_fdt_add_subnode(ms->fdt, intc_name); 291 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 292 intc_phandles[cpu]); 293 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 294 "riscv,cpu-intc"); 295 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 296 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 297 298 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 299 qemu_fdt_add_subnode(ms->fdt, core_name); 300 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 301 } 302 } 303 304 static void create_fdt_socket_memory(RISCVVirtState *s, 305 const MemMapEntry *memmap, int socket) 306 { 307 g_autofree char *mem_name = NULL; 308 uint64_t addr, size; 309 MachineState *ms = MACHINE(s); 310 311 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 312 size = riscv_socket_mem_size(ms, socket); 313 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 314 qemu_fdt_add_subnode(ms->fdt, mem_name); 315 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 316 addr >> 32, addr, size >> 32, size); 317 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 318 riscv_socket_fdt_write_id(ms, mem_name, socket); 319 } 320 321 static void create_fdt_socket_clint(RISCVVirtState *s, 322 const MemMapEntry *memmap, int socket, 323 uint32_t *intc_phandles) 324 { 325 int cpu; 326 g_autofree char *clint_name = NULL; 327 g_autofree uint32_t *clint_cells = NULL; 328 unsigned long clint_addr; 329 MachineState *ms = MACHINE(s); 330 static const char * const clint_compat[2] = { 331 "sifive,clint0", "riscv,clint0" 332 }; 333 334 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 335 336 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 337 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 338 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 339 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 340 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 341 } 342 343 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 344 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 345 qemu_fdt_add_subnode(ms->fdt, clint_name); 346 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 347 (char **)&clint_compat, 348 ARRAY_SIZE(clint_compat)); 349 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 350 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 351 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 352 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 353 riscv_socket_fdt_write_id(ms, clint_name, socket); 354 } 355 356 static void create_fdt_socket_aclint(RISCVVirtState *s, 357 const MemMapEntry *memmap, int socket, 358 uint32_t *intc_phandles) 359 { 360 int cpu; 361 char *name; 362 unsigned long addr, size; 363 uint32_t aclint_cells_size; 364 g_autofree uint32_t *aclint_mswi_cells = NULL; 365 g_autofree uint32_t *aclint_sswi_cells = NULL; 366 g_autofree uint32_t *aclint_mtimer_cells = NULL; 367 MachineState *ms = MACHINE(s); 368 369 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 370 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 371 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 372 373 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 374 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 375 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 376 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 377 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 378 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 379 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 380 } 381 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 382 383 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 384 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 385 name = g_strdup_printf("/soc/mswi@%lx", addr); 386 qemu_fdt_add_subnode(ms->fdt, name); 387 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 388 "riscv,aclint-mswi"); 389 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 390 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 391 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 392 aclint_mswi_cells, aclint_cells_size); 393 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 394 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 395 riscv_socket_fdt_write_id(ms, name, socket); 396 g_free(name); 397 } 398 399 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 400 addr = memmap[VIRT_CLINT].base + 401 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 402 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 403 } else { 404 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 405 (memmap[VIRT_CLINT].size * socket); 406 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 407 } 408 name = g_strdup_printf("/soc/mtimer@%lx", addr); 409 qemu_fdt_add_subnode(ms->fdt, name); 410 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 411 "riscv,aclint-mtimer"); 412 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 413 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 414 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 415 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 416 0x0, RISCV_ACLINT_DEFAULT_MTIME); 417 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 418 aclint_mtimer_cells, aclint_cells_size); 419 riscv_socket_fdt_write_id(ms, name, socket); 420 g_free(name); 421 422 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 423 addr = memmap[VIRT_ACLINT_SSWI].base + 424 (memmap[VIRT_ACLINT_SSWI].size * socket); 425 name = g_strdup_printf("/soc/sswi@%lx", addr); 426 qemu_fdt_add_subnode(ms->fdt, name); 427 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 428 "riscv,aclint-sswi"); 429 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 430 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 431 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 432 aclint_sswi_cells, aclint_cells_size); 433 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 434 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 435 riscv_socket_fdt_write_id(ms, name, socket); 436 g_free(name); 437 } 438 } 439 440 static void create_fdt_socket_plic(RISCVVirtState *s, 441 const MemMapEntry *memmap, int socket, 442 uint32_t *phandle, uint32_t *intc_phandles, 443 uint32_t *plic_phandles) 444 { 445 int cpu; 446 g_autofree char *plic_name = NULL; 447 g_autofree uint32_t *plic_cells; 448 unsigned long plic_addr; 449 MachineState *ms = MACHINE(s); 450 static const char * const plic_compat[2] = { 451 "sifive,plic-1.0.0", "riscv,plic0" 452 }; 453 454 plic_phandles[socket] = (*phandle)++; 455 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 456 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 457 qemu_fdt_add_subnode(ms->fdt, plic_name); 458 qemu_fdt_setprop_cell(ms->fdt, plic_name, 459 "#interrupt-cells", FDT_PLIC_INT_CELLS); 460 qemu_fdt_setprop_cell(ms->fdt, plic_name, 461 "#address-cells", FDT_PLIC_ADDR_CELLS); 462 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 463 (char **)&plic_compat, 464 ARRAY_SIZE(plic_compat)); 465 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 466 467 if (kvm_enabled()) { 468 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 469 470 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 471 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 472 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 473 } 474 475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 476 plic_cells, 477 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 478 } else { 479 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 480 481 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 482 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 483 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 484 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 485 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 486 } 487 488 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 489 plic_cells, 490 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 491 } 492 493 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 494 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 495 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 496 VIRT_IRQCHIP_NUM_SOURCES - 1); 497 riscv_socket_fdt_write_id(ms, plic_name, socket); 498 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 499 plic_phandles[socket]); 500 501 if (!socket) { 502 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 503 memmap[VIRT_PLATFORM_BUS].base, 504 memmap[VIRT_PLATFORM_BUS].size, 505 VIRT_PLATFORM_BUS_IRQ); 506 } 507 } 508 509 uint32_t imsic_num_bits(uint32_t count) 510 { 511 uint32_t ret = 0; 512 513 while (BIT(ret) < count) { 514 ret++; 515 } 516 517 return ret; 518 } 519 520 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 521 uint32_t *intc_phandles, uint32_t msi_phandle, 522 bool m_mode, uint32_t imsic_guest_bits) 523 { 524 int cpu, socket; 525 g_autofree char *imsic_name = NULL; 526 MachineState *ms = MACHINE(s); 527 int socket_count = riscv_socket_count(ms); 528 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 529 g_autofree uint32_t *imsic_cells = NULL; 530 g_autofree uint32_t *imsic_regs = NULL; 531 static const char * const imsic_compat[2] = { 532 "qemu,imsics", "riscv,imsics" 533 }; 534 535 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 536 imsic_regs = g_new0(uint32_t, socket_count * 4); 537 538 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 539 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 540 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 541 } 542 543 imsic_max_hart_per_socket = 0; 544 for (socket = 0; socket < socket_count; socket++) { 545 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 546 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 547 s->soc[socket].num_harts; 548 imsic_regs[socket * 4 + 0] = 0; 549 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 550 imsic_regs[socket * 4 + 2] = 0; 551 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 552 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 553 imsic_max_hart_per_socket = s->soc[socket].num_harts; 554 } 555 } 556 557 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 558 (unsigned long)base_addr); 559 qemu_fdt_add_subnode(ms->fdt, imsic_name); 560 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 561 (char **)&imsic_compat, 562 ARRAY_SIZE(imsic_compat)); 563 564 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 565 FDT_IMSIC_INT_CELLS); 566 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 567 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 568 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 569 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 570 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 571 socket_count * sizeof(uint32_t) * 4); 572 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 573 VIRT_IRQCHIP_NUM_MSIS); 574 575 if (imsic_guest_bits) { 576 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 577 imsic_guest_bits); 578 } 579 580 if (socket_count > 1) { 581 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 582 imsic_num_bits(imsic_max_hart_per_socket)); 583 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 584 imsic_num_bits(socket_count)); 585 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 586 IMSIC_MMIO_GROUP_MIN_SHIFT); 587 } 588 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 589 } 590 591 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 592 uint32_t *phandle, uint32_t *intc_phandles, 593 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 594 { 595 *msi_m_phandle = (*phandle)++; 596 *msi_s_phandle = (*phandle)++; 597 598 if (!kvm_enabled()) { 599 /* M-level IMSIC node */ 600 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 601 *msi_m_phandle, true, 0); 602 } 603 604 /* S-level IMSIC node */ 605 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 606 *msi_s_phandle, false, 607 imsic_num_bits(s->aia_guests + 1)); 608 609 } 610 611 /* Caller must free string after use */ 612 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 613 { 614 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 615 } 616 617 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 618 unsigned long aplic_addr, uint32_t aplic_size, 619 uint32_t msi_phandle, 620 uint32_t *intc_phandles, 621 uint32_t aplic_phandle, 622 uint32_t aplic_child_phandle, 623 bool m_mode, int num_harts) 624 { 625 int cpu; 626 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 627 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 628 MachineState *ms = MACHINE(s); 629 static const char * const aplic_compat[2] = { 630 "qemu,aplic", "riscv,aplic" 631 }; 632 633 for (cpu = 0; cpu < num_harts; cpu++) { 634 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 635 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 636 } 637 638 qemu_fdt_add_subnode(ms->fdt, aplic_name); 639 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 640 (char **)&aplic_compat, 641 ARRAY_SIZE(aplic_compat)); 642 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 643 FDT_APLIC_ADDR_CELLS); 644 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 645 "#interrupt-cells", FDT_APLIC_INT_CELLS); 646 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 647 648 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 649 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 650 aplic_cells, num_harts * sizeof(uint32_t) * 2); 651 } else { 652 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 653 } 654 655 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 656 0x0, aplic_addr, 0x0, aplic_size); 657 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 658 VIRT_IRQCHIP_NUM_SOURCES); 659 660 if (aplic_child_phandle) { 661 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 662 aplic_child_phandle); 663 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 664 aplic_child_phandle, 0x1, 665 VIRT_IRQCHIP_NUM_SOURCES); 666 /* 667 * DEPRECATED_9.1: Compat property kept temporarily 668 * to allow old firmwares to work with AIA. Do *not* 669 * use 'riscv,delegate' in new code: use 670 * 'riscv,delegation' instead. 671 */ 672 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 673 aplic_child_phandle, 0x1, 674 VIRT_IRQCHIP_NUM_SOURCES); 675 } 676 677 riscv_socket_fdt_write_id(ms, aplic_name, socket); 678 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 679 } 680 681 static void create_fdt_socket_aplic(RISCVVirtState *s, 682 const MemMapEntry *memmap, int socket, 683 uint32_t msi_m_phandle, 684 uint32_t msi_s_phandle, 685 uint32_t *phandle, 686 uint32_t *intc_phandles, 687 uint32_t *aplic_phandles, 688 int num_harts) 689 { 690 unsigned long aplic_addr; 691 MachineState *ms = MACHINE(s); 692 uint32_t aplic_m_phandle, aplic_s_phandle; 693 694 aplic_m_phandle = (*phandle)++; 695 aplic_s_phandle = (*phandle)++; 696 697 if (!kvm_enabled()) { 698 /* M-level APLIC node */ 699 aplic_addr = memmap[VIRT_APLIC_M].base + 700 (memmap[VIRT_APLIC_M].size * socket); 701 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 702 msi_m_phandle, intc_phandles, 703 aplic_m_phandle, aplic_s_phandle, 704 true, num_harts); 705 } 706 707 /* S-level APLIC node */ 708 aplic_addr = memmap[VIRT_APLIC_S].base + 709 (memmap[VIRT_APLIC_S].size * socket); 710 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 711 msi_s_phandle, intc_phandles, 712 aplic_s_phandle, 0, 713 false, num_harts); 714 715 if (!socket) { 716 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 717 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 718 memmap[VIRT_PLATFORM_BUS].base, 719 memmap[VIRT_PLATFORM_BUS].size, 720 VIRT_PLATFORM_BUS_IRQ); 721 } 722 723 aplic_phandles[socket] = aplic_s_phandle; 724 } 725 726 static void create_fdt_pmu(RISCVVirtState *s) 727 { 728 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 729 MachineState *ms = MACHINE(s); 730 RISCVCPU hart = s->soc[0].harts[0]; 731 732 qemu_fdt_add_subnode(ms->fdt, pmu_name); 733 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 734 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 735 } 736 737 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 738 uint32_t *phandle, 739 uint32_t *irq_mmio_phandle, 740 uint32_t *irq_pcie_phandle, 741 uint32_t *irq_virtio_phandle, 742 uint32_t *msi_pcie_phandle) 743 { 744 int socket, phandle_pos; 745 MachineState *ms = MACHINE(s); 746 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 747 uint32_t xplic_phandles[MAX_NODES]; 748 g_autofree uint32_t *intc_phandles = NULL; 749 int socket_count = riscv_socket_count(ms); 750 751 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 752 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 753 kvm_enabled() ? 754 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : 755 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 756 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 757 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 758 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 759 760 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 761 762 phandle_pos = ms->smp.cpus; 763 for (socket = (socket_count - 1); socket >= 0; socket--) { 764 g_autofree char *clust_name = NULL; 765 phandle_pos -= s->soc[socket].num_harts; 766 767 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 768 qemu_fdt_add_subnode(ms->fdt, clust_name); 769 770 create_fdt_socket_cpus(s, socket, clust_name, phandle, 771 &intc_phandles[phandle_pos]); 772 773 create_fdt_socket_memory(s, memmap, socket); 774 775 if (virt_aclint_allowed() && s->have_aclint) { 776 create_fdt_socket_aclint(s, memmap, socket, 777 &intc_phandles[phandle_pos]); 778 } else if (tcg_enabled()) { 779 create_fdt_socket_clint(s, memmap, socket, 780 &intc_phandles[phandle_pos]); 781 } 782 } 783 784 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 785 create_fdt_imsic(s, memmap, phandle, intc_phandles, 786 &msi_m_phandle, &msi_s_phandle); 787 *msi_pcie_phandle = msi_s_phandle; 788 } 789 790 /* 791 * With KVM AIA aplic-imsic, using an irqchip without split 792 * mode, we'll use only one APLIC instance. 793 */ 794 if (!virt_use_emulated_aplic(s->aia_type)) { 795 create_fdt_socket_aplic(s, memmap, 0, 796 msi_m_phandle, msi_s_phandle, phandle, 797 &intc_phandles[0], xplic_phandles, 798 ms->smp.cpus); 799 800 *irq_mmio_phandle = xplic_phandles[0]; 801 *irq_virtio_phandle = xplic_phandles[0]; 802 *irq_pcie_phandle = xplic_phandles[0]; 803 } else { 804 phandle_pos = ms->smp.cpus; 805 for (socket = (socket_count - 1); socket >= 0; socket--) { 806 phandle_pos -= s->soc[socket].num_harts; 807 808 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 809 create_fdt_socket_plic(s, memmap, socket, phandle, 810 &intc_phandles[phandle_pos], 811 xplic_phandles); 812 } else { 813 create_fdt_socket_aplic(s, memmap, socket, 814 msi_m_phandle, msi_s_phandle, phandle, 815 &intc_phandles[phandle_pos], 816 xplic_phandles, 817 s->soc[socket].num_harts); 818 } 819 } 820 821 for (socket = 0; socket < socket_count; socket++) { 822 if (socket == 0) { 823 *irq_mmio_phandle = xplic_phandles[socket]; 824 *irq_virtio_phandle = xplic_phandles[socket]; 825 *irq_pcie_phandle = xplic_phandles[socket]; 826 } 827 if (socket == 1) { 828 *irq_virtio_phandle = xplic_phandles[socket]; 829 *irq_pcie_phandle = xplic_phandles[socket]; 830 } 831 if (socket == 2) { 832 *irq_pcie_phandle = xplic_phandles[socket]; 833 } 834 } 835 } 836 837 riscv_socket_fdt_write_distance_matrix(ms); 838 } 839 840 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 841 uint32_t irq_virtio_phandle) 842 { 843 int i; 844 MachineState *ms = MACHINE(s); 845 846 for (i = 0; i < VIRTIO_COUNT; i++) { 847 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 848 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 849 850 qemu_fdt_add_subnode(ms->fdt, name); 851 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 852 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 853 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 854 0x0, memmap[VIRT_VIRTIO].size); 855 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 856 irq_virtio_phandle); 857 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 858 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 859 VIRTIO_IRQ + i); 860 } else { 861 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 862 VIRTIO_IRQ + i, 0x4); 863 } 864 } 865 } 866 867 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 868 uint32_t irq_pcie_phandle, 869 uint32_t msi_pcie_phandle, 870 uint32_t iommu_sys_phandle) 871 { 872 g_autofree char *name = NULL; 873 MachineState *ms = MACHINE(s); 874 875 name = g_strdup_printf("/soc/pci@%lx", 876 (long) memmap[VIRT_PCIE_ECAM].base); 877 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 878 FDT_PCI_ADDR_CELLS); 879 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 880 FDT_PCI_INT_CELLS); 881 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 882 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 883 "pci-host-ecam-generic"); 884 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 885 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 886 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 887 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 888 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 889 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 890 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 891 } 892 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 893 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 894 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 895 1, FDT_PCI_RANGE_IOPORT, 2, 0, 896 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 897 1, FDT_PCI_RANGE_MMIO, 898 2, memmap[VIRT_PCIE_MMIO].base, 899 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 900 1, FDT_PCI_RANGE_MMIO_64BIT, 901 2, virt_high_pcie_memmap.base, 902 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 903 904 if (virt_is_iommu_sys_enabled(s)) { 905 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", 906 0, iommu_sys_phandle, 0, 0, 0, 907 iommu_sys_phandle, 0, 0xffff); 908 } 909 910 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 911 } 912 913 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 914 uint32_t *phandle) 915 { 916 char *name; 917 uint32_t test_phandle; 918 MachineState *ms = MACHINE(s); 919 920 test_phandle = (*phandle)++; 921 name = g_strdup_printf("/soc/test@%lx", 922 (long)memmap[VIRT_TEST].base); 923 qemu_fdt_add_subnode(ms->fdt, name); 924 { 925 static const char * const compat[3] = { 926 "sifive,test1", "sifive,test0", "syscon" 927 }; 928 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 929 (char **)&compat, ARRAY_SIZE(compat)); 930 } 931 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 932 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 933 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 934 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 935 g_free(name); 936 937 name = g_strdup_printf("/reboot"); 938 qemu_fdt_add_subnode(ms->fdt, name); 939 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 940 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 941 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 942 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 943 g_free(name); 944 945 name = g_strdup_printf("/poweroff"); 946 qemu_fdt_add_subnode(ms->fdt, name); 947 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 948 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 949 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 950 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 951 g_free(name); 952 } 953 954 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 955 uint32_t irq_mmio_phandle) 956 { 957 g_autofree char *name = NULL; 958 MachineState *ms = MACHINE(s); 959 960 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 961 qemu_fdt_add_subnode(ms->fdt, name); 962 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 963 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 964 0x0, memmap[VIRT_UART0].base, 965 0x0, memmap[VIRT_UART0].size); 966 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 967 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 968 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 969 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 970 } else { 971 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 972 } 973 974 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 975 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); 976 } 977 978 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 979 uint32_t irq_mmio_phandle) 980 { 981 g_autofree char *name = NULL; 982 MachineState *ms = MACHINE(s); 983 984 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 985 qemu_fdt_add_subnode(ms->fdt, name); 986 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 987 "google,goldfish-rtc"); 988 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 989 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 990 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 991 irq_mmio_phandle); 992 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 993 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 994 } else { 995 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 996 } 997 } 998 999 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 1000 { 1001 MachineState *ms = MACHINE(s); 1002 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 1003 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 1004 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 1005 1006 qemu_fdt_add_subnode(ms->fdt, name); 1007 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 1008 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 1009 2, flashbase, 2, flashsize, 1010 2, flashbase + flashsize, 2, flashsize); 1011 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 1012 } 1013 1014 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 1015 { 1016 MachineState *ms = MACHINE(s); 1017 hwaddr base = memmap[VIRT_FW_CFG].base; 1018 hwaddr size = memmap[VIRT_FW_CFG].size; 1019 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1020 1021 qemu_fdt_add_subnode(ms->fdt, nodename); 1022 qemu_fdt_setprop_string(ms->fdt, nodename, 1023 "compatible", "qemu,fw-cfg-mmio"); 1024 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1025 2, base, 2, size); 1026 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1027 } 1028 1029 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1030 { 1031 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1032 void *fdt = MACHINE(s)->fdt; 1033 uint32_t iommu_phandle; 1034 g_autofree char *iommu_node = NULL; 1035 g_autofree char *pci_node = NULL; 1036 1037 pci_node = g_strdup_printf("/soc/pci@%lx", 1038 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1039 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1040 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1041 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1042 1043 qemu_fdt_add_subnode(fdt, iommu_node); 1044 1045 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1046 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1047 1, bdf << 8, 1, 0, 1, 0, 1048 1, 0, 1, 0); 1049 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1050 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1051 1052 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1053 0, iommu_phandle, 0, bdf, 1054 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1055 } 1056 1057 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, 1058 uint32_t msi_phandle, 1059 uint32_t *iommu_sys_phandle) 1060 { 1061 const char comp[] = "riscv,iommu"; 1062 void *fdt = MACHINE(s)->fdt; 1063 uint32_t iommu_phandle; 1064 g_autofree char *iommu_node = NULL; 1065 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; 1066 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; 1067 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { 1068 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, 1069 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, 1070 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, 1071 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, 1072 }; 1073 1074 iommu_node = g_strdup_printf("/soc/iommu@%x", 1075 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); 1076 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1077 qemu_fdt_add_subnode(fdt, iommu_node); 1078 1079 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1080 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1081 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1082 1083 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1084 addr >> 32, addr, size >> 32, size); 1085 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); 1086 1087 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", 1088 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, 1089 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, 1090 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, 1091 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); 1092 1093 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); 1094 1095 *iommu_sys_phandle = iommu_phandle; 1096 } 1097 1098 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) 1099 { 1100 const char comp[] = "riscv,pci-iommu"; 1101 void *fdt = MACHINE(s)->fdt; 1102 uint32_t iommu_phandle; 1103 g_autofree char *iommu_node = NULL; 1104 g_autofree char *pci_node = NULL; 1105 1106 pci_node = g_strdup_printf("/soc/pci@%lx", 1107 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1108 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); 1109 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1110 qemu_fdt_add_subnode(fdt, iommu_node); 1111 1112 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1113 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1114 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1115 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1116 bdf << 8, 0, 0, 0, 0); 1117 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1118 0, iommu_phandle, 0, bdf, 1119 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1120 } 1121 1122 static void finalize_fdt(RISCVVirtState *s) 1123 { 1124 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1125 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1126 uint32_t iommu_sys_phandle = 1; 1127 1128 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1129 &irq_pcie_phandle, &irq_virtio_phandle, 1130 &msi_pcie_phandle); 1131 1132 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1133 1134 if (virt_is_iommu_sys_enabled(s)) { 1135 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, 1136 &iommu_sys_phandle); 1137 } 1138 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, 1139 iommu_sys_phandle); 1140 1141 create_fdt_reset(s, virt_memmap, &phandle); 1142 1143 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1144 1145 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1146 } 1147 1148 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1149 { 1150 MachineState *ms = MACHINE(s); 1151 uint8_t rng_seed[32]; 1152 g_autofree char *name = NULL; 1153 1154 ms->fdt = create_device_tree(&s->fdt_size); 1155 if (!ms->fdt) { 1156 error_report("create_device_tree() failed"); 1157 exit(1); 1158 } 1159 1160 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1161 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1162 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1163 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1164 1165 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1166 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1167 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1168 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1169 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1170 1171 /* 1172 * The "/soc/pci@..." node is needed for PCIE hotplugs 1173 * that might happen before finalize_fdt(). 1174 */ 1175 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1176 qemu_fdt_add_subnode(ms->fdt, name); 1177 1178 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1179 1180 /* Pass seed to RNG */ 1181 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1182 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1183 rng_seed, sizeof(rng_seed)); 1184 1185 qemu_fdt_add_subnode(ms->fdt, "/aliases"); 1186 1187 create_fdt_flash(s, memmap); 1188 create_fdt_fw_cfg(s, memmap); 1189 create_fdt_pmu(s); 1190 } 1191 1192 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1193 DeviceState *irqchip, 1194 RISCVVirtState *s) 1195 { 1196 DeviceState *dev; 1197 MemoryRegion *ecam_alias, *ecam_reg; 1198 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1199 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1200 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1201 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1202 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1203 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1204 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1205 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1206 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1207 qemu_irq irq; 1208 int i; 1209 1210 dev = qdev_new(TYPE_GPEX_HOST); 1211 1212 /* Set GPEX object properties for the virt machine */ 1213 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, 1214 ecam_base, NULL); 1215 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, 1216 ecam_size, NULL); 1217 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, 1218 mmio_base, NULL); 1219 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, 1220 mmio_size, NULL); 1221 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, 1222 high_mmio_base, NULL); 1223 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1224 high_mmio_size, NULL); 1225 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, 1226 pio_base, NULL); 1227 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, 1228 pio_size, NULL); 1229 1230 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1231 1232 ecam_alias = g_new0(MemoryRegion, 1); 1233 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1234 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1235 ecam_reg, 0, ecam_size); 1236 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1237 1238 mmio_alias = g_new0(MemoryRegion, 1); 1239 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1240 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1241 mmio_reg, mmio_base, mmio_size); 1242 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1243 1244 /* Map high MMIO space */ 1245 high_mmio_alias = g_new0(MemoryRegion, 1); 1246 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1247 mmio_reg, high_mmio_base, high_mmio_size); 1248 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1249 high_mmio_alias); 1250 1251 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1252 1253 for (i = 0; i < PCI_NUM_PINS; i++) { 1254 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1255 1256 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1257 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1258 } 1259 1260 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; 1261 return dev; 1262 } 1263 1264 static FWCfgState *create_fw_cfg(const MachineState *ms) 1265 { 1266 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1267 FWCfgState *fw_cfg; 1268 1269 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1270 &address_space_memory); 1271 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1272 1273 return fw_cfg; 1274 } 1275 1276 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1277 int base_hartid, int hart_count) 1278 { 1279 g_autofree char *plic_hart_config = NULL; 1280 1281 /* Per-socket PLIC hart topology configuration string */ 1282 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1283 1284 /* Per-socket PLIC */ 1285 return sifive_plic_create( 1286 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1287 plic_hart_config, hart_count, base_hartid, 1288 VIRT_IRQCHIP_NUM_SOURCES, 1289 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1290 VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE, 1291 VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE, 1292 VIRT_PLIC_CONTEXT_BASE, 1293 VIRT_PLIC_CONTEXT_STRIDE, 1294 memmap[VIRT_PLIC].size); 1295 } 1296 1297 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1298 const MemMapEntry *memmap, int socket, 1299 int base_hartid, int hart_count) 1300 { 1301 int i; 1302 hwaddr addr = 0; 1303 uint32_t guest_bits; 1304 DeviceState *aplic_s = NULL; 1305 DeviceState *aplic_m = NULL; 1306 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1307 1308 if (msimode) { 1309 if (!kvm_enabled()) { 1310 /* Per-socket M-level IMSICs */ 1311 addr = memmap[VIRT_IMSIC_M].base + 1312 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1313 for (i = 0; i < hart_count; i++) { 1314 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1315 base_hartid + i, true, 1, 1316 VIRT_IRQCHIP_NUM_MSIS); 1317 } 1318 } 1319 1320 /* Per-socket S-level IMSICs */ 1321 guest_bits = imsic_num_bits(aia_guests + 1); 1322 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1323 for (i = 0; i < hart_count; i++) { 1324 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1325 base_hartid + i, false, 1 + aia_guests, 1326 VIRT_IRQCHIP_NUM_MSIS); 1327 } 1328 } 1329 1330 if (!kvm_enabled()) { 1331 /* Per-socket M-level APLIC */ 1332 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1333 socket * memmap[VIRT_APLIC_M].size, 1334 memmap[VIRT_APLIC_M].size, 1335 (msimode) ? 0 : base_hartid, 1336 (msimode) ? 0 : hart_count, 1337 VIRT_IRQCHIP_NUM_SOURCES, 1338 VIRT_IRQCHIP_NUM_PRIO_BITS, 1339 msimode, true, NULL); 1340 } 1341 1342 /* Per-socket S-level APLIC */ 1343 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1344 socket * memmap[VIRT_APLIC_S].size, 1345 memmap[VIRT_APLIC_S].size, 1346 (msimode) ? 0 : base_hartid, 1347 (msimode) ? 0 : hart_count, 1348 VIRT_IRQCHIP_NUM_SOURCES, 1349 VIRT_IRQCHIP_NUM_PRIO_BITS, 1350 msimode, false, aplic_m); 1351 1352 if (kvm_enabled() && msimode) { 1353 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); 1354 } 1355 1356 return kvm_enabled() ? aplic_s : aplic_m; 1357 } 1358 1359 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1360 { 1361 DeviceState *dev; 1362 SysBusDevice *sysbus; 1363 const MemMapEntry *memmap = virt_memmap; 1364 int i; 1365 MemoryRegion *sysmem = get_system_memory(); 1366 1367 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1368 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1369 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1370 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1371 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1372 s->platform_bus_dev = dev; 1373 1374 sysbus = SYS_BUS_DEVICE(dev); 1375 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1376 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1377 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1378 } 1379 1380 memory_region_add_subregion(sysmem, 1381 memmap[VIRT_PLATFORM_BUS].base, 1382 sysbus_mmio_get_region(sysbus, 0)); 1383 } 1384 1385 static void virt_build_smbios(RISCVVirtState *s) 1386 { 1387 MachineClass *mc = MACHINE_GET_CLASS(s); 1388 MachineState *ms = MACHINE(s); 1389 uint8_t *smbios_tables, *smbios_anchor; 1390 size_t smbios_tables_len, smbios_anchor_len; 1391 struct smbios_phys_mem_area mem_array; 1392 const char *product = "QEMU Virtual Machine"; 1393 1394 if (kvm_enabled()) { 1395 product = "KVM Virtual Machine"; 1396 } 1397 1398 smbios_set_defaults("QEMU", product, mc->name); 1399 1400 if (riscv_is_32bit(&s->soc[0])) { 1401 smbios_set_default_processor_family(0x200); 1402 } else { 1403 smbios_set_default_processor_family(0x201); 1404 } 1405 1406 /* build the array of physical mem area from base_memmap */ 1407 mem_array.address = s->memmap[VIRT_DRAM].base; 1408 mem_array.length = ms->ram_size; 1409 1410 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1411 &mem_array, 1, 1412 &smbios_tables, &smbios_tables_len, 1413 &smbios_anchor, &smbios_anchor_len, 1414 &error_fatal); 1415 1416 if (smbios_anchor) { 1417 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1418 smbios_tables, smbios_tables_len); 1419 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1420 smbios_anchor, smbios_anchor_len); 1421 } 1422 } 1423 1424 static void virt_machine_done(Notifier *notifier, void *data) 1425 { 1426 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1427 machine_done); 1428 const MemMapEntry *memmap = virt_memmap; 1429 MachineState *machine = MACHINE(s); 1430 hwaddr start_addr = memmap[VIRT_DRAM].base; 1431 target_ulong firmware_end_addr, kernel_start_addr; 1432 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1433 uint64_t fdt_load_addr; 1434 uint64_t kernel_entry = 0; 1435 BlockBackend *pflash_blk0; 1436 RISCVBootInfo boot_info; 1437 1438 /* 1439 * An user provided dtb must include everything, including 1440 * dynamic sysbus devices. Our FDT needs to be finalized. 1441 */ 1442 if (machine->dtb == NULL) { 1443 finalize_fdt(s); 1444 } 1445 1446 /* 1447 * Only direct boot kernel is currently supported for KVM VM, 1448 * so the "-bios" parameter is not supported when KVM is enabled. 1449 */ 1450 if (kvm_enabled()) { 1451 if (machine->firmware) { 1452 if (strcmp(machine->firmware, "none")) { 1453 error_report("Machine mode firmware is not supported in " 1454 "combination with KVM."); 1455 exit(1); 1456 } 1457 } else { 1458 machine->firmware = g_strdup("none"); 1459 } 1460 } 1461 1462 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1463 &start_addr, NULL); 1464 1465 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1466 if (pflash_blk0) { 1467 if (machine->firmware && !strcmp(machine->firmware, "none") && 1468 !kvm_enabled()) { 1469 /* 1470 * Pflash was supplied but bios is none and not KVM guest, 1471 * let's overwrite the address we jump to after reset to 1472 * the base of the flash. 1473 */ 1474 start_addr = virt_memmap[VIRT_FLASH].base; 1475 } else { 1476 /* 1477 * Pflash was supplied but either KVM guest or bios is not none. 1478 * In this case, base of the flash would contain S-mode payload. 1479 */ 1480 riscv_setup_firmware_boot(machine); 1481 kernel_entry = virt_memmap[VIRT_FLASH].base; 1482 } 1483 } 1484 1485 riscv_boot_info_init(&boot_info, &s->soc[0]); 1486 1487 if (machine->kernel_filename && !kernel_entry) { 1488 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, 1489 firmware_end_addr); 1490 riscv_load_kernel(machine, &boot_info, kernel_start_addr, 1491 true, NULL); 1492 kernel_entry = boot_info.image_low_addr; 1493 } 1494 1495 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1496 memmap[VIRT_DRAM].size, 1497 machine, &boot_info); 1498 riscv_load_fdt(fdt_load_addr, machine->fdt); 1499 1500 /* load the reset vector */ 1501 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1502 virt_memmap[VIRT_MROM].base, 1503 virt_memmap[VIRT_MROM].size, kernel_entry, 1504 fdt_load_addr); 1505 1506 /* 1507 * Only direct boot kernel is currently supported for KVM VM, 1508 * So here setup kernel start address and fdt address. 1509 * TODO:Support firmware loading and integrate to TCG start 1510 */ 1511 if (kvm_enabled()) { 1512 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1513 } 1514 1515 virt_build_smbios(s); 1516 1517 if (virt_is_acpi_enabled(s)) { 1518 virt_acpi_setup(s); 1519 } 1520 } 1521 1522 static void virt_machine_init(MachineState *machine) 1523 { 1524 const MemMapEntry *memmap = virt_memmap; 1525 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1526 MemoryRegion *system_memory = get_system_memory(); 1527 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1528 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1529 int i, base_hartid, hart_count; 1530 int socket_count = riscv_socket_count(machine); 1531 1532 /* Check socket count limit */ 1533 if (VIRT_SOCKETS_MAX < socket_count) { 1534 error_report("number of sockets/nodes should be less than %d", 1535 VIRT_SOCKETS_MAX); 1536 exit(1); 1537 } 1538 1539 if (!virt_aclint_allowed() && s->have_aclint) { 1540 error_report("'aclint' is only available with TCG acceleration"); 1541 exit(1); 1542 } 1543 1544 /* Initialize sockets */ 1545 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1546 for (i = 0; i < socket_count; i++) { 1547 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1548 1549 if (!riscv_socket_check_hartids(machine, i)) { 1550 error_report("discontinuous hartids in socket%d", i); 1551 exit(1); 1552 } 1553 1554 base_hartid = riscv_socket_first_hartid(machine, i); 1555 if (base_hartid < 0) { 1556 error_report("can't find hartid base for socket%d", i); 1557 exit(1); 1558 } 1559 1560 hart_count = riscv_socket_hart_count(machine, i); 1561 if (hart_count < 0) { 1562 error_report("can't find hart count for socket%d", i); 1563 exit(1); 1564 } 1565 1566 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1567 TYPE_RISCV_HART_ARRAY); 1568 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1569 machine->cpu_type, &error_abort); 1570 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1571 base_hartid, &error_abort); 1572 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1573 hart_count, &error_abort); 1574 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1575 1576 if (virt_aclint_allowed() && s->have_aclint) { 1577 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1578 /* Per-socket ACLINT MTIMER */ 1579 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1580 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1581 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1582 base_hartid, hart_count, 1583 RISCV_ACLINT_DEFAULT_MTIMECMP, 1584 RISCV_ACLINT_DEFAULT_MTIME, 1585 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1586 } else { 1587 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1588 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1589 i * memmap[VIRT_CLINT].size, 1590 base_hartid, hart_count, false); 1591 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1592 i * memmap[VIRT_CLINT].size + 1593 RISCV_ACLINT_SWI_SIZE, 1594 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1595 base_hartid, hart_count, 1596 RISCV_ACLINT_DEFAULT_MTIMECMP, 1597 RISCV_ACLINT_DEFAULT_MTIME, 1598 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1599 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1600 i * memmap[VIRT_ACLINT_SSWI].size, 1601 base_hartid, hart_count, true); 1602 } 1603 } else if (tcg_enabled()) { 1604 /* Per-socket SiFive CLINT */ 1605 riscv_aclint_swi_create( 1606 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1607 base_hartid, hart_count, false); 1608 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1609 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1610 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1611 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1612 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1613 } 1614 1615 /* Per-socket interrupt controller */ 1616 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1617 s->irqchip[i] = virt_create_plic(memmap, i, 1618 base_hartid, hart_count); 1619 } else { 1620 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1621 memmap, i, base_hartid, 1622 hart_count); 1623 } 1624 1625 /* Try to use different IRQCHIP instance based device type */ 1626 if (i == 0) { 1627 mmio_irqchip = s->irqchip[i]; 1628 virtio_irqchip = s->irqchip[i]; 1629 pcie_irqchip = s->irqchip[i]; 1630 } 1631 if (i == 1) { 1632 virtio_irqchip = s->irqchip[i]; 1633 pcie_irqchip = s->irqchip[i]; 1634 } 1635 if (i == 2) { 1636 pcie_irqchip = s->irqchip[i]; 1637 } 1638 } 1639 1640 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { 1641 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1642 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1643 memmap[VIRT_APLIC_S].base, 1644 memmap[VIRT_IMSIC_S].base, 1645 s->aia_guests); 1646 } 1647 1648 if (riscv_is_32bit(&s->soc[0])) { 1649 #if HOST_LONG_BITS == 64 1650 /* limit RAM size in a 32-bit system */ 1651 if (machine->ram_size > 10 * GiB) { 1652 machine->ram_size = 10 * GiB; 1653 error_report("Limiting RAM size to 10 GiB"); 1654 } 1655 #endif 1656 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1657 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1658 } else { 1659 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1660 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1661 virt_high_pcie_memmap.base = 1662 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1663 } 1664 1665 s->memmap = virt_memmap; 1666 1667 /* register system main memory (actual RAM) */ 1668 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1669 machine->ram); 1670 1671 /* boot rom */ 1672 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1673 memmap[VIRT_MROM].size, &error_fatal); 1674 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1675 mask_rom); 1676 1677 /* 1678 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1679 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1680 */ 1681 s->fw_cfg = create_fw_cfg(machine); 1682 rom_set_fw(s->fw_cfg); 1683 1684 /* SiFive Test MMIO device */ 1685 sifive_test_create(memmap[VIRT_TEST].base); 1686 1687 /* VirtIO MMIO devices */ 1688 for (i = 0; i < VIRTIO_COUNT; i++) { 1689 sysbus_create_simple("virtio-mmio", 1690 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1691 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1692 } 1693 1694 gpex_pcie_init(system_memory, pcie_irqchip, s); 1695 1696 create_platform_bus(s, mmio_irqchip); 1697 1698 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1699 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1700 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1701 1702 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1703 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1704 1705 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1706 /* Map legacy -drive if=pflash to machine properties */ 1707 pflash_cfi01_legacy_drive(s->flash[i], 1708 drive_get(IF_PFLASH, 0, i)); 1709 } 1710 virt_flash_map(s, system_memory); 1711 1712 /* load/create device tree */ 1713 if (machine->dtb) { 1714 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1715 if (!machine->fdt) { 1716 error_report("load_device_tree() failed"); 1717 exit(1); 1718 } 1719 } else { 1720 create_fdt(s, memmap); 1721 } 1722 1723 if (virt_is_iommu_sys_enabled(s)) { 1724 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); 1725 1726 object_property_set_uint(OBJECT(iommu_sys), "addr", 1727 s->memmap[VIRT_IOMMU_SYS].base, 1728 &error_fatal); 1729 object_property_set_uint(OBJECT(iommu_sys), "base-irq", 1730 IOMMU_SYS_IRQ, 1731 &error_fatal); 1732 object_property_set_link(OBJECT(iommu_sys), "irqchip", 1733 OBJECT(mmio_irqchip), 1734 &error_fatal); 1735 1736 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); 1737 } 1738 1739 s->machine_done.notify = virt_machine_done; 1740 qemu_add_machine_init_done_notifier(&s->machine_done); 1741 } 1742 1743 static void virt_machine_instance_init(Object *obj) 1744 { 1745 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1746 1747 virt_flash_create(s); 1748 1749 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1750 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1751 s->acpi = ON_OFF_AUTO_AUTO; 1752 s->iommu_sys = ON_OFF_AUTO_AUTO; 1753 } 1754 1755 static char *virt_get_aia_guests(Object *obj, Error **errp) 1756 { 1757 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1758 1759 return g_strdup_printf("%d", s->aia_guests); 1760 } 1761 1762 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1763 { 1764 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1765 1766 s->aia_guests = atoi(val); 1767 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1768 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1769 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1770 VIRT_IRQCHIP_MAX_GUESTS); 1771 } 1772 } 1773 1774 static char *virt_get_aia(Object *obj, Error **errp) 1775 { 1776 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1777 const char *val; 1778 1779 switch (s->aia_type) { 1780 case VIRT_AIA_TYPE_APLIC: 1781 val = "aplic"; 1782 break; 1783 case VIRT_AIA_TYPE_APLIC_IMSIC: 1784 val = "aplic-imsic"; 1785 break; 1786 default: 1787 val = "none"; 1788 break; 1789 }; 1790 1791 return g_strdup(val); 1792 } 1793 1794 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1795 { 1796 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1797 1798 if (!strcmp(val, "none")) { 1799 s->aia_type = VIRT_AIA_TYPE_NONE; 1800 } else if (!strcmp(val, "aplic")) { 1801 s->aia_type = VIRT_AIA_TYPE_APLIC; 1802 } else if (!strcmp(val, "aplic-imsic")) { 1803 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1804 } else { 1805 error_setg(errp, "Invalid AIA interrupt controller type"); 1806 error_append_hint(errp, "Valid values are none, aplic, and " 1807 "aplic-imsic.\n"); 1808 } 1809 } 1810 1811 static bool virt_get_aclint(Object *obj, Error **errp) 1812 { 1813 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1814 1815 return s->have_aclint; 1816 } 1817 1818 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1819 { 1820 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1821 1822 s->have_aclint = value; 1823 } 1824 1825 bool virt_is_iommu_sys_enabled(RISCVVirtState *s) 1826 { 1827 return s->iommu_sys == ON_OFF_AUTO_ON; 1828 } 1829 1830 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, 1831 void *opaque, Error **errp) 1832 { 1833 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1834 OnOffAuto iommu_sys = s->iommu_sys; 1835 1836 visit_type_OnOffAuto(v, name, &iommu_sys, errp); 1837 } 1838 1839 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, 1840 void *opaque, Error **errp) 1841 { 1842 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1843 1844 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); 1845 } 1846 1847 bool virt_is_acpi_enabled(RISCVVirtState *s) 1848 { 1849 return s->acpi != ON_OFF_AUTO_OFF; 1850 } 1851 1852 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1853 void *opaque, Error **errp) 1854 { 1855 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1856 OnOffAuto acpi = s->acpi; 1857 1858 visit_type_OnOffAuto(v, name, &acpi, errp); 1859 } 1860 1861 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1862 void *opaque, Error **errp) 1863 { 1864 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1865 1866 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1867 } 1868 1869 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1870 DeviceState *dev) 1871 { 1872 MachineClass *mc = MACHINE_GET_CLASS(machine); 1873 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1874 1875 if (device_is_dynamic_sysbus(mc, dev) || 1876 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1877 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1878 s->iommu_sys = ON_OFF_AUTO_OFF; 1879 return HOTPLUG_HANDLER(machine); 1880 } 1881 1882 return NULL; 1883 } 1884 1885 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1886 DeviceState *dev, Error **errp) 1887 { 1888 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1889 1890 if (s->platform_bus_dev) { 1891 MachineClass *mc = MACHINE_GET_CLASS(s); 1892 1893 if (device_is_dynamic_sysbus(mc, dev)) { 1894 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1895 SYS_BUS_DEVICE(dev)); 1896 } 1897 } 1898 1899 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1900 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1901 } 1902 1903 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1904 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1905 s->iommu_sys = ON_OFF_AUTO_OFF; 1906 } 1907 } 1908 1909 static void virt_machine_class_init(ObjectClass *oc, const void *data) 1910 { 1911 MachineClass *mc = MACHINE_CLASS(oc); 1912 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1913 1914 mc->desc = "RISC-V VirtIO board"; 1915 mc->init = virt_machine_init; 1916 mc->max_cpus = VIRT_CPUS_MAX; 1917 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1918 mc->block_default_type = IF_VIRTIO; 1919 mc->no_cdrom = 1; 1920 mc->pci_allow_0_address = true; 1921 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1922 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1923 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1924 mc->numa_mem_supported = true; 1925 /* platform instead of architectural choice */ 1926 mc->cpu_cluster_has_numa_boundary = true; 1927 mc->default_ram_id = "riscv_virt_board.ram"; 1928 assert(!mc->get_hotplug_handler); 1929 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1930 1931 hc->plug = virt_machine_device_plug_cb; 1932 1933 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1934 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 1935 #ifdef CONFIG_TPM 1936 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1937 #endif 1938 1939 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1940 virt_set_aclint); 1941 object_class_property_set_description(oc, "aclint", 1942 "(TCG only) Set on/off to " 1943 "enable/disable emulating " 1944 "ACLINT devices"); 1945 1946 object_class_property_add_str(oc, "aia", virt_get_aia, 1947 virt_set_aia); 1948 object_class_property_set_description(oc, "aia", 1949 "Set type of AIA interrupt " 1950 "controller. Valid values are " 1951 "none, aplic, and aplic-imsic."); 1952 1953 object_class_property_add_str(oc, "aia-guests", 1954 virt_get_aia_guests, 1955 virt_set_aia_guests); 1956 { 1957 g_autofree char *str = 1958 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1959 "Valid value should be between 0 and %d.", 1960 VIRT_IRQCHIP_MAX_GUESTS); 1961 object_class_property_set_description(oc, "aia-guests", str); 1962 } 1963 1964 object_class_property_add(oc, "acpi", "OnOffAuto", 1965 virt_get_acpi, virt_set_acpi, 1966 NULL, NULL); 1967 object_class_property_set_description(oc, "acpi", 1968 "Enable ACPI"); 1969 1970 object_class_property_add(oc, "iommu-sys", "OnOffAuto", 1971 virt_get_iommu_sys, virt_set_iommu_sys, 1972 NULL, NULL); 1973 object_class_property_set_description(oc, "iommu-sys", 1974 "Enable IOMMU platform device"); 1975 } 1976 1977 static const TypeInfo virt_machine_typeinfo = { 1978 .name = MACHINE_TYPE_NAME("virt"), 1979 .parent = TYPE_MACHINE, 1980 .class_init = virt_machine_class_init, 1981 .instance_init = virt_machine_instance_init, 1982 .instance_size = sizeof(RISCVVirtState), 1983 .interfaces = (const InterfaceInfo[]) { 1984 { TYPE_HOTPLUG_HANDLER }, 1985 { } 1986 }, 1987 }; 1988 1989 static void virt_machine_init_register_types(void) 1990 { 1991 type_register_static(&virt_machine_typeinfo); 1992 } 1993 1994 type_init(virt_machine_init_register_types) 1995