1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/sifive_clint.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 46 static const MemMapEntry virt_memmap[] = { 47 [VIRT_DEBUG] = { 0x0, 0x100 }, 48 [VIRT_MROM] = { 0x1000, 0xf000 }, 49 [VIRT_TEST] = { 0x100000, 0x1000 }, 50 [VIRT_RTC] = { 0x101000, 0x1000 }, 51 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 52 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 53 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 54 [VIRT_UART0] = { 0x10000000, 0x100 }, 55 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 56 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 57 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 58 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 59 [VIRT_DRAM] = { 0x80000000, 0x0 }, 60 }; 61 62 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 63 64 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 65 const char *name, 66 const char *alias_prop_name) 67 { 68 /* 69 * Create a single flash device. We use the same parameters as 70 * the flash devices on the ARM virt board. 71 */ 72 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 73 74 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 75 qdev_prop_set_uint8(dev, "width", 4); 76 qdev_prop_set_uint8(dev, "device-width", 2); 77 qdev_prop_set_bit(dev, "big-endian", false); 78 qdev_prop_set_uint16(dev, "id0", 0x89); 79 qdev_prop_set_uint16(dev, "id1", 0x18); 80 qdev_prop_set_uint16(dev, "id2", 0x00); 81 qdev_prop_set_uint16(dev, "id3", 0x00); 82 qdev_prop_set_string(dev, "name", name); 83 84 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 85 object_property_add_alias(OBJECT(s), alias_prop_name, 86 OBJECT(dev), "drive"); 87 88 return PFLASH_CFI01(dev); 89 } 90 91 static void virt_flash_create(RISCVVirtState *s) 92 { 93 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 94 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 95 } 96 97 static void virt_flash_map1(PFlashCFI01 *flash, 98 hwaddr base, hwaddr size, 99 MemoryRegion *sysmem) 100 { 101 DeviceState *dev = DEVICE(flash); 102 103 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 104 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 105 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 106 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 107 108 memory_region_add_subregion(sysmem, base, 109 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 110 0)); 111 } 112 113 static void virt_flash_map(RISCVVirtState *s, 114 MemoryRegion *sysmem) 115 { 116 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 117 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 118 119 virt_flash_map1(s->flash[0], flashbase, flashsize, 120 sysmem); 121 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 122 sysmem); 123 } 124 125 static void create_pcie_irq_map(void *fdt, char *nodename, 126 uint32_t plic_phandle) 127 { 128 int pin, dev; 129 uint32_t 130 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 131 uint32_t *irq_map = full_irq_map; 132 133 /* This code creates a standard swizzle of interrupts such that 134 * each device's first interrupt is based on it's PCI_SLOT number. 135 * (See pci_swizzle_map_irq_fn()) 136 * 137 * We only need one entry per interrupt in the table (not one per 138 * possible slot) seeing the interrupt-map-mask will allow the table 139 * to wrap to any number of devices. 140 */ 141 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 142 int devfn = dev * 0x8; 143 144 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 145 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 146 int i = 0; 147 148 irq_map[i] = cpu_to_be32(devfn << 8); 149 150 i += FDT_PCI_ADDR_CELLS; 151 irq_map[i] = cpu_to_be32(pin + 1); 152 153 i += FDT_PCI_INT_CELLS; 154 irq_map[i++] = cpu_to_be32(plic_phandle); 155 156 i += FDT_PLIC_ADDR_CELLS; 157 irq_map[i] = cpu_to_be32(irq_nr); 158 159 irq_map += FDT_INT_MAP_WIDTH; 160 } 161 } 162 163 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 164 full_irq_map, sizeof(full_irq_map)); 165 166 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 167 0x1800, 0, 0, 0x7); 168 } 169 170 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 171 uint64_t mem_size, const char *cmdline, bool is_32_bit) 172 { 173 void *fdt; 174 int i, cpu, socket; 175 MachineState *mc = MACHINE(s); 176 uint64_t addr, size; 177 uint32_t *clint_cells, *plic_cells; 178 unsigned long clint_addr, plic_addr; 179 uint32_t plic_phandle[MAX_NODES]; 180 uint32_t cpu_phandle, intc_phandle, test_phandle; 181 uint32_t phandle = 1, plic_mmio_phandle = 1; 182 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 183 char *mem_name, *cpu_name, *core_name, *intc_name; 184 char *name, *clint_name, *plic_name, *clust_name; 185 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 186 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 187 188 if (mc->dtb) { 189 fdt = s->fdt = load_device_tree(mc->dtb, &s->fdt_size); 190 if (!fdt) { 191 error_report("load_device_tree() failed"); 192 exit(1); 193 } 194 goto update_bootargs; 195 } else { 196 fdt = s->fdt = create_device_tree(&s->fdt_size); 197 if (!fdt) { 198 error_report("create_device_tree() failed"); 199 exit(1); 200 } 201 } 202 203 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 204 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 205 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 206 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 207 208 qemu_fdt_add_subnode(fdt, "/soc"); 209 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 210 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 211 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 212 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 213 214 qemu_fdt_add_subnode(fdt, "/cpus"); 215 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 216 SIFIVE_CLINT_TIMEBASE_FREQ); 217 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 218 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 219 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 220 221 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 222 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 223 qemu_fdt_add_subnode(fdt, clust_name); 224 225 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 226 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 227 228 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 229 cpu_phandle = phandle++; 230 231 cpu_name = g_strdup_printf("/cpus/cpu@%d", 232 s->soc[socket].hartid_base + cpu); 233 qemu_fdt_add_subnode(fdt, cpu_name); 234 if (is_32_bit) { 235 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 236 } else { 237 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 238 } 239 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 240 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 241 g_free(name); 242 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 243 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 244 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 245 s->soc[socket].hartid_base + cpu); 246 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 247 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 248 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 249 250 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 251 qemu_fdt_add_subnode(fdt, intc_name); 252 intc_phandle = phandle++; 253 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 254 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 255 "riscv,cpu-intc"); 256 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 257 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 258 259 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 260 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 261 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 262 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 263 264 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 265 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 266 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 267 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 268 269 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 270 qemu_fdt_add_subnode(fdt, core_name); 271 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 272 273 g_free(core_name); 274 g_free(intc_name); 275 g_free(cpu_name); 276 } 277 278 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 279 size = riscv_socket_mem_size(mc, socket); 280 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 281 qemu_fdt_add_subnode(fdt, mem_name); 282 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 283 addr >> 32, addr, size >> 32, size); 284 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 285 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 286 g_free(mem_name); 287 288 clint_addr = memmap[VIRT_CLINT].base + 289 (memmap[VIRT_CLINT].size * socket); 290 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 291 qemu_fdt_add_subnode(fdt, clint_name); 292 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 293 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 294 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 295 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 296 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 297 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 298 g_free(clint_name); 299 300 plic_phandle[socket] = phandle++; 301 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 302 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 303 qemu_fdt_add_subnode(fdt, plic_name); 304 qemu_fdt_setprop_cell(fdt, plic_name, 305 "#address-cells", FDT_PLIC_ADDR_CELLS); 306 qemu_fdt_setprop_cell(fdt, plic_name, 307 "#interrupt-cells", FDT_PLIC_INT_CELLS); 308 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 309 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 310 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 311 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 312 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 313 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 314 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 315 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 316 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 317 g_free(plic_name); 318 319 g_free(clint_cells); 320 g_free(plic_cells); 321 g_free(clust_name); 322 } 323 324 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 325 if (socket == 0) { 326 plic_mmio_phandle = plic_phandle[socket]; 327 plic_virtio_phandle = plic_phandle[socket]; 328 plic_pcie_phandle = plic_phandle[socket]; 329 } 330 if (socket == 1) { 331 plic_virtio_phandle = plic_phandle[socket]; 332 plic_pcie_phandle = plic_phandle[socket]; 333 } 334 if (socket == 2) { 335 plic_pcie_phandle = plic_phandle[socket]; 336 } 337 } 338 339 riscv_socket_fdt_write_distance_matrix(mc, fdt); 340 341 for (i = 0; i < VIRTIO_COUNT; i++) { 342 name = g_strdup_printf("/soc/virtio_mmio@%lx", 343 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 344 qemu_fdt_add_subnode(fdt, name); 345 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 346 qemu_fdt_setprop_cells(fdt, name, "reg", 347 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 348 0x0, memmap[VIRT_VIRTIO].size); 349 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 350 plic_virtio_phandle); 351 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 352 g_free(name); 353 } 354 355 name = g_strdup_printf("/soc/pci@%lx", 356 (long) memmap[VIRT_PCIE_ECAM].base); 357 qemu_fdt_add_subnode(fdt, name); 358 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 359 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 360 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 361 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 362 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 363 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 364 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 365 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 366 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 367 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 368 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 369 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 370 1, FDT_PCI_RANGE_IOPORT, 2, 0, 371 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 372 1, FDT_PCI_RANGE_MMIO, 373 2, memmap[VIRT_PCIE_MMIO].base, 374 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); 375 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 376 g_free(name); 377 378 test_phandle = phandle++; 379 name = g_strdup_printf("/soc/test@%lx", 380 (long)memmap[VIRT_TEST].base); 381 qemu_fdt_add_subnode(fdt, name); 382 { 383 const char compat[] = "sifive,test1\0sifive,test0\0syscon"; 384 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); 385 } 386 qemu_fdt_setprop_cells(fdt, name, "reg", 387 0x0, memmap[VIRT_TEST].base, 388 0x0, memmap[VIRT_TEST].size); 389 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 390 test_phandle = qemu_fdt_get_phandle(fdt, name); 391 g_free(name); 392 393 name = g_strdup_printf("/soc/reboot"); 394 qemu_fdt_add_subnode(fdt, name); 395 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 396 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 397 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 398 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 399 g_free(name); 400 401 name = g_strdup_printf("/soc/poweroff"); 402 qemu_fdt_add_subnode(fdt, name); 403 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 404 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 405 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 406 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 407 g_free(name); 408 409 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 410 qemu_fdt_add_subnode(fdt, name); 411 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 412 qemu_fdt_setprop_cells(fdt, name, "reg", 413 0x0, memmap[VIRT_UART0].base, 414 0x0, memmap[VIRT_UART0].size); 415 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 416 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 417 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 418 419 qemu_fdt_add_subnode(fdt, "/chosen"); 420 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 421 g_free(name); 422 423 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 424 qemu_fdt_add_subnode(fdt, name); 425 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 426 qemu_fdt_setprop_cells(fdt, name, "reg", 427 0x0, memmap[VIRT_RTC].base, 428 0x0, memmap[VIRT_RTC].size); 429 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 430 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 431 g_free(name); 432 433 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 434 qemu_fdt_add_subnode(s->fdt, name); 435 qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); 436 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 437 2, flashbase, 2, flashsize, 438 2, flashbase + flashsize, 2, flashsize); 439 qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); 440 g_free(name); 441 442 update_bootargs: 443 if (cmdline) { 444 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 445 } 446 } 447 448 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 449 hwaddr ecam_base, hwaddr ecam_size, 450 hwaddr mmio_base, hwaddr mmio_size, 451 hwaddr pio_base, 452 DeviceState *plic) 453 { 454 DeviceState *dev; 455 MemoryRegion *ecam_alias, *ecam_reg; 456 MemoryRegion *mmio_alias, *mmio_reg; 457 qemu_irq irq; 458 int i; 459 460 dev = qdev_new(TYPE_GPEX_HOST); 461 462 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 463 464 ecam_alias = g_new0(MemoryRegion, 1); 465 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 466 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 467 ecam_reg, 0, ecam_size); 468 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 469 470 mmio_alias = g_new0(MemoryRegion, 1); 471 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 472 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 473 mmio_reg, mmio_base, mmio_size); 474 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 475 476 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 477 478 for (i = 0; i < GPEX_NUM_IRQS; i++) { 479 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 480 481 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 482 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 483 } 484 485 return dev; 486 } 487 488 static void virt_machine_init(MachineState *machine) 489 { 490 const MemMapEntry *memmap = virt_memmap; 491 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 492 MemoryRegion *system_memory = get_system_memory(); 493 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 494 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 495 char *plic_hart_config, *soc_name; 496 size_t plic_hart_config_len; 497 target_ulong start_addr = memmap[VIRT_DRAM].base; 498 target_ulong firmware_end_addr, kernel_start_addr; 499 uint32_t fdt_load_addr; 500 uint64_t kernel_entry; 501 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 502 int i, j, base_hartid, hart_count; 503 504 /* Check socket count limit */ 505 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 506 error_report("number of sockets/nodes should be less than %d", 507 VIRT_SOCKETS_MAX); 508 exit(1); 509 } 510 511 /* Initialize sockets */ 512 mmio_plic = virtio_plic = pcie_plic = NULL; 513 for (i = 0; i < riscv_socket_count(machine); i++) { 514 if (!riscv_socket_check_hartids(machine, i)) { 515 error_report("discontinuous hartids in socket%d", i); 516 exit(1); 517 } 518 519 base_hartid = riscv_socket_first_hartid(machine, i); 520 if (base_hartid < 0) { 521 error_report("can't find hartid base for socket%d", i); 522 exit(1); 523 } 524 525 hart_count = riscv_socket_hart_count(machine, i); 526 if (hart_count < 0) { 527 error_report("can't find hart count for socket%d", i); 528 exit(1); 529 } 530 531 soc_name = g_strdup_printf("soc%d", i); 532 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 533 TYPE_RISCV_HART_ARRAY); 534 g_free(soc_name); 535 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 536 machine->cpu_type, &error_abort); 537 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 538 base_hartid, &error_abort); 539 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 540 hart_count, &error_abort); 541 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 542 543 /* Per-socket CLINT */ 544 sifive_clint_create( 545 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 546 memmap[VIRT_CLINT].size, base_hartid, hart_count, 547 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 548 SIFIVE_CLINT_TIMEBASE_FREQ, true); 549 550 /* Per-socket PLIC hart topology configuration string */ 551 plic_hart_config_len = 552 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 553 plic_hart_config = g_malloc0(plic_hart_config_len); 554 for (j = 0; j < hart_count; j++) { 555 if (j != 0) { 556 strncat(plic_hart_config, ",", plic_hart_config_len); 557 } 558 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 559 plic_hart_config_len); 560 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 561 } 562 563 /* Per-socket PLIC */ 564 s->plic[i] = sifive_plic_create( 565 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 566 plic_hart_config, base_hartid, 567 VIRT_PLIC_NUM_SOURCES, 568 VIRT_PLIC_NUM_PRIORITIES, 569 VIRT_PLIC_PRIORITY_BASE, 570 VIRT_PLIC_PENDING_BASE, 571 VIRT_PLIC_ENABLE_BASE, 572 VIRT_PLIC_ENABLE_STRIDE, 573 VIRT_PLIC_CONTEXT_BASE, 574 VIRT_PLIC_CONTEXT_STRIDE, 575 memmap[VIRT_PLIC].size); 576 g_free(plic_hart_config); 577 578 /* Try to use different PLIC instance based device type */ 579 if (i == 0) { 580 mmio_plic = s->plic[i]; 581 virtio_plic = s->plic[i]; 582 pcie_plic = s->plic[i]; 583 } 584 if (i == 1) { 585 virtio_plic = s->plic[i]; 586 pcie_plic = s->plic[i]; 587 } 588 if (i == 2) { 589 pcie_plic = s->plic[i]; 590 } 591 } 592 593 if (riscv_is_32bit(&s->soc[0])) { 594 #if HOST_LONG_BITS == 64 595 /* limit RAM size in a 32-bit system */ 596 if (machine->ram_size > 10 * GiB) { 597 machine->ram_size = 10 * GiB; 598 error_report("Limiting RAM size to 10 GiB"); 599 } 600 #endif 601 } 602 603 /* register system main memory (actual RAM) */ 604 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 605 machine->ram_size, &error_fatal); 606 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 607 main_mem); 608 609 /* create device tree */ 610 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 611 riscv_is_32bit(&s->soc[0])); 612 613 /* boot rom */ 614 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 615 memmap[VIRT_MROM].size, &error_fatal); 616 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 617 mask_rom); 618 619 if (riscv_is_32bit(&s->soc[0])) { 620 firmware_end_addr = riscv_find_and_load_firmware(machine, 621 "opensbi-riscv32-generic-fw_dynamic.bin", 622 start_addr, NULL); 623 } else { 624 firmware_end_addr = riscv_find_and_load_firmware(machine, 625 "opensbi-riscv64-generic-fw_dynamic.bin", 626 start_addr, NULL); 627 } 628 629 if (machine->kernel_filename) { 630 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 631 firmware_end_addr); 632 633 kernel_entry = riscv_load_kernel(machine->kernel_filename, 634 kernel_start_addr, NULL); 635 636 if (machine->initrd_filename) { 637 hwaddr start; 638 hwaddr end = riscv_load_initrd(machine->initrd_filename, 639 machine->ram_size, kernel_entry, 640 &start); 641 qemu_fdt_setprop_cell(s->fdt, "/chosen", 642 "linux,initrd-start", start); 643 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 644 end); 645 } 646 } else { 647 /* 648 * If dynamic firmware is used, it doesn't know where is the next mode 649 * if kernel argument is not set. 650 */ 651 kernel_entry = 0; 652 } 653 654 if (drive_get(IF_PFLASH, 0, 0)) { 655 /* 656 * Pflash was supplied, let's overwrite the address we jump to after 657 * reset to the base of the flash. 658 */ 659 start_addr = virt_memmap[VIRT_FLASH].base; 660 } 661 662 /* Compute the fdt load address in dram */ 663 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 664 machine->ram_size, s->fdt); 665 /* load the reset vector */ 666 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 667 virt_memmap[VIRT_MROM].base, 668 virt_memmap[VIRT_MROM].size, kernel_entry, 669 fdt_load_addr, s->fdt); 670 671 /* SiFive Test MMIO device */ 672 sifive_test_create(memmap[VIRT_TEST].base); 673 674 /* VirtIO MMIO devices */ 675 for (i = 0; i < VIRTIO_COUNT; i++) { 676 sysbus_create_simple("virtio-mmio", 677 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 678 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 679 } 680 681 gpex_pcie_init(system_memory, 682 memmap[VIRT_PCIE_ECAM].base, 683 memmap[VIRT_PCIE_ECAM].size, 684 memmap[VIRT_PCIE_MMIO].base, 685 memmap[VIRT_PCIE_MMIO].size, 686 memmap[VIRT_PCIE_PIO].base, 687 DEVICE(pcie_plic)); 688 689 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 690 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 691 serial_hd(0), DEVICE_LITTLE_ENDIAN); 692 693 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 694 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 695 696 virt_flash_create(s); 697 698 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 699 /* Map legacy -drive if=pflash to machine properties */ 700 pflash_cfi01_legacy_drive(s->flash[i], 701 drive_get(IF_PFLASH, 0, i)); 702 } 703 virt_flash_map(s, system_memory); 704 } 705 706 static void virt_machine_instance_init(Object *obj) 707 { 708 } 709 710 static void virt_machine_class_init(ObjectClass *oc, void *data) 711 { 712 MachineClass *mc = MACHINE_CLASS(oc); 713 714 mc->desc = "RISC-V VirtIO board"; 715 mc->init = virt_machine_init; 716 mc->max_cpus = VIRT_CPUS_MAX; 717 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 718 mc->pci_allow_0_address = true; 719 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 720 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 721 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 722 mc->numa_mem_supported = true; 723 } 724 725 static const TypeInfo virt_machine_typeinfo = { 726 .name = MACHINE_TYPE_NAME("virt"), 727 .parent = TYPE_MACHINE, 728 .class_init = virt_machine_class_init, 729 .instance_init = virt_machine_instance_init, 730 .instance_size = sizeof(RISCVVirtState), 731 }; 732 733 static void virt_machine_init_register_types(void) 734 { 735 type_register_static(&virt_machine_typeinfo); 736 } 737 738 type_init(virt_machine_init_register_types) 739