1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/riscv_aclint.h" 36 #include "hw/intc/riscv_aplic.h" 37 #include "hw/intc/riscv_imsic.h" 38 #include "hw/intc/sifive_plic.h" 39 #include "hw/misc/sifive_test.h" 40 #include "chardev/char.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/pci/pci.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/display/ramfb.h" 47 48 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 49 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 50 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 51 #error "Can't accomodate single IMSIC group in address space" 52 #endif 53 54 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 55 VIRT_IMSIC_GROUP_MAX_SIZE) 56 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 57 #error "Can't accomodate all IMSIC groups in address space" 58 #endif 59 60 static const MemMapEntry virt_memmap[] = { 61 [VIRT_DEBUG] = { 0x0, 0x100 }, 62 [VIRT_MROM] = { 0x1000, 0xf000 }, 63 [VIRT_TEST] = { 0x100000, 0x1000 }, 64 [VIRT_RTC] = { 0x101000, 0x1000 }, 65 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 66 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 67 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 68 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 69 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 70 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 71 [VIRT_UART0] = { 0x10000000, 0x100 }, 72 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 73 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 74 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 75 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 76 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 77 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 78 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 79 [VIRT_DRAM] = { 0x80000000, 0x0 }, 80 }; 81 82 /* PCIe high mmio is fixed for RV32 */ 83 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 84 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 85 86 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 87 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 88 89 static MemMapEntry virt_high_pcie_memmap; 90 91 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 92 93 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 94 const char *name, 95 const char *alias_prop_name) 96 { 97 /* 98 * Create a single flash device. We use the same parameters as 99 * the flash devices on the ARM virt board. 100 */ 101 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 102 103 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 104 qdev_prop_set_uint8(dev, "width", 4); 105 qdev_prop_set_uint8(dev, "device-width", 2); 106 qdev_prop_set_bit(dev, "big-endian", false); 107 qdev_prop_set_uint16(dev, "id0", 0x89); 108 qdev_prop_set_uint16(dev, "id1", 0x18); 109 qdev_prop_set_uint16(dev, "id2", 0x00); 110 qdev_prop_set_uint16(dev, "id3", 0x00); 111 qdev_prop_set_string(dev, "name", name); 112 113 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 114 object_property_add_alias(OBJECT(s), alias_prop_name, 115 OBJECT(dev), "drive"); 116 117 return PFLASH_CFI01(dev); 118 } 119 120 static void virt_flash_create(RISCVVirtState *s) 121 { 122 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 123 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 124 } 125 126 static void virt_flash_map1(PFlashCFI01 *flash, 127 hwaddr base, hwaddr size, 128 MemoryRegion *sysmem) 129 { 130 DeviceState *dev = DEVICE(flash); 131 132 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 133 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 134 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 135 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 136 137 memory_region_add_subregion(sysmem, base, 138 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 139 0)); 140 } 141 142 static void virt_flash_map(RISCVVirtState *s, 143 MemoryRegion *sysmem) 144 { 145 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 146 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 147 148 virt_flash_map1(s->flash[0], flashbase, flashsize, 149 sysmem); 150 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 151 sysmem); 152 } 153 154 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 155 uint32_t irqchip_phandle) 156 { 157 int pin, dev; 158 uint32_t irq_map_stride = 0; 159 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 160 FDT_MAX_INT_MAP_WIDTH] = {}; 161 uint32_t *irq_map = full_irq_map; 162 163 /* This code creates a standard swizzle of interrupts such that 164 * each device's first interrupt is based on it's PCI_SLOT number. 165 * (See pci_swizzle_map_irq_fn()) 166 * 167 * We only need one entry per interrupt in the table (not one per 168 * possible slot) seeing the interrupt-map-mask will allow the table 169 * to wrap to any number of devices. 170 */ 171 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 172 int devfn = dev * 0x8; 173 174 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 175 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 176 int i = 0; 177 178 /* Fill PCI address cells */ 179 irq_map[i] = cpu_to_be32(devfn << 8); 180 i += FDT_PCI_ADDR_CELLS; 181 182 /* Fill PCI Interrupt cells */ 183 irq_map[i] = cpu_to_be32(pin + 1); 184 i += FDT_PCI_INT_CELLS; 185 186 /* Fill interrupt controller phandle and cells */ 187 irq_map[i++] = cpu_to_be32(irqchip_phandle); 188 irq_map[i++] = cpu_to_be32(irq_nr); 189 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 190 irq_map[i++] = cpu_to_be32(0x4); 191 } 192 193 if (!irq_map_stride) { 194 irq_map_stride = i; 195 } 196 irq_map += irq_map_stride; 197 } 198 } 199 200 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 201 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 202 irq_map_stride * sizeof(uint32_t)); 203 204 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 205 0x1800, 0, 0, 0x7); 206 } 207 208 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 209 char *clust_name, uint32_t *phandle, 210 bool is_32_bit, uint32_t *intc_phandles) 211 { 212 int cpu; 213 uint32_t cpu_phandle; 214 MachineState *mc = MACHINE(s); 215 char *name, *cpu_name, *core_name, *intc_name; 216 217 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 218 cpu_phandle = (*phandle)++; 219 220 cpu_name = g_strdup_printf("/cpus/cpu@%d", 221 s->soc[socket].hartid_base + cpu); 222 qemu_fdt_add_subnode(mc->fdt, cpu_name); 223 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 224 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 225 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 226 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 227 g_free(name); 228 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 229 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 230 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 231 s->soc[socket].hartid_base + cpu); 232 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 233 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 234 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 235 236 intc_phandles[cpu] = (*phandle)++; 237 238 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 239 qemu_fdt_add_subnode(mc->fdt, intc_name); 240 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 241 intc_phandles[cpu]); 242 if (riscv_feature(&s->soc[socket].harts[cpu].env, 243 RISCV_FEATURE_AIA)) { 244 static const char * const compat[2] = { 245 "riscv,cpu-intc-aia", "riscv,cpu-intc" 246 }; 247 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 248 (char **)&compat, ARRAY_SIZE(compat)); 249 } else { 250 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 251 "riscv,cpu-intc"); 252 } 253 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 254 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 255 256 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 257 qemu_fdt_add_subnode(mc->fdt, core_name); 258 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 259 260 g_free(core_name); 261 g_free(intc_name); 262 g_free(cpu_name); 263 } 264 } 265 266 static void create_fdt_socket_memory(RISCVVirtState *s, 267 const MemMapEntry *memmap, int socket) 268 { 269 char *mem_name; 270 uint64_t addr, size; 271 MachineState *mc = MACHINE(s); 272 273 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 274 size = riscv_socket_mem_size(mc, socket); 275 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 276 qemu_fdt_add_subnode(mc->fdt, mem_name); 277 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 278 addr >> 32, addr, size >> 32, size); 279 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 280 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 281 g_free(mem_name); 282 } 283 284 static void create_fdt_socket_clint(RISCVVirtState *s, 285 const MemMapEntry *memmap, int socket, 286 uint32_t *intc_phandles) 287 { 288 int cpu; 289 char *clint_name; 290 uint32_t *clint_cells; 291 unsigned long clint_addr; 292 MachineState *mc = MACHINE(s); 293 static const char * const clint_compat[2] = { 294 "sifive,clint0", "riscv,clint0" 295 }; 296 297 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 298 299 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 300 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 301 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 302 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 303 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 304 } 305 306 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 307 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 308 qemu_fdt_add_subnode(mc->fdt, clint_name); 309 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 310 (char **)&clint_compat, 311 ARRAY_SIZE(clint_compat)); 312 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 313 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 314 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 315 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 316 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 317 g_free(clint_name); 318 319 g_free(clint_cells); 320 } 321 322 static void create_fdt_socket_aclint(RISCVVirtState *s, 323 const MemMapEntry *memmap, int socket, 324 uint32_t *intc_phandles) 325 { 326 int cpu; 327 char *name; 328 unsigned long addr, size; 329 uint32_t aclint_cells_size; 330 uint32_t *aclint_mswi_cells; 331 uint32_t *aclint_sswi_cells; 332 uint32_t *aclint_mtimer_cells; 333 MachineState *mc = MACHINE(s); 334 335 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 336 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 337 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 338 339 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 340 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 341 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 342 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 343 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 344 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 345 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 346 } 347 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 348 349 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 350 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 351 name = g_strdup_printf("/soc/mswi@%lx", addr); 352 qemu_fdt_add_subnode(mc->fdt, name); 353 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 354 "riscv,aclint-mswi"); 355 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 356 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 357 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 358 aclint_mswi_cells, aclint_cells_size); 359 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 360 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 361 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 362 g_free(name); 363 } 364 365 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 366 addr = memmap[VIRT_CLINT].base + 367 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 368 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 369 } else { 370 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 371 (memmap[VIRT_CLINT].size * socket); 372 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 373 } 374 name = g_strdup_printf("/soc/mtimer@%lx", addr); 375 qemu_fdt_add_subnode(mc->fdt, name); 376 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 377 "riscv,aclint-mtimer"); 378 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 379 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 380 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 381 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 382 0x0, RISCV_ACLINT_DEFAULT_MTIME); 383 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 384 aclint_mtimer_cells, aclint_cells_size); 385 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 386 g_free(name); 387 388 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 389 addr = memmap[VIRT_ACLINT_SSWI].base + 390 (memmap[VIRT_ACLINT_SSWI].size * socket); 391 name = g_strdup_printf("/soc/sswi@%lx", addr); 392 qemu_fdt_add_subnode(mc->fdt, name); 393 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 394 "riscv,aclint-sswi"); 395 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 396 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 397 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 398 aclint_sswi_cells, aclint_cells_size); 399 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 400 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 401 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 402 g_free(name); 403 } 404 405 g_free(aclint_mswi_cells); 406 g_free(aclint_mtimer_cells); 407 g_free(aclint_sswi_cells); 408 } 409 410 static void create_fdt_socket_plic(RISCVVirtState *s, 411 const MemMapEntry *memmap, int socket, 412 uint32_t *phandle, uint32_t *intc_phandles, 413 uint32_t *plic_phandles) 414 { 415 int cpu; 416 char *plic_name; 417 uint32_t *plic_cells; 418 unsigned long plic_addr; 419 MachineState *mc = MACHINE(s); 420 static const char * const plic_compat[2] = { 421 "sifive,plic-1.0.0", "riscv,plic0" 422 }; 423 424 if (kvm_enabled()) { 425 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 426 } else { 427 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 428 } 429 430 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 431 if (kvm_enabled()) { 432 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 433 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 434 } else { 435 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 436 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 437 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 438 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 439 } 440 } 441 442 plic_phandles[socket] = (*phandle)++; 443 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 444 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 445 qemu_fdt_add_subnode(mc->fdt, plic_name); 446 qemu_fdt_setprop_cell(mc->fdt, plic_name, 447 "#interrupt-cells", FDT_PLIC_INT_CELLS); 448 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 449 (char **)&plic_compat, 450 ARRAY_SIZE(plic_compat)); 451 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 452 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 453 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 454 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 455 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 456 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 457 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 458 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 459 plic_phandles[socket]); 460 g_free(plic_name); 461 462 g_free(plic_cells); 463 } 464 465 static uint32_t imsic_num_bits(uint32_t count) 466 { 467 uint32_t ret = 0; 468 469 while (BIT(ret) < count) { 470 ret++; 471 } 472 473 return ret; 474 } 475 476 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 477 uint32_t *phandle, uint32_t *intc_phandles, 478 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 479 { 480 int cpu, socket; 481 char *imsic_name; 482 MachineState *mc = MACHINE(s); 483 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 484 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 485 486 *msi_m_phandle = (*phandle)++; 487 *msi_s_phandle = (*phandle)++; 488 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 489 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 490 491 /* M-level IMSIC node */ 492 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 493 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 494 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 495 } 496 imsic_max_hart_per_socket = 0; 497 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 498 imsic_addr = memmap[VIRT_IMSIC_M].base + 499 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 500 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 501 imsic_regs[socket * 4 + 0] = 0; 502 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 503 imsic_regs[socket * 4 + 2] = 0; 504 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 505 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 506 imsic_max_hart_per_socket = s->soc[socket].num_harts; 507 } 508 } 509 imsic_name = g_strdup_printf("/soc/imsics@%lx", 510 (unsigned long)memmap[VIRT_IMSIC_M].base); 511 qemu_fdt_add_subnode(mc->fdt, imsic_name); 512 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 513 "riscv,imsics"); 514 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 515 FDT_IMSIC_INT_CELLS); 516 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 517 NULL, 0); 518 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 519 NULL, 0); 520 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 521 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 522 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 523 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 524 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 525 VIRT_IRQCHIP_NUM_MSIS); 526 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 527 VIRT_IRQCHIP_IPI_MSI); 528 if (riscv_socket_count(mc) > 1) { 529 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 530 imsic_num_bits(imsic_max_hart_per_socket)); 531 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 532 imsic_num_bits(riscv_socket_count(mc))); 533 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 534 IMSIC_MMIO_GROUP_MIN_SHIFT); 535 } 536 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 537 g_free(imsic_name); 538 539 /* S-level IMSIC node */ 540 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 541 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 542 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 543 } 544 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 545 imsic_max_hart_per_socket = 0; 546 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 547 imsic_addr = memmap[VIRT_IMSIC_S].base + 548 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 549 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 550 s->soc[socket].num_harts; 551 imsic_regs[socket * 4 + 0] = 0; 552 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 553 imsic_regs[socket * 4 + 2] = 0; 554 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 555 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 556 imsic_max_hart_per_socket = s->soc[socket].num_harts; 557 } 558 } 559 imsic_name = g_strdup_printf("/soc/imsics@%lx", 560 (unsigned long)memmap[VIRT_IMSIC_S].base); 561 qemu_fdt_add_subnode(mc->fdt, imsic_name); 562 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 563 "riscv,imsics"); 564 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 565 FDT_IMSIC_INT_CELLS); 566 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 567 NULL, 0); 568 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 569 NULL, 0); 570 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 571 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 572 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 573 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 574 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 575 VIRT_IRQCHIP_NUM_MSIS); 576 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 577 VIRT_IRQCHIP_IPI_MSI); 578 if (imsic_guest_bits) { 579 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 580 imsic_guest_bits); 581 } 582 if (riscv_socket_count(mc) > 1) { 583 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 584 imsic_num_bits(imsic_max_hart_per_socket)); 585 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 586 imsic_num_bits(riscv_socket_count(mc))); 587 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 588 IMSIC_MMIO_GROUP_MIN_SHIFT); 589 } 590 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 591 g_free(imsic_name); 592 593 g_free(imsic_regs); 594 g_free(imsic_cells); 595 } 596 597 static void create_fdt_socket_aplic(RISCVVirtState *s, 598 const MemMapEntry *memmap, int socket, 599 uint32_t msi_m_phandle, 600 uint32_t msi_s_phandle, 601 uint32_t *phandle, 602 uint32_t *intc_phandles, 603 uint32_t *aplic_phandles) 604 { 605 int cpu; 606 char *aplic_name; 607 uint32_t *aplic_cells; 608 unsigned long aplic_addr; 609 MachineState *mc = MACHINE(s); 610 uint32_t aplic_m_phandle, aplic_s_phandle; 611 612 aplic_m_phandle = (*phandle)++; 613 aplic_s_phandle = (*phandle)++; 614 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 615 616 /* M-level APLIC node */ 617 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 618 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 619 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 620 } 621 aplic_addr = memmap[VIRT_APLIC_M].base + 622 (memmap[VIRT_APLIC_M].size * socket); 623 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 624 qemu_fdt_add_subnode(mc->fdt, aplic_name); 625 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 626 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 627 "#interrupt-cells", FDT_APLIC_INT_CELLS); 628 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 629 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 630 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 631 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 632 } else { 633 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 634 msi_m_phandle); 635 } 636 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 637 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 638 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 639 VIRT_IRQCHIP_NUM_SOURCES); 640 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 641 aplic_s_phandle); 642 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 643 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 644 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 645 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 646 g_free(aplic_name); 647 648 /* S-level APLIC node */ 649 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 650 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 651 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 652 } 653 aplic_addr = memmap[VIRT_APLIC_S].base + 654 (memmap[VIRT_APLIC_S].size * socket); 655 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 656 qemu_fdt_add_subnode(mc->fdt, aplic_name); 657 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 658 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 659 "#interrupt-cells", FDT_APLIC_INT_CELLS); 660 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 661 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 662 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 663 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 664 } else { 665 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 666 msi_s_phandle); 667 } 668 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 669 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 670 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 671 VIRT_IRQCHIP_NUM_SOURCES); 672 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 673 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 674 g_free(aplic_name); 675 676 g_free(aplic_cells); 677 aplic_phandles[socket] = aplic_s_phandle; 678 } 679 680 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 681 bool is_32_bit, uint32_t *phandle, 682 uint32_t *irq_mmio_phandle, 683 uint32_t *irq_pcie_phandle, 684 uint32_t *irq_virtio_phandle, 685 uint32_t *msi_pcie_phandle) 686 { 687 char *clust_name; 688 int socket, phandle_pos; 689 MachineState *mc = MACHINE(s); 690 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 691 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 692 693 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 694 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 695 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 696 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 697 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 698 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 699 700 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 701 702 phandle_pos = mc->smp.cpus; 703 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 704 phandle_pos -= s->soc[socket].num_harts; 705 706 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 707 qemu_fdt_add_subnode(mc->fdt, clust_name); 708 709 create_fdt_socket_cpus(s, socket, clust_name, phandle, 710 is_32_bit, &intc_phandles[phandle_pos]); 711 712 create_fdt_socket_memory(s, memmap, socket); 713 714 g_free(clust_name); 715 716 if (!kvm_enabled()) { 717 if (s->have_aclint) { 718 create_fdt_socket_aclint(s, memmap, socket, 719 &intc_phandles[phandle_pos]); 720 } else { 721 create_fdt_socket_clint(s, memmap, socket, 722 &intc_phandles[phandle_pos]); 723 } 724 } 725 } 726 727 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 728 create_fdt_imsic(s, memmap, phandle, intc_phandles, 729 &msi_m_phandle, &msi_s_phandle); 730 *msi_pcie_phandle = msi_s_phandle; 731 } 732 733 phandle_pos = mc->smp.cpus; 734 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 735 phandle_pos -= s->soc[socket].num_harts; 736 737 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 738 create_fdt_socket_plic(s, memmap, socket, phandle, 739 &intc_phandles[phandle_pos], xplic_phandles); 740 } else { 741 create_fdt_socket_aplic(s, memmap, socket, 742 msi_m_phandle, msi_s_phandle, phandle, 743 &intc_phandles[phandle_pos], xplic_phandles); 744 } 745 } 746 747 g_free(intc_phandles); 748 749 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 750 if (socket == 0) { 751 *irq_mmio_phandle = xplic_phandles[socket]; 752 *irq_virtio_phandle = xplic_phandles[socket]; 753 *irq_pcie_phandle = xplic_phandles[socket]; 754 } 755 if (socket == 1) { 756 *irq_virtio_phandle = xplic_phandles[socket]; 757 *irq_pcie_phandle = xplic_phandles[socket]; 758 } 759 if (socket == 2) { 760 *irq_pcie_phandle = xplic_phandles[socket]; 761 } 762 } 763 764 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 765 } 766 767 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 768 uint32_t irq_virtio_phandle) 769 { 770 int i; 771 char *name; 772 MachineState *mc = MACHINE(s); 773 774 for (i = 0; i < VIRTIO_COUNT; i++) { 775 name = g_strdup_printf("/soc/virtio_mmio@%lx", 776 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 777 qemu_fdt_add_subnode(mc->fdt, name); 778 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 779 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 780 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 781 0x0, memmap[VIRT_VIRTIO].size); 782 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 783 irq_virtio_phandle); 784 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 785 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 786 VIRTIO_IRQ + i); 787 } else { 788 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 789 VIRTIO_IRQ + i, 0x4); 790 } 791 g_free(name); 792 } 793 } 794 795 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 796 uint32_t irq_pcie_phandle, 797 uint32_t msi_pcie_phandle) 798 { 799 char *name; 800 MachineState *mc = MACHINE(s); 801 802 name = g_strdup_printf("/soc/pci@%lx", 803 (long) memmap[VIRT_PCIE_ECAM].base); 804 qemu_fdt_add_subnode(mc->fdt, name); 805 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 806 FDT_PCI_ADDR_CELLS); 807 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 808 FDT_PCI_INT_CELLS); 809 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 810 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 811 "pci-host-ecam-generic"); 812 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 813 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 814 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 815 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 816 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 817 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 818 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 819 } 820 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 821 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 822 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 823 1, FDT_PCI_RANGE_IOPORT, 2, 0, 824 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 825 1, FDT_PCI_RANGE_MMIO, 826 2, memmap[VIRT_PCIE_MMIO].base, 827 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 828 1, FDT_PCI_RANGE_MMIO_64BIT, 829 2, virt_high_pcie_memmap.base, 830 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 831 832 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 833 g_free(name); 834 } 835 836 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 837 uint32_t *phandle) 838 { 839 char *name; 840 uint32_t test_phandle; 841 MachineState *mc = MACHINE(s); 842 843 test_phandle = (*phandle)++; 844 name = g_strdup_printf("/soc/test@%lx", 845 (long)memmap[VIRT_TEST].base); 846 qemu_fdt_add_subnode(mc->fdt, name); 847 { 848 static const char * const compat[3] = { 849 "sifive,test1", "sifive,test0", "syscon" 850 }; 851 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 852 (char **)&compat, ARRAY_SIZE(compat)); 853 } 854 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 855 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 856 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 857 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 858 g_free(name); 859 860 name = g_strdup_printf("/soc/reboot"); 861 qemu_fdt_add_subnode(mc->fdt, name); 862 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 863 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 864 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 865 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 866 g_free(name); 867 868 name = g_strdup_printf("/soc/poweroff"); 869 qemu_fdt_add_subnode(mc->fdt, name); 870 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 871 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 872 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 873 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 874 g_free(name); 875 } 876 877 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 878 uint32_t irq_mmio_phandle) 879 { 880 char *name; 881 MachineState *mc = MACHINE(s); 882 883 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 884 qemu_fdt_add_subnode(mc->fdt, name); 885 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 886 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 887 0x0, memmap[VIRT_UART0].base, 888 0x0, memmap[VIRT_UART0].size); 889 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 890 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 891 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 892 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 893 } else { 894 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 895 } 896 897 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 898 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 899 g_free(name); 900 } 901 902 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 903 uint32_t irq_mmio_phandle) 904 { 905 char *name; 906 MachineState *mc = MACHINE(s); 907 908 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 909 qemu_fdt_add_subnode(mc->fdt, name); 910 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 911 "google,goldfish-rtc"); 912 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 913 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 914 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 915 irq_mmio_phandle); 916 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 917 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 918 } else { 919 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 920 } 921 g_free(name); 922 } 923 924 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 925 { 926 char *name; 927 MachineState *mc = MACHINE(s); 928 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 929 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 930 931 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 932 qemu_fdt_add_subnode(mc->fdt, name); 933 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 934 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 935 2, flashbase, 2, flashsize, 936 2, flashbase + flashsize, 2, flashsize); 937 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 938 g_free(name); 939 } 940 941 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 942 uint64_t mem_size, const char *cmdline, bool is_32_bit) 943 { 944 MachineState *mc = MACHINE(s); 945 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 946 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 947 948 if (mc->dtb) { 949 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 950 if (!mc->fdt) { 951 error_report("load_device_tree() failed"); 952 exit(1); 953 } 954 goto update_bootargs; 955 } else { 956 mc->fdt = create_device_tree(&s->fdt_size); 957 if (!mc->fdt) { 958 error_report("create_device_tree() failed"); 959 exit(1); 960 } 961 } 962 963 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 964 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 965 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 966 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 967 968 qemu_fdt_add_subnode(mc->fdt, "/soc"); 969 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 970 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 971 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 972 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 973 974 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 975 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 976 &msi_pcie_phandle); 977 978 create_fdt_virtio(s, memmap, irq_virtio_phandle); 979 980 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 981 982 create_fdt_reset(s, memmap, &phandle); 983 984 create_fdt_uart(s, memmap, irq_mmio_phandle); 985 986 create_fdt_rtc(s, memmap, irq_mmio_phandle); 987 988 create_fdt_flash(s, memmap); 989 990 update_bootargs: 991 if (cmdline) { 992 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 993 } 994 } 995 996 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 997 hwaddr ecam_base, hwaddr ecam_size, 998 hwaddr mmio_base, hwaddr mmio_size, 999 hwaddr high_mmio_base, 1000 hwaddr high_mmio_size, 1001 hwaddr pio_base, 1002 DeviceState *irqchip) 1003 { 1004 DeviceState *dev; 1005 MemoryRegion *ecam_alias, *ecam_reg; 1006 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1007 qemu_irq irq; 1008 int i; 1009 1010 dev = qdev_new(TYPE_GPEX_HOST); 1011 1012 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1013 1014 ecam_alias = g_new0(MemoryRegion, 1); 1015 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1016 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1017 ecam_reg, 0, ecam_size); 1018 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1019 1020 mmio_alias = g_new0(MemoryRegion, 1); 1021 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1022 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1023 mmio_reg, mmio_base, mmio_size); 1024 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1025 1026 /* Map high MMIO space */ 1027 high_mmio_alias = g_new0(MemoryRegion, 1); 1028 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1029 mmio_reg, high_mmio_base, high_mmio_size); 1030 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1031 high_mmio_alias); 1032 1033 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1034 1035 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1036 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1037 1038 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1039 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1040 } 1041 1042 return dev; 1043 } 1044 1045 static FWCfgState *create_fw_cfg(const MachineState *mc) 1046 { 1047 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1048 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 1049 FWCfgState *fw_cfg; 1050 char *nodename; 1051 1052 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1053 &address_space_memory); 1054 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1055 1056 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1057 qemu_fdt_add_subnode(mc->fdt, nodename); 1058 qemu_fdt_setprop_string(mc->fdt, nodename, 1059 "compatible", "qemu,fw-cfg-mmio"); 1060 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 1061 2, base, 2, size); 1062 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 1063 g_free(nodename); 1064 return fw_cfg; 1065 } 1066 1067 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1068 int base_hartid, int hart_count) 1069 { 1070 DeviceState *ret; 1071 char *plic_hart_config; 1072 1073 /* Per-socket PLIC hart topology configuration string */ 1074 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1075 1076 /* Per-socket PLIC */ 1077 ret = sifive_plic_create( 1078 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1079 plic_hart_config, hart_count, base_hartid, 1080 VIRT_IRQCHIP_NUM_SOURCES, 1081 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1082 VIRT_PLIC_PRIORITY_BASE, 1083 VIRT_PLIC_PENDING_BASE, 1084 VIRT_PLIC_ENABLE_BASE, 1085 VIRT_PLIC_ENABLE_STRIDE, 1086 VIRT_PLIC_CONTEXT_BASE, 1087 VIRT_PLIC_CONTEXT_STRIDE, 1088 memmap[VIRT_PLIC].size); 1089 1090 g_free(plic_hart_config); 1091 1092 return ret; 1093 } 1094 1095 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1096 const MemMapEntry *memmap, int socket, 1097 int base_hartid, int hart_count) 1098 { 1099 int i; 1100 hwaddr addr; 1101 uint32_t guest_bits; 1102 DeviceState *aplic_m; 1103 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1104 1105 if (msimode) { 1106 /* Per-socket M-level IMSICs */ 1107 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1108 for (i = 0; i < hart_count; i++) { 1109 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1110 base_hartid + i, true, 1, 1111 VIRT_IRQCHIP_NUM_MSIS); 1112 } 1113 1114 /* Per-socket S-level IMSICs */ 1115 guest_bits = imsic_num_bits(aia_guests + 1); 1116 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1117 for (i = 0; i < hart_count; i++) { 1118 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1119 base_hartid + i, false, 1 + aia_guests, 1120 VIRT_IRQCHIP_NUM_MSIS); 1121 } 1122 } 1123 1124 /* Per-socket M-level APLIC */ 1125 aplic_m = riscv_aplic_create( 1126 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1127 memmap[VIRT_APLIC_M].size, 1128 (msimode) ? 0 : base_hartid, 1129 (msimode) ? 0 : hart_count, 1130 VIRT_IRQCHIP_NUM_SOURCES, 1131 VIRT_IRQCHIP_NUM_PRIO_BITS, 1132 msimode, true, NULL); 1133 1134 if (aplic_m) { 1135 /* Per-socket S-level APLIC */ 1136 riscv_aplic_create( 1137 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1138 memmap[VIRT_APLIC_S].size, 1139 (msimode) ? 0 : base_hartid, 1140 (msimode) ? 0 : hart_count, 1141 VIRT_IRQCHIP_NUM_SOURCES, 1142 VIRT_IRQCHIP_NUM_PRIO_BITS, 1143 msimode, false, aplic_m); 1144 } 1145 1146 return aplic_m; 1147 } 1148 1149 static void virt_machine_init(MachineState *machine) 1150 { 1151 const MemMapEntry *memmap = virt_memmap; 1152 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1153 MemoryRegion *system_memory = get_system_memory(); 1154 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1155 char *soc_name; 1156 target_ulong start_addr = memmap[VIRT_DRAM].base; 1157 target_ulong firmware_end_addr, kernel_start_addr; 1158 uint32_t fdt_load_addr; 1159 uint64_t kernel_entry; 1160 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1161 int i, base_hartid, hart_count; 1162 1163 /* Check socket count limit */ 1164 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1165 error_report("number of sockets/nodes should be less than %d", 1166 VIRT_SOCKETS_MAX); 1167 exit(1); 1168 } 1169 1170 /* Initialize sockets */ 1171 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1172 for (i = 0; i < riscv_socket_count(machine); i++) { 1173 if (!riscv_socket_check_hartids(machine, i)) { 1174 error_report("discontinuous hartids in socket%d", i); 1175 exit(1); 1176 } 1177 1178 base_hartid = riscv_socket_first_hartid(machine, i); 1179 if (base_hartid < 0) { 1180 error_report("can't find hartid base for socket%d", i); 1181 exit(1); 1182 } 1183 1184 hart_count = riscv_socket_hart_count(machine, i); 1185 if (hart_count < 0) { 1186 error_report("can't find hart count for socket%d", i); 1187 exit(1); 1188 } 1189 1190 soc_name = g_strdup_printf("soc%d", i); 1191 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1192 TYPE_RISCV_HART_ARRAY); 1193 g_free(soc_name); 1194 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1195 machine->cpu_type, &error_abort); 1196 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1197 base_hartid, &error_abort); 1198 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1199 hart_count, &error_abort); 1200 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 1201 1202 if (!kvm_enabled()) { 1203 if (s->have_aclint) { 1204 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1205 /* Per-socket ACLINT MTIMER */ 1206 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1207 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1208 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1209 base_hartid, hart_count, 1210 RISCV_ACLINT_DEFAULT_MTIMECMP, 1211 RISCV_ACLINT_DEFAULT_MTIME, 1212 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1213 } else { 1214 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1215 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1216 i * memmap[VIRT_CLINT].size, 1217 base_hartid, hart_count, false); 1218 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1219 i * memmap[VIRT_CLINT].size + 1220 RISCV_ACLINT_SWI_SIZE, 1221 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1222 base_hartid, hart_count, 1223 RISCV_ACLINT_DEFAULT_MTIMECMP, 1224 RISCV_ACLINT_DEFAULT_MTIME, 1225 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1226 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1227 i * memmap[VIRT_ACLINT_SSWI].size, 1228 base_hartid, hart_count, true); 1229 } 1230 } else { 1231 /* Per-socket SiFive CLINT */ 1232 riscv_aclint_swi_create( 1233 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1234 base_hartid, hart_count, false); 1235 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1236 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1237 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1238 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1239 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1240 } 1241 } 1242 1243 /* Per-socket interrupt controller */ 1244 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1245 s->irqchip[i] = virt_create_plic(memmap, i, 1246 base_hartid, hart_count); 1247 } else { 1248 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1249 memmap, i, base_hartid, 1250 hart_count); 1251 } 1252 1253 /* Try to use different IRQCHIP instance based device type */ 1254 if (i == 0) { 1255 mmio_irqchip = s->irqchip[i]; 1256 virtio_irqchip = s->irqchip[i]; 1257 pcie_irqchip = s->irqchip[i]; 1258 } 1259 if (i == 1) { 1260 virtio_irqchip = s->irqchip[i]; 1261 pcie_irqchip = s->irqchip[i]; 1262 } 1263 if (i == 2) { 1264 pcie_irqchip = s->irqchip[i]; 1265 } 1266 } 1267 1268 if (riscv_is_32bit(&s->soc[0])) { 1269 #if HOST_LONG_BITS == 64 1270 /* limit RAM size in a 32-bit system */ 1271 if (machine->ram_size > 10 * GiB) { 1272 machine->ram_size = 10 * GiB; 1273 error_report("Limiting RAM size to 10 GiB"); 1274 } 1275 #endif 1276 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1277 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1278 } else { 1279 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1280 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1281 virt_high_pcie_memmap.base = 1282 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1283 } 1284 1285 /* register system main memory (actual RAM) */ 1286 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1287 machine->ram); 1288 1289 /* create device tree */ 1290 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1291 riscv_is_32bit(&s->soc[0])); 1292 1293 /* boot rom */ 1294 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1295 memmap[VIRT_MROM].size, &error_fatal); 1296 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1297 mask_rom); 1298 1299 /* 1300 * Only direct boot kernel is currently supported for KVM VM, 1301 * so the "-bios" parameter is ignored and treated like "-bios none" 1302 * when KVM is enabled. 1303 */ 1304 if (kvm_enabled()) { 1305 g_free(machine->firmware); 1306 machine->firmware = g_strdup("none"); 1307 } 1308 1309 if (riscv_is_32bit(&s->soc[0])) { 1310 firmware_end_addr = riscv_find_and_load_firmware(machine, 1311 RISCV32_BIOS_BIN, start_addr, NULL); 1312 } else { 1313 firmware_end_addr = riscv_find_and_load_firmware(machine, 1314 RISCV64_BIOS_BIN, start_addr, NULL); 1315 } 1316 1317 if (machine->kernel_filename) { 1318 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1319 firmware_end_addr); 1320 1321 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1322 kernel_start_addr, NULL); 1323 1324 if (machine->initrd_filename) { 1325 hwaddr start; 1326 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1327 machine->ram_size, kernel_entry, 1328 &start); 1329 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1330 "linux,initrd-start", start); 1331 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1332 end); 1333 } 1334 } else { 1335 /* 1336 * If dynamic firmware is used, it doesn't know where is the next mode 1337 * if kernel argument is not set. 1338 */ 1339 kernel_entry = 0; 1340 } 1341 1342 if (drive_get(IF_PFLASH, 0, 0)) { 1343 /* 1344 * Pflash was supplied, let's overwrite the address we jump to after 1345 * reset to the base of the flash. 1346 */ 1347 start_addr = virt_memmap[VIRT_FLASH].base; 1348 } 1349 1350 /* 1351 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1352 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1353 */ 1354 s->fw_cfg = create_fw_cfg(machine); 1355 rom_set_fw(s->fw_cfg); 1356 1357 /* Compute the fdt load address in dram */ 1358 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1359 machine->ram_size, machine->fdt); 1360 /* load the reset vector */ 1361 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1362 virt_memmap[VIRT_MROM].base, 1363 virt_memmap[VIRT_MROM].size, kernel_entry, 1364 fdt_load_addr, machine->fdt); 1365 1366 /* 1367 * Only direct boot kernel is currently supported for KVM VM, 1368 * So here setup kernel start address and fdt address. 1369 * TODO:Support firmware loading and integrate to TCG start 1370 */ 1371 if (kvm_enabled()) { 1372 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1373 } 1374 1375 /* SiFive Test MMIO device */ 1376 sifive_test_create(memmap[VIRT_TEST].base); 1377 1378 /* VirtIO MMIO devices */ 1379 for (i = 0; i < VIRTIO_COUNT; i++) { 1380 sysbus_create_simple("virtio-mmio", 1381 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1382 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1383 } 1384 1385 gpex_pcie_init(system_memory, 1386 memmap[VIRT_PCIE_ECAM].base, 1387 memmap[VIRT_PCIE_ECAM].size, 1388 memmap[VIRT_PCIE_MMIO].base, 1389 memmap[VIRT_PCIE_MMIO].size, 1390 virt_high_pcie_memmap.base, 1391 virt_high_pcie_memmap.size, 1392 memmap[VIRT_PCIE_PIO].base, 1393 DEVICE(pcie_irqchip)); 1394 1395 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1396 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1397 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1398 1399 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1400 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1401 1402 virt_flash_create(s); 1403 1404 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1405 /* Map legacy -drive if=pflash to machine properties */ 1406 pflash_cfi01_legacy_drive(s->flash[i], 1407 drive_get(IF_PFLASH, 0, i)); 1408 } 1409 virt_flash_map(s, system_memory); 1410 } 1411 1412 static void virt_machine_instance_init(Object *obj) 1413 { 1414 } 1415 1416 static char *virt_get_aia_guests(Object *obj, Error **errp) 1417 { 1418 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1419 char val[32]; 1420 1421 sprintf(val, "%d", s->aia_guests); 1422 return g_strdup(val); 1423 } 1424 1425 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1426 { 1427 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1428 1429 s->aia_guests = atoi(val); 1430 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1431 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1432 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1433 VIRT_IRQCHIP_MAX_GUESTS); 1434 } 1435 } 1436 1437 static char *virt_get_aia(Object *obj, Error **errp) 1438 { 1439 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1440 const char *val; 1441 1442 switch (s->aia_type) { 1443 case VIRT_AIA_TYPE_APLIC: 1444 val = "aplic"; 1445 break; 1446 case VIRT_AIA_TYPE_APLIC_IMSIC: 1447 val = "aplic-imsic"; 1448 break; 1449 default: 1450 val = "none"; 1451 break; 1452 }; 1453 1454 return g_strdup(val); 1455 } 1456 1457 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1458 { 1459 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1460 1461 if (!strcmp(val, "none")) { 1462 s->aia_type = VIRT_AIA_TYPE_NONE; 1463 } else if (!strcmp(val, "aplic")) { 1464 s->aia_type = VIRT_AIA_TYPE_APLIC; 1465 } else if (!strcmp(val, "aplic-imsic")) { 1466 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1467 } else { 1468 error_setg(errp, "Invalid AIA interrupt controller type"); 1469 error_append_hint(errp, "Valid values are none, aplic, and " 1470 "aplic-imsic.\n"); 1471 } 1472 } 1473 1474 static bool virt_get_aclint(Object *obj, Error **errp) 1475 { 1476 MachineState *ms = MACHINE(obj); 1477 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1478 1479 return s->have_aclint; 1480 } 1481 1482 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1483 { 1484 MachineState *ms = MACHINE(obj); 1485 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1486 1487 s->have_aclint = value; 1488 } 1489 1490 static void virt_machine_class_init(ObjectClass *oc, void *data) 1491 { 1492 char str[128]; 1493 MachineClass *mc = MACHINE_CLASS(oc); 1494 1495 mc->desc = "RISC-V VirtIO board"; 1496 mc->init = virt_machine_init; 1497 mc->max_cpus = VIRT_CPUS_MAX; 1498 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1499 mc->pci_allow_0_address = true; 1500 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1501 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1502 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1503 mc->numa_mem_supported = true; 1504 mc->default_ram_id = "riscv_virt_board.ram"; 1505 1506 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1507 1508 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1509 virt_set_aclint); 1510 object_class_property_set_description(oc, "aclint", 1511 "Set on/off to enable/disable " 1512 "emulating ACLINT devices"); 1513 1514 object_class_property_add_str(oc, "aia", virt_get_aia, 1515 virt_set_aia); 1516 object_class_property_set_description(oc, "aia", 1517 "Set type of AIA interrupt " 1518 "conttoller. Valid values are " 1519 "none, aplic, and aplic-imsic."); 1520 1521 object_class_property_add_str(oc, "aia-guests", 1522 virt_get_aia_guests, 1523 virt_set_aia_guests); 1524 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1525 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1526 object_class_property_set_description(oc, "aia-guests", str); 1527 } 1528 1529 static const TypeInfo virt_machine_typeinfo = { 1530 .name = MACHINE_TYPE_NAME("virt"), 1531 .parent = TYPE_MACHINE, 1532 .class_init = virt_machine_class_init, 1533 .instance_init = virt_machine_instance_init, 1534 .instance_size = sizeof(RISCVVirtState), 1535 }; 1536 1537 static void virt_machine_init_register_types(void) 1538 { 1539 type_register_static(&virt_machine_typeinfo); 1540 } 1541 1542 type_init(virt_machine_init_register_types) 1543