1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/sifive_clint.h" 36 #include "hw/intc/sifive_plic.h" 37 #include "hw/misc/sifive_test.h" 38 #include "chardev/char.h" 39 #include "sysemu/arch_init.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci-host/gpex.h" 44 #include "hw/display/ramfb.h" 45 46 static const MemMapEntry virt_memmap[] = { 47 [VIRT_DEBUG] = { 0x0, 0x100 }, 48 [VIRT_MROM] = { 0x1000, 0xf000 }, 49 [VIRT_TEST] = { 0x100000, 0x1000 }, 50 [VIRT_RTC] = { 0x101000, 0x1000 }, 51 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 52 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 53 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 54 [VIRT_UART0] = { 0x10000000, 0x100 }, 55 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 56 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 57 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 58 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 59 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 60 [VIRT_DRAM] = { 0x80000000, 0x0 }, 61 }; 62 63 /* PCIe high mmio is fixed for RV32 */ 64 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 65 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 66 67 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 68 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 69 70 static MemMapEntry virt_high_pcie_memmap; 71 72 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 73 74 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 75 const char *name, 76 const char *alias_prop_name) 77 { 78 /* 79 * Create a single flash device. We use the same parameters as 80 * the flash devices on the ARM virt board. 81 */ 82 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 83 84 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 85 qdev_prop_set_uint8(dev, "width", 4); 86 qdev_prop_set_uint8(dev, "device-width", 2); 87 qdev_prop_set_bit(dev, "big-endian", false); 88 qdev_prop_set_uint16(dev, "id0", 0x89); 89 qdev_prop_set_uint16(dev, "id1", 0x18); 90 qdev_prop_set_uint16(dev, "id2", 0x00); 91 qdev_prop_set_uint16(dev, "id3", 0x00); 92 qdev_prop_set_string(dev, "name", name); 93 94 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 95 object_property_add_alias(OBJECT(s), alias_prop_name, 96 OBJECT(dev), "drive"); 97 98 return PFLASH_CFI01(dev); 99 } 100 101 static void virt_flash_create(RISCVVirtState *s) 102 { 103 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 104 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 105 } 106 107 static void virt_flash_map1(PFlashCFI01 *flash, 108 hwaddr base, hwaddr size, 109 MemoryRegion *sysmem) 110 { 111 DeviceState *dev = DEVICE(flash); 112 113 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 114 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 115 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 117 118 memory_region_add_subregion(sysmem, base, 119 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 120 0)); 121 } 122 123 static void virt_flash_map(RISCVVirtState *s, 124 MemoryRegion *sysmem) 125 { 126 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 127 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 128 129 virt_flash_map1(s->flash[0], flashbase, flashsize, 130 sysmem); 131 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 132 sysmem); 133 } 134 135 static void create_pcie_irq_map(void *fdt, char *nodename, 136 uint32_t plic_phandle) 137 { 138 int pin, dev; 139 uint32_t 140 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 141 uint32_t *irq_map = full_irq_map; 142 143 /* This code creates a standard swizzle of interrupts such that 144 * each device's first interrupt is based on it's PCI_SLOT number. 145 * (See pci_swizzle_map_irq_fn()) 146 * 147 * We only need one entry per interrupt in the table (not one per 148 * possible slot) seeing the interrupt-map-mask will allow the table 149 * to wrap to any number of devices. 150 */ 151 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 152 int devfn = dev * 0x8; 153 154 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 155 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 156 int i = 0; 157 158 irq_map[i] = cpu_to_be32(devfn << 8); 159 160 i += FDT_PCI_ADDR_CELLS; 161 irq_map[i] = cpu_to_be32(pin + 1); 162 163 i += FDT_PCI_INT_CELLS; 164 irq_map[i++] = cpu_to_be32(plic_phandle); 165 166 i += FDT_PLIC_ADDR_CELLS; 167 irq_map[i] = cpu_to_be32(irq_nr); 168 169 irq_map += FDT_INT_MAP_WIDTH; 170 } 171 } 172 173 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 174 full_irq_map, sizeof(full_irq_map)); 175 176 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 177 0x1800, 0, 0, 0x7); 178 } 179 180 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 181 uint64_t mem_size, const char *cmdline, bool is_32_bit) 182 { 183 void *fdt; 184 int i, cpu, socket; 185 MachineState *mc = MACHINE(s); 186 uint64_t addr, size; 187 uint32_t *clint_cells, *plic_cells; 188 unsigned long clint_addr, plic_addr; 189 uint32_t plic_phandle[MAX_NODES]; 190 uint32_t cpu_phandle, intc_phandle, test_phandle; 191 uint32_t phandle = 1, plic_mmio_phandle = 1; 192 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 193 char *mem_name, *cpu_name, *core_name, *intc_name; 194 char *name, *clint_name, *plic_name, *clust_name; 195 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 196 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 197 static const char * const clint_compat[2] = { 198 "sifive,clint0", "riscv,clint0" 199 }; 200 201 if (mc->dtb) { 202 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 203 if (!fdt) { 204 error_report("load_device_tree() failed"); 205 exit(1); 206 } 207 goto update_bootargs; 208 } else { 209 fdt = mc->fdt = create_device_tree(&s->fdt_size); 210 if (!fdt) { 211 error_report("create_device_tree() failed"); 212 exit(1); 213 } 214 } 215 216 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 217 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 218 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 219 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 220 221 qemu_fdt_add_subnode(fdt, "/soc"); 222 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 223 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 224 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 225 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 226 227 qemu_fdt_add_subnode(fdt, "/cpus"); 228 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 229 SIFIVE_CLINT_TIMEBASE_FREQ); 230 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 231 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 232 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 233 234 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 235 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 236 qemu_fdt_add_subnode(fdt, clust_name); 237 238 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 239 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 240 241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 242 cpu_phandle = phandle++; 243 244 cpu_name = g_strdup_printf("/cpus/cpu@%d", 245 s->soc[socket].hartid_base + cpu); 246 qemu_fdt_add_subnode(fdt, cpu_name); 247 if (is_32_bit) { 248 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 249 } else { 250 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 251 } 252 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 253 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 254 g_free(name); 255 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 256 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 257 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 258 s->soc[socket].hartid_base + cpu); 259 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 260 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 261 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 262 263 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 264 qemu_fdt_add_subnode(fdt, intc_name); 265 intc_phandle = phandle++; 266 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 267 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 268 "riscv,cpu-intc"); 269 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 270 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 271 272 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 273 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 274 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 275 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 276 277 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 278 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 279 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 280 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 281 282 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 283 qemu_fdt_add_subnode(fdt, core_name); 284 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 285 286 g_free(core_name); 287 g_free(intc_name); 288 g_free(cpu_name); 289 } 290 291 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 292 size = riscv_socket_mem_size(mc, socket); 293 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 294 qemu_fdt_add_subnode(fdt, mem_name); 295 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 296 addr >> 32, addr, size >> 32, size); 297 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 298 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 299 g_free(mem_name); 300 301 clint_addr = memmap[VIRT_CLINT].base + 302 (memmap[VIRT_CLINT].size * socket); 303 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 304 qemu_fdt_add_subnode(fdt, clint_name); 305 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 306 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 307 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 308 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 309 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 310 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 311 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 312 g_free(clint_name); 313 314 plic_phandle[socket] = phandle++; 315 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 316 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 317 qemu_fdt_add_subnode(fdt, plic_name); 318 qemu_fdt_setprop_cell(fdt, plic_name, 319 "#address-cells", FDT_PLIC_ADDR_CELLS); 320 qemu_fdt_setprop_cell(fdt, plic_name, 321 "#interrupt-cells", FDT_PLIC_INT_CELLS); 322 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 323 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 324 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 325 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 326 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 327 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 328 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 329 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 330 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 331 g_free(plic_name); 332 333 g_free(clint_cells); 334 g_free(plic_cells); 335 g_free(clust_name); 336 } 337 338 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 339 if (socket == 0) { 340 plic_mmio_phandle = plic_phandle[socket]; 341 plic_virtio_phandle = plic_phandle[socket]; 342 plic_pcie_phandle = plic_phandle[socket]; 343 } 344 if (socket == 1) { 345 plic_virtio_phandle = plic_phandle[socket]; 346 plic_pcie_phandle = plic_phandle[socket]; 347 } 348 if (socket == 2) { 349 plic_pcie_phandle = plic_phandle[socket]; 350 } 351 } 352 353 riscv_socket_fdt_write_distance_matrix(mc, fdt); 354 355 for (i = 0; i < VIRTIO_COUNT; i++) { 356 name = g_strdup_printf("/soc/virtio_mmio@%lx", 357 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 358 qemu_fdt_add_subnode(fdt, name); 359 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 360 qemu_fdt_setprop_cells(fdt, name, "reg", 361 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 362 0x0, memmap[VIRT_VIRTIO].size); 363 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 364 plic_virtio_phandle); 365 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 366 g_free(name); 367 } 368 369 name = g_strdup_printf("/soc/pci@%lx", 370 (long) memmap[VIRT_PCIE_ECAM].base); 371 qemu_fdt_add_subnode(fdt, name); 372 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 373 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 374 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 375 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 376 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 377 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 378 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 379 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 380 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 381 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 382 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 383 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 384 1, FDT_PCI_RANGE_IOPORT, 2, 0, 385 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 386 1, FDT_PCI_RANGE_MMIO, 387 2, memmap[VIRT_PCIE_MMIO].base, 388 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 389 1, FDT_PCI_RANGE_MMIO_64BIT, 390 2, virt_high_pcie_memmap.base, 391 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 392 393 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 394 g_free(name); 395 396 test_phandle = phandle++; 397 name = g_strdup_printf("/soc/test@%lx", 398 (long)memmap[VIRT_TEST].base); 399 qemu_fdt_add_subnode(fdt, name); 400 { 401 static const char * const compat[3] = { 402 "sifive,test1", "sifive,test0", "syscon" 403 }; 404 qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, 405 ARRAY_SIZE(compat)); 406 } 407 qemu_fdt_setprop_cells(fdt, name, "reg", 408 0x0, memmap[VIRT_TEST].base, 409 0x0, memmap[VIRT_TEST].size); 410 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 411 test_phandle = qemu_fdt_get_phandle(fdt, name); 412 g_free(name); 413 414 name = g_strdup_printf("/soc/reboot"); 415 qemu_fdt_add_subnode(fdt, name); 416 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 417 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 418 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 419 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 420 g_free(name); 421 422 name = g_strdup_printf("/soc/poweroff"); 423 qemu_fdt_add_subnode(fdt, name); 424 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 425 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 426 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 427 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 428 g_free(name); 429 430 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 431 qemu_fdt_add_subnode(fdt, name); 432 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 433 qemu_fdt_setprop_cells(fdt, name, "reg", 434 0x0, memmap[VIRT_UART0].base, 435 0x0, memmap[VIRT_UART0].size); 436 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 437 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 438 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 439 440 qemu_fdt_add_subnode(fdt, "/chosen"); 441 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 442 g_free(name); 443 444 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 445 qemu_fdt_add_subnode(fdt, name); 446 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 447 qemu_fdt_setprop_cells(fdt, name, "reg", 448 0x0, memmap[VIRT_RTC].base, 449 0x0, memmap[VIRT_RTC].size); 450 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 451 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 452 g_free(name); 453 454 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 455 qemu_fdt_add_subnode(mc->fdt, name); 456 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 457 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 458 2, flashbase, 2, flashsize, 459 2, flashbase + flashsize, 2, flashsize); 460 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 461 g_free(name); 462 463 update_bootargs: 464 if (cmdline) { 465 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 466 } 467 } 468 469 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 470 hwaddr ecam_base, hwaddr ecam_size, 471 hwaddr mmio_base, hwaddr mmio_size, 472 hwaddr high_mmio_base, 473 hwaddr high_mmio_size, 474 hwaddr pio_base, 475 DeviceState *plic) 476 { 477 DeviceState *dev; 478 MemoryRegion *ecam_alias, *ecam_reg; 479 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 480 qemu_irq irq; 481 int i; 482 483 dev = qdev_new(TYPE_GPEX_HOST); 484 485 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 486 487 ecam_alias = g_new0(MemoryRegion, 1); 488 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 489 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 490 ecam_reg, 0, ecam_size); 491 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 492 493 mmio_alias = g_new0(MemoryRegion, 1); 494 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 495 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 496 mmio_reg, mmio_base, mmio_size); 497 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 498 499 /* Map high MMIO space */ 500 high_mmio_alias = g_new0(MemoryRegion, 1); 501 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 502 mmio_reg, high_mmio_base, high_mmio_size); 503 memory_region_add_subregion(get_system_memory(), high_mmio_base, 504 high_mmio_alias); 505 506 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 507 508 for (i = 0; i < GPEX_NUM_IRQS; i++) { 509 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 510 511 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 512 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 513 } 514 515 return dev; 516 } 517 518 static FWCfgState *create_fw_cfg(const MachineState *mc) 519 { 520 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 521 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 522 FWCfgState *fw_cfg; 523 char *nodename; 524 525 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 526 &address_space_memory); 527 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 528 529 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 530 qemu_fdt_add_subnode(mc->fdt, nodename); 531 qemu_fdt_setprop_string(mc->fdt, nodename, 532 "compatible", "qemu,fw-cfg-mmio"); 533 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 534 2, base, 2, size); 535 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 536 g_free(nodename); 537 return fw_cfg; 538 } 539 540 static void virt_machine_init(MachineState *machine) 541 { 542 const MemMapEntry *memmap = virt_memmap; 543 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 544 MemoryRegion *system_memory = get_system_memory(); 545 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 546 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 547 char *plic_hart_config, *soc_name; 548 size_t plic_hart_config_len; 549 target_ulong start_addr = memmap[VIRT_DRAM].base; 550 target_ulong firmware_end_addr, kernel_start_addr; 551 uint32_t fdt_load_addr; 552 uint64_t kernel_entry; 553 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 554 int i, j, base_hartid, hart_count; 555 556 /* Check socket count limit */ 557 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 558 error_report("number of sockets/nodes should be less than %d", 559 VIRT_SOCKETS_MAX); 560 exit(1); 561 } 562 563 /* Initialize sockets */ 564 mmio_plic = virtio_plic = pcie_plic = NULL; 565 for (i = 0; i < riscv_socket_count(machine); i++) { 566 if (!riscv_socket_check_hartids(machine, i)) { 567 error_report("discontinuous hartids in socket%d", i); 568 exit(1); 569 } 570 571 base_hartid = riscv_socket_first_hartid(machine, i); 572 if (base_hartid < 0) { 573 error_report("can't find hartid base for socket%d", i); 574 exit(1); 575 } 576 577 hart_count = riscv_socket_hart_count(machine, i); 578 if (hart_count < 0) { 579 error_report("can't find hart count for socket%d", i); 580 exit(1); 581 } 582 583 soc_name = g_strdup_printf("soc%d", i); 584 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 585 TYPE_RISCV_HART_ARRAY); 586 g_free(soc_name); 587 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 588 machine->cpu_type, &error_abort); 589 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 590 base_hartid, &error_abort); 591 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 592 hart_count, &error_abort); 593 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 594 595 /* Per-socket CLINT */ 596 sifive_clint_create( 597 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 598 memmap[VIRT_CLINT].size, base_hartid, hart_count, 599 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 600 SIFIVE_CLINT_TIMEBASE_FREQ, true); 601 602 /* Per-socket PLIC hart topology configuration string */ 603 plic_hart_config_len = 604 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 605 plic_hart_config = g_malloc0(plic_hart_config_len); 606 for (j = 0; j < hart_count; j++) { 607 if (j != 0) { 608 strncat(plic_hart_config, ",", plic_hart_config_len); 609 } 610 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 611 plic_hart_config_len); 612 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 613 } 614 615 /* Per-socket PLIC */ 616 s->plic[i] = sifive_plic_create( 617 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 618 plic_hart_config, base_hartid, 619 VIRT_PLIC_NUM_SOURCES, 620 VIRT_PLIC_NUM_PRIORITIES, 621 VIRT_PLIC_PRIORITY_BASE, 622 VIRT_PLIC_PENDING_BASE, 623 VIRT_PLIC_ENABLE_BASE, 624 VIRT_PLIC_ENABLE_STRIDE, 625 VIRT_PLIC_CONTEXT_BASE, 626 VIRT_PLIC_CONTEXT_STRIDE, 627 memmap[VIRT_PLIC].size); 628 g_free(plic_hart_config); 629 630 /* Try to use different PLIC instance based device type */ 631 if (i == 0) { 632 mmio_plic = s->plic[i]; 633 virtio_plic = s->plic[i]; 634 pcie_plic = s->plic[i]; 635 } 636 if (i == 1) { 637 virtio_plic = s->plic[i]; 638 pcie_plic = s->plic[i]; 639 } 640 if (i == 2) { 641 pcie_plic = s->plic[i]; 642 } 643 } 644 645 if (riscv_is_32bit(&s->soc[0])) { 646 #if HOST_LONG_BITS == 64 647 /* limit RAM size in a 32-bit system */ 648 if (machine->ram_size > 10 * GiB) { 649 machine->ram_size = 10 * GiB; 650 error_report("Limiting RAM size to 10 GiB"); 651 } 652 #endif 653 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 654 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 655 } else { 656 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 657 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 658 virt_high_pcie_memmap.base = 659 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 660 } 661 662 /* register system main memory (actual RAM) */ 663 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 664 machine->ram_size, &error_fatal); 665 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 666 main_mem); 667 668 /* create device tree */ 669 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 670 riscv_is_32bit(&s->soc[0])); 671 672 /* boot rom */ 673 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 674 memmap[VIRT_MROM].size, &error_fatal); 675 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 676 mask_rom); 677 678 if (riscv_is_32bit(&s->soc[0])) { 679 firmware_end_addr = riscv_find_and_load_firmware(machine, 680 "opensbi-riscv32-generic-fw_dynamic.bin", 681 start_addr, NULL); 682 } else { 683 firmware_end_addr = riscv_find_and_load_firmware(machine, 684 "opensbi-riscv64-generic-fw_dynamic.bin", 685 start_addr, NULL); 686 } 687 688 if (machine->kernel_filename) { 689 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 690 firmware_end_addr); 691 692 kernel_entry = riscv_load_kernel(machine->kernel_filename, 693 kernel_start_addr, NULL); 694 695 if (machine->initrd_filename) { 696 hwaddr start; 697 hwaddr end = riscv_load_initrd(machine->initrd_filename, 698 machine->ram_size, kernel_entry, 699 &start); 700 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 701 "linux,initrd-start", start); 702 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 703 end); 704 } 705 } else { 706 /* 707 * If dynamic firmware is used, it doesn't know where is the next mode 708 * if kernel argument is not set. 709 */ 710 kernel_entry = 0; 711 } 712 713 if (drive_get(IF_PFLASH, 0, 0)) { 714 /* 715 * Pflash was supplied, let's overwrite the address we jump to after 716 * reset to the base of the flash. 717 */ 718 start_addr = virt_memmap[VIRT_FLASH].base; 719 } 720 721 /* 722 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 723 * tree cannot be altered and we get FDT_ERR_NOSPACE. 724 */ 725 s->fw_cfg = create_fw_cfg(machine); 726 rom_set_fw(s->fw_cfg); 727 728 /* Compute the fdt load address in dram */ 729 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 730 machine->ram_size, machine->fdt); 731 /* load the reset vector */ 732 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 733 virt_memmap[VIRT_MROM].base, 734 virt_memmap[VIRT_MROM].size, kernel_entry, 735 fdt_load_addr, machine->fdt); 736 737 /* SiFive Test MMIO device */ 738 sifive_test_create(memmap[VIRT_TEST].base); 739 740 /* VirtIO MMIO devices */ 741 for (i = 0; i < VIRTIO_COUNT; i++) { 742 sysbus_create_simple("virtio-mmio", 743 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 744 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 745 } 746 747 gpex_pcie_init(system_memory, 748 memmap[VIRT_PCIE_ECAM].base, 749 memmap[VIRT_PCIE_ECAM].size, 750 memmap[VIRT_PCIE_MMIO].base, 751 memmap[VIRT_PCIE_MMIO].size, 752 virt_high_pcie_memmap.base, 753 virt_high_pcie_memmap.size, 754 memmap[VIRT_PCIE_PIO].base, 755 DEVICE(pcie_plic)); 756 757 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 758 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 759 serial_hd(0), DEVICE_LITTLE_ENDIAN); 760 761 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 762 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 763 764 virt_flash_create(s); 765 766 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 767 /* Map legacy -drive if=pflash to machine properties */ 768 pflash_cfi01_legacy_drive(s->flash[i], 769 drive_get(IF_PFLASH, 0, i)); 770 } 771 virt_flash_map(s, system_memory); 772 } 773 774 static void virt_machine_instance_init(Object *obj) 775 { 776 } 777 778 static void virt_machine_class_init(ObjectClass *oc, void *data) 779 { 780 MachineClass *mc = MACHINE_CLASS(oc); 781 782 mc->desc = "RISC-V VirtIO board"; 783 mc->init = virt_machine_init; 784 mc->max_cpus = VIRT_CPUS_MAX; 785 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 786 mc->pci_allow_0_address = true; 787 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 788 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 789 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 790 mc->numa_mem_supported = true; 791 792 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 793 } 794 795 static const TypeInfo virt_machine_typeinfo = { 796 .name = MACHINE_TYPE_NAME("virt"), 797 .parent = TYPE_MACHINE, 798 .class_init = virt_machine_class_init, 799 .instance_init = virt_machine_instance_init, 800 .instance_size = sizeof(RISCVVirtState), 801 }; 802 803 static void virt_machine_init_register_types(void) 804 { 805 type_register_static(&virt_machine_typeinfo); 806 } 807 808 type_init(virt_machine_init_register_types) 809