1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/firmware/smbios.h" 40 #include "hw/intc/riscv_aclint.h" 41 #include "hw/intc/riscv_aplic.h" 42 #include "hw/intc/sifive_plic.h" 43 #include "hw/misc/sifive_test.h" 44 #include "hw/platform-bus.h" 45 #include "chardev/char.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/tcg.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/tpm.h" 51 #include "hw/pci/pci.h" 52 #include "hw/pci-host/gpex.h" 53 #include "hw/display/ramfb.h" 54 #include "hw/acpi/aml-build.h" 55 #include "qapi/qapi-visit-common.h" 56 #include "hw/virtio/virtio-iommu.h" 57 58 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 59 static bool virt_use_kvm_aia(RISCVVirtState *s) 60 { 61 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 62 } 63 64 static const MemMapEntry virt_memmap[] = { 65 [VIRT_DEBUG] = { 0x0, 0x100 }, 66 [VIRT_MROM] = { 0x1000, 0xf000 }, 67 [VIRT_TEST] = { 0x100000, 0x1000 }, 68 [VIRT_RTC] = { 0x101000, 0x1000 }, 69 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 70 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 71 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 72 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 73 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 74 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 75 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 76 [VIRT_UART0] = { 0x10000000, 0x100 }, 77 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 78 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 79 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 80 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 81 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 82 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 83 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 84 [VIRT_DRAM] = { 0x80000000, 0x0 }, 85 }; 86 87 /* PCIe high mmio is fixed for RV32 */ 88 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 89 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 90 91 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 92 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 93 94 static MemMapEntry virt_high_pcie_memmap; 95 96 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 97 98 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 99 const char *name, 100 const char *alias_prop_name) 101 { 102 /* 103 * Create a single flash device. We use the same parameters as 104 * the flash devices on the ARM virt board. 105 */ 106 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 107 108 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 109 qdev_prop_set_uint8(dev, "width", 4); 110 qdev_prop_set_uint8(dev, "device-width", 2); 111 qdev_prop_set_bit(dev, "big-endian", false); 112 qdev_prop_set_uint16(dev, "id0", 0x89); 113 qdev_prop_set_uint16(dev, "id1", 0x18); 114 qdev_prop_set_uint16(dev, "id2", 0x00); 115 qdev_prop_set_uint16(dev, "id3", 0x00); 116 qdev_prop_set_string(dev, "name", name); 117 118 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 119 object_property_add_alias(OBJECT(s), alias_prop_name, 120 OBJECT(dev), "drive"); 121 122 return PFLASH_CFI01(dev); 123 } 124 125 static void virt_flash_create(RISCVVirtState *s) 126 { 127 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 128 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 129 } 130 131 static void virt_flash_map1(PFlashCFI01 *flash, 132 hwaddr base, hwaddr size, 133 MemoryRegion *sysmem) 134 { 135 DeviceState *dev = DEVICE(flash); 136 137 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 138 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 139 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 140 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 141 142 memory_region_add_subregion(sysmem, base, 143 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 144 0)); 145 } 146 147 static void virt_flash_map(RISCVVirtState *s, 148 MemoryRegion *sysmem) 149 { 150 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 151 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 152 153 virt_flash_map1(s->flash[0], flashbase, flashsize, 154 sysmem); 155 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 156 sysmem); 157 } 158 159 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 160 uint32_t irqchip_phandle) 161 { 162 int pin, dev; 163 uint32_t irq_map_stride = 0; 164 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 165 FDT_MAX_INT_MAP_WIDTH] = {}; 166 uint32_t *irq_map = full_irq_map; 167 168 /* This code creates a standard swizzle of interrupts such that 169 * each device's first interrupt is based on it's PCI_SLOT number. 170 * (See pci_swizzle_map_irq_fn()) 171 * 172 * We only need one entry per interrupt in the table (not one per 173 * possible slot) seeing the interrupt-map-mask will allow the table 174 * to wrap to any number of devices. 175 */ 176 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 177 int devfn = dev * 0x8; 178 179 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 180 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 181 int i = 0; 182 183 /* Fill PCI address cells */ 184 irq_map[i] = cpu_to_be32(devfn << 8); 185 i += FDT_PCI_ADDR_CELLS; 186 187 /* Fill PCI Interrupt cells */ 188 irq_map[i] = cpu_to_be32(pin + 1); 189 i += FDT_PCI_INT_CELLS; 190 191 /* Fill interrupt controller phandle and cells */ 192 irq_map[i++] = cpu_to_be32(irqchip_phandle); 193 irq_map[i++] = cpu_to_be32(irq_nr); 194 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 195 irq_map[i++] = cpu_to_be32(0x4); 196 } 197 198 if (!irq_map_stride) { 199 irq_map_stride = i; 200 } 201 irq_map += irq_map_stride; 202 } 203 } 204 205 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 206 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 207 irq_map_stride * sizeof(uint32_t)); 208 209 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 210 0x1800, 0, 0, 0x7); 211 } 212 213 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 214 char *clust_name, uint32_t *phandle, 215 uint32_t *intc_phandles) 216 { 217 int cpu; 218 uint32_t cpu_phandle; 219 MachineState *ms = MACHINE(s); 220 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 221 uint8_t satp_mode_max; 222 223 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 224 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 225 g_autofree char *cpu_name = NULL; 226 g_autofree char *core_name = NULL; 227 g_autofree char *intc_name = NULL; 228 g_autofree char *sv_name = NULL; 229 230 cpu_phandle = (*phandle)++; 231 232 cpu_name = g_strdup_printf("/cpus/cpu@%d", 233 s->soc[socket].hartid_base + cpu); 234 qemu_fdt_add_subnode(ms->fdt, cpu_name); 235 236 if (cpu_ptr->cfg.satp_mode.supported != 0) { 237 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 238 sv_name = g_strdup_printf("riscv,%s", 239 satp_mode_str(satp_mode_max, is_32_bit)); 240 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 241 } 242 243 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 244 245 if (cpu_ptr->cfg.ext_zicbom) { 246 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 247 cpu_ptr->cfg.cbom_blocksize); 248 } 249 250 if (cpu_ptr->cfg.ext_zicboz) { 251 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 252 cpu_ptr->cfg.cboz_blocksize); 253 } 254 255 if (cpu_ptr->cfg.ext_zicbop) { 256 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 257 cpu_ptr->cfg.cbop_blocksize); 258 } 259 260 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 261 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 263 s->soc[socket].hartid_base + cpu); 264 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 265 riscv_socket_fdt_write_id(ms, cpu_name, socket); 266 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 267 268 intc_phandles[cpu] = (*phandle)++; 269 270 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 271 qemu_fdt_add_subnode(ms->fdt, intc_name); 272 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 273 intc_phandles[cpu]); 274 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 275 "riscv,cpu-intc"); 276 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 277 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 278 279 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 280 qemu_fdt_add_subnode(ms->fdt, core_name); 281 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 282 } 283 } 284 285 static void create_fdt_socket_memory(RISCVVirtState *s, 286 const MemMapEntry *memmap, int socket) 287 { 288 g_autofree char *mem_name = NULL; 289 uint64_t addr, size; 290 MachineState *ms = MACHINE(s); 291 292 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 293 size = riscv_socket_mem_size(ms, socket); 294 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 295 qemu_fdt_add_subnode(ms->fdt, mem_name); 296 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 297 addr >> 32, addr, size >> 32, size); 298 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 299 riscv_socket_fdt_write_id(ms, mem_name, socket); 300 } 301 302 static void create_fdt_socket_clint(RISCVVirtState *s, 303 const MemMapEntry *memmap, int socket, 304 uint32_t *intc_phandles) 305 { 306 int cpu; 307 g_autofree char *clint_name = NULL; 308 g_autofree uint32_t *clint_cells = NULL; 309 unsigned long clint_addr; 310 MachineState *ms = MACHINE(s); 311 static const char * const clint_compat[2] = { 312 "sifive,clint0", "riscv,clint0" 313 }; 314 315 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 316 317 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 318 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 319 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 320 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 321 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 322 } 323 324 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 325 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 326 qemu_fdt_add_subnode(ms->fdt, clint_name); 327 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 328 (char **)&clint_compat, 329 ARRAY_SIZE(clint_compat)); 330 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 331 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 332 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 333 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 334 riscv_socket_fdt_write_id(ms, clint_name, socket); 335 } 336 337 static void create_fdt_socket_aclint(RISCVVirtState *s, 338 const MemMapEntry *memmap, int socket, 339 uint32_t *intc_phandles) 340 { 341 int cpu; 342 char *name; 343 unsigned long addr, size; 344 uint32_t aclint_cells_size; 345 g_autofree uint32_t *aclint_mswi_cells = NULL; 346 g_autofree uint32_t *aclint_sswi_cells = NULL; 347 g_autofree uint32_t *aclint_mtimer_cells = NULL; 348 MachineState *ms = MACHINE(s); 349 350 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 352 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 353 354 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 355 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 357 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 359 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 360 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 361 } 362 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 363 364 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 365 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 366 name = g_strdup_printf("/soc/mswi@%lx", addr); 367 qemu_fdt_add_subnode(ms->fdt, name); 368 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 369 "riscv,aclint-mswi"); 370 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 371 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 372 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 373 aclint_mswi_cells, aclint_cells_size); 374 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 375 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 376 riscv_socket_fdt_write_id(ms, name, socket); 377 g_free(name); 378 } 379 380 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 381 addr = memmap[VIRT_CLINT].base + 382 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 383 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 384 } else { 385 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 386 (memmap[VIRT_CLINT].size * socket); 387 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 388 } 389 name = g_strdup_printf("/soc/mtimer@%lx", addr); 390 qemu_fdt_add_subnode(ms->fdt, name); 391 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 392 "riscv,aclint-mtimer"); 393 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 395 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 396 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 397 0x0, RISCV_ACLINT_DEFAULT_MTIME); 398 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 399 aclint_mtimer_cells, aclint_cells_size); 400 riscv_socket_fdt_write_id(ms, name, socket); 401 g_free(name); 402 403 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 404 addr = memmap[VIRT_ACLINT_SSWI].base + 405 (memmap[VIRT_ACLINT_SSWI].size * socket); 406 name = g_strdup_printf("/soc/sswi@%lx", addr); 407 qemu_fdt_add_subnode(ms->fdt, name); 408 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 409 "riscv,aclint-sswi"); 410 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 411 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 412 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 413 aclint_sswi_cells, aclint_cells_size); 414 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 415 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 416 riscv_socket_fdt_write_id(ms, name, socket); 417 g_free(name); 418 } 419 } 420 421 static void create_fdt_socket_plic(RISCVVirtState *s, 422 const MemMapEntry *memmap, int socket, 423 uint32_t *phandle, uint32_t *intc_phandles, 424 uint32_t *plic_phandles) 425 { 426 int cpu; 427 g_autofree char *plic_name = NULL; 428 g_autofree uint32_t *plic_cells; 429 unsigned long plic_addr; 430 MachineState *ms = MACHINE(s); 431 static const char * const plic_compat[2] = { 432 "sifive,plic-1.0.0", "riscv,plic0" 433 }; 434 435 plic_phandles[socket] = (*phandle)++; 436 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 437 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 438 qemu_fdt_add_subnode(ms->fdt, plic_name); 439 qemu_fdt_setprop_cell(ms->fdt, plic_name, 440 "#interrupt-cells", FDT_PLIC_INT_CELLS); 441 qemu_fdt_setprop_cell(ms->fdt, plic_name, 442 "#address-cells", FDT_PLIC_ADDR_CELLS); 443 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 444 (char **)&plic_compat, 445 ARRAY_SIZE(plic_compat)); 446 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 447 448 if (kvm_enabled()) { 449 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 450 451 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 452 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 453 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 454 } 455 456 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 457 plic_cells, 458 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 459 } else { 460 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 461 462 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 463 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 464 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 465 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 466 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 467 } 468 469 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 470 plic_cells, 471 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 472 } 473 474 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 475 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 476 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 477 VIRT_IRQCHIP_NUM_SOURCES - 1); 478 riscv_socket_fdt_write_id(ms, plic_name, socket); 479 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 480 plic_phandles[socket]); 481 482 if (!socket) { 483 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 484 memmap[VIRT_PLATFORM_BUS].base, 485 memmap[VIRT_PLATFORM_BUS].size, 486 VIRT_PLATFORM_BUS_IRQ); 487 } 488 } 489 490 uint32_t imsic_num_bits(uint32_t count) 491 { 492 uint32_t ret = 0; 493 494 while (BIT(ret) < count) { 495 ret++; 496 } 497 498 return ret; 499 } 500 501 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 502 uint32_t *intc_phandles, uint32_t msi_phandle, 503 bool m_mode, uint32_t imsic_guest_bits) 504 { 505 int cpu, socket; 506 g_autofree char *imsic_name = NULL; 507 MachineState *ms = MACHINE(s); 508 int socket_count = riscv_socket_count(ms); 509 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 510 g_autofree uint32_t *imsic_cells = NULL; 511 g_autofree uint32_t *imsic_regs = NULL; 512 513 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 514 imsic_regs = g_new0(uint32_t, socket_count * 4); 515 516 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 517 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 518 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 519 } 520 521 imsic_max_hart_per_socket = 0; 522 for (socket = 0; socket < socket_count; socket++) { 523 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 524 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 525 s->soc[socket].num_harts; 526 imsic_regs[socket * 4 + 0] = 0; 527 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 528 imsic_regs[socket * 4 + 2] = 0; 529 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 530 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 531 imsic_max_hart_per_socket = s->soc[socket].num_harts; 532 } 533 } 534 535 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 536 qemu_fdt_add_subnode(ms->fdt, imsic_name); 537 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 538 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 539 FDT_IMSIC_INT_CELLS); 540 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 541 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 542 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 543 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 544 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 545 socket_count * sizeof(uint32_t) * 4); 546 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 547 VIRT_IRQCHIP_NUM_MSIS); 548 549 if (imsic_guest_bits) { 550 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 551 imsic_guest_bits); 552 } 553 554 if (socket_count > 1) { 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 556 imsic_num_bits(imsic_max_hart_per_socket)); 557 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 558 imsic_num_bits(socket_count)); 559 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 560 IMSIC_MMIO_GROUP_MIN_SHIFT); 561 } 562 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 563 } 564 565 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 566 uint32_t *phandle, uint32_t *intc_phandles, 567 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 568 { 569 *msi_m_phandle = (*phandle)++; 570 *msi_s_phandle = (*phandle)++; 571 572 if (!kvm_enabled()) { 573 /* M-level IMSIC node */ 574 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 575 *msi_m_phandle, true, 0); 576 } 577 578 /* S-level IMSIC node */ 579 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 580 *msi_s_phandle, false, 581 imsic_num_bits(s->aia_guests + 1)); 582 583 } 584 585 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 586 unsigned long aplic_addr, uint32_t aplic_size, 587 uint32_t msi_phandle, 588 uint32_t *intc_phandles, 589 uint32_t aplic_phandle, 590 uint32_t aplic_child_phandle, 591 bool m_mode, int num_harts) 592 { 593 int cpu; 594 g_autofree char *aplic_name = NULL; 595 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 596 MachineState *ms = MACHINE(s); 597 598 for (cpu = 0; cpu < num_harts; cpu++) { 599 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 600 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 601 } 602 603 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 604 qemu_fdt_add_subnode(ms->fdt, aplic_name); 605 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 606 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 607 "#interrupt-cells", FDT_APLIC_INT_CELLS); 608 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 609 610 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 611 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 612 aplic_cells, num_harts * sizeof(uint32_t) * 2); 613 } else { 614 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 615 } 616 617 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 618 0x0, aplic_addr, 0x0, aplic_size); 619 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 620 VIRT_IRQCHIP_NUM_SOURCES); 621 622 if (aplic_child_phandle) { 623 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 624 aplic_child_phandle); 625 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 626 aplic_child_phandle, 0x1, 627 VIRT_IRQCHIP_NUM_SOURCES); 628 } 629 630 riscv_socket_fdt_write_id(ms, aplic_name, socket); 631 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 632 } 633 634 static void create_fdt_socket_aplic(RISCVVirtState *s, 635 const MemMapEntry *memmap, int socket, 636 uint32_t msi_m_phandle, 637 uint32_t msi_s_phandle, 638 uint32_t *phandle, 639 uint32_t *intc_phandles, 640 uint32_t *aplic_phandles, 641 int num_harts) 642 { 643 g_autofree char *aplic_name = NULL; 644 unsigned long aplic_addr; 645 MachineState *ms = MACHINE(s); 646 uint32_t aplic_m_phandle, aplic_s_phandle; 647 648 aplic_m_phandle = (*phandle)++; 649 aplic_s_phandle = (*phandle)++; 650 651 if (!kvm_enabled()) { 652 /* M-level APLIC node */ 653 aplic_addr = memmap[VIRT_APLIC_M].base + 654 (memmap[VIRT_APLIC_M].size * socket); 655 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 656 msi_m_phandle, intc_phandles, 657 aplic_m_phandle, aplic_s_phandle, 658 true, num_harts); 659 } 660 661 /* S-level APLIC node */ 662 aplic_addr = memmap[VIRT_APLIC_S].base + 663 (memmap[VIRT_APLIC_S].size * socket); 664 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 665 msi_s_phandle, intc_phandles, 666 aplic_s_phandle, 0, 667 false, num_harts); 668 669 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 670 671 if (!socket) { 672 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 673 memmap[VIRT_PLATFORM_BUS].base, 674 memmap[VIRT_PLATFORM_BUS].size, 675 VIRT_PLATFORM_BUS_IRQ); 676 } 677 678 aplic_phandles[socket] = aplic_s_phandle; 679 } 680 681 static void create_fdt_pmu(RISCVVirtState *s) 682 { 683 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 684 MachineState *ms = MACHINE(s); 685 RISCVCPU hart = s->soc[0].harts[0]; 686 687 qemu_fdt_add_subnode(ms->fdt, pmu_name); 688 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 689 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 690 } 691 692 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 693 uint32_t *phandle, 694 uint32_t *irq_mmio_phandle, 695 uint32_t *irq_pcie_phandle, 696 uint32_t *irq_virtio_phandle, 697 uint32_t *msi_pcie_phandle) 698 { 699 int socket, phandle_pos; 700 MachineState *ms = MACHINE(s); 701 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 702 uint32_t xplic_phandles[MAX_NODES]; 703 g_autofree uint32_t *intc_phandles = NULL; 704 int socket_count = riscv_socket_count(ms); 705 706 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 707 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 708 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 709 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 710 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 711 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 712 713 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 714 715 phandle_pos = ms->smp.cpus; 716 for (socket = (socket_count - 1); socket >= 0; socket--) { 717 g_autofree char *clust_name = NULL; 718 phandle_pos -= s->soc[socket].num_harts; 719 720 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 721 qemu_fdt_add_subnode(ms->fdt, clust_name); 722 723 create_fdt_socket_cpus(s, socket, clust_name, phandle, 724 &intc_phandles[phandle_pos]); 725 726 create_fdt_socket_memory(s, memmap, socket); 727 728 if (tcg_enabled()) { 729 if (s->have_aclint) { 730 create_fdt_socket_aclint(s, memmap, socket, 731 &intc_phandles[phandle_pos]); 732 } else { 733 create_fdt_socket_clint(s, memmap, socket, 734 &intc_phandles[phandle_pos]); 735 } 736 } 737 } 738 739 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 740 create_fdt_imsic(s, memmap, phandle, intc_phandles, 741 &msi_m_phandle, &msi_s_phandle); 742 *msi_pcie_phandle = msi_s_phandle; 743 } 744 745 /* KVM AIA only has one APLIC instance */ 746 if (kvm_enabled() && virt_use_kvm_aia(s)) { 747 create_fdt_socket_aplic(s, memmap, 0, 748 msi_m_phandle, msi_s_phandle, phandle, 749 &intc_phandles[0], xplic_phandles, 750 ms->smp.cpus); 751 } else { 752 phandle_pos = ms->smp.cpus; 753 for (socket = (socket_count - 1); socket >= 0; socket--) { 754 phandle_pos -= s->soc[socket].num_harts; 755 756 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 757 create_fdt_socket_plic(s, memmap, socket, phandle, 758 &intc_phandles[phandle_pos], 759 xplic_phandles); 760 } else { 761 create_fdt_socket_aplic(s, memmap, socket, 762 msi_m_phandle, msi_s_phandle, phandle, 763 &intc_phandles[phandle_pos], 764 xplic_phandles, 765 s->soc[socket].num_harts); 766 } 767 } 768 } 769 770 if (kvm_enabled() && virt_use_kvm_aia(s)) { 771 *irq_mmio_phandle = xplic_phandles[0]; 772 *irq_virtio_phandle = xplic_phandles[0]; 773 *irq_pcie_phandle = xplic_phandles[0]; 774 } else { 775 for (socket = 0; socket < socket_count; socket++) { 776 if (socket == 0) { 777 *irq_mmio_phandle = xplic_phandles[socket]; 778 *irq_virtio_phandle = xplic_phandles[socket]; 779 *irq_pcie_phandle = xplic_phandles[socket]; 780 } 781 if (socket == 1) { 782 *irq_virtio_phandle = xplic_phandles[socket]; 783 *irq_pcie_phandle = xplic_phandles[socket]; 784 } 785 if (socket == 2) { 786 *irq_pcie_phandle = xplic_phandles[socket]; 787 } 788 } 789 } 790 791 riscv_socket_fdt_write_distance_matrix(ms); 792 } 793 794 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 795 uint32_t irq_virtio_phandle) 796 { 797 int i; 798 MachineState *ms = MACHINE(s); 799 800 for (i = 0; i < VIRTIO_COUNT; i++) { 801 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 802 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 803 804 qemu_fdt_add_subnode(ms->fdt, name); 805 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 806 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 807 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 808 0x0, memmap[VIRT_VIRTIO].size); 809 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 810 irq_virtio_phandle); 811 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 812 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 813 VIRTIO_IRQ + i); 814 } else { 815 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 816 VIRTIO_IRQ + i, 0x4); 817 } 818 } 819 } 820 821 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 822 uint32_t irq_pcie_phandle, 823 uint32_t msi_pcie_phandle) 824 { 825 g_autofree char *name = NULL; 826 MachineState *ms = MACHINE(s); 827 828 name = g_strdup_printf("/soc/pci@%lx", 829 (long) memmap[VIRT_PCIE_ECAM].base); 830 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 831 FDT_PCI_ADDR_CELLS); 832 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 833 FDT_PCI_INT_CELLS); 834 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 835 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 836 "pci-host-ecam-generic"); 837 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 838 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 839 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 840 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 841 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 842 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 843 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 844 } 845 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 846 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 847 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 848 1, FDT_PCI_RANGE_IOPORT, 2, 0, 849 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 850 1, FDT_PCI_RANGE_MMIO, 851 2, memmap[VIRT_PCIE_MMIO].base, 852 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 853 1, FDT_PCI_RANGE_MMIO_64BIT, 854 2, virt_high_pcie_memmap.base, 855 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 856 857 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 858 } 859 860 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 861 uint32_t *phandle) 862 { 863 char *name; 864 uint32_t test_phandle; 865 MachineState *ms = MACHINE(s); 866 867 test_phandle = (*phandle)++; 868 name = g_strdup_printf("/soc/test@%lx", 869 (long)memmap[VIRT_TEST].base); 870 qemu_fdt_add_subnode(ms->fdt, name); 871 { 872 static const char * const compat[3] = { 873 "sifive,test1", "sifive,test0", "syscon" 874 }; 875 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 876 (char **)&compat, ARRAY_SIZE(compat)); 877 } 878 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 879 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 880 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 881 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 882 g_free(name); 883 884 name = g_strdup_printf("/reboot"); 885 qemu_fdt_add_subnode(ms->fdt, name); 886 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 887 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 888 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 889 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 890 g_free(name); 891 892 name = g_strdup_printf("/poweroff"); 893 qemu_fdt_add_subnode(ms->fdt, name); 894 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 895 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 896 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 897 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 898 g_free(name); 899 } 900 901 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 902 uint32_t irq_mmio_phandle) 903 { 904 g_autofree char *name = NULL; 905 MachineState *ms = MACHINE(s); 906 907 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 908 qemu_fdt_add_subnode(ms->fdt, name); 909 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 910 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 911 0x0, memmap[VIRT_UART0].base, 912 0x0, memmap[VIRT_UART0].size); 913 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 914 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 915 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 916 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 917 } else { 918 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 919 } 920 921 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 922 } 923 924 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 925 uint32_t irq_mmio_phandle) 926 { 927 g_autofree char *name = NULL; 928 MachineState *ms = MACHINE(s); 929 930 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 931 qemu_fdt_add_subnode(ms->fdt, name); 932 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 933 "google,goldfish-rtc"); 934 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 935 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 936 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 937 irq_mmio_phandle); 938 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 939 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 940 } else { 941 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 942 } 943 } 944 945 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 946 { 947 MachineState *ms = MACHINE(s); 948 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 949 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 950 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 951 952 qemu_fdt_add_subnode(ms->fdt, name); 953 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 954 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 955 2, flashbase, 2, flashsize, 956 2, flashbase + flashsize, 2, flashsize); 957 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 958 } 959 960 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 961 { 962 MachineState *ms = MACHINE(s); 963 hwaddr base = memmap[VIRT_FW_CFG].base; 964 hwaddr size = memmap[VIRT_FW_CFG].size; 965 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 966 967 qemu_fdt_add_subnode(ms->fdt, nodename); 968 qemu_fdt_setprop_string(ms->fdt, nodename, 969 "compatible", "qemu,fw-cfg-mmio"); 970 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 971 2, base, 2, size); 972 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 973 } 974 975 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 976 { 977 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 978 void *fdt = MACHINE(s)->fdt; 979 uint32_t iommu_phandle; 980 g_autofree char *iommu_node = NULL; 981 g_autofree char *pci_node = NULL; 982 983 pci_node = g_strdup_printf("/soc/pci@%lx", 984 (long) virt_memmap[VIRT_PCIE_ECAM].base); 985 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 986 PCI_SLOT(bdf), PCI_FUNC(bdf)); 987 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 988 989 qemu_fdt_add_subnode(fdt, iommu_node); 990 991 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 992 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 993 1, bdf << 8, 1, 0, 1, 0, 994 1, 0, 1, 0); 995 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 996 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 997 998 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 999 0, iommu_phandle, 0, bdf, 1000 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1001 } 1002 1003 static void finalize_fdt(RISCVVirtState *s) 1004 { 1005 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1006 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1007 1008 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1009 &irq_pcie_phandle, &irq_virtio_phandle, 1010 &msi_pcie_phandle); 1011 1012 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1013 1014 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1015 1016 create_fdt_reset(s, virt_memmap, &phandle); 1017 1018 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1019 1020 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1021 } 1022 1023 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1024 { 1025 MachineState *ms = MACHINE(s); 1026 uint8_t rng_seed[32]; 1027 g_autofree char *name = NULL; 1028 1029 ms->fdt = create_device_tree(&s->fdt_size); 1030 if (!ms->fdt) { 1031 error_report("create_device_tree() failed"); 1032 exit(1); 1033 } 1034 1035 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1036 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1037 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1038 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1039 1040 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1041 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1042 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1043 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1044 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1045 1046 /* 1047 * The "/soc/pci@..." node is needed for PCIE hotplugs 1048 * that might happen before finalize_fdt(). 1049 */ 1050 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1051 qemu_fdt_add_subnode(ms->fdt, name); 1052 1053 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1054 1055 /* Pass seed to RNG */ 1056 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1057 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1058 rng_seed, sizeof(rng_seed)); 1059 1060 create_fdt_flash(s, memmap); 1061 create_fdt_fw_cfg(s, memmap); 1062 create_fdt_pmu(s); 1063 } 1064 1065 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1066 DeviceState *irqchip, 1067 RISCVVirtState *s) 1068 { 1069 DeviceState *dev; 1070 MemoryRegion *ecam_alias, *ecam_reg; 1071 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1072 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1073 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1074 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1075 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1076 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1077 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1078 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1079 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1080 qemu_irq irq; 1081 int i; 1082 1083 dev = qdev_new(TYPE_GPEX_HOST); 1084 1085 /* Set GPEX object properties for the virt machine */ 1086 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1087 ecam_base, NULL); 1088 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1089 ecam_size, NULL); 1090 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1091 PCI_HOST_BELOW_4G_MMIO_BASE, 1092 mmio_base, NULL); 1093 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1094 mmio_size, NULL); 1095 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1096 PCI_HOST_ABOVE_4G_MMIO_BASE, 1097 high_mmio_base, NULL); 1098 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1099 high_mmio_size, NULL); 1100 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1101 pio_base, NULL); 1102 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1103 pio_size, NULL); 1104 1105 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1106 1107 ecam_alias = g_new0(MemoryRegion, 1); 1108 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1109 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1110 ecam_reg, 0, ecam_size); 1111 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1112 1113 mmio_alias = g_new0(MemoryRegion, 1); 1114 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1115 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1116 mmio_reg, mmio_base, mmio_size); 1117 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1118 1119 /* Map high MMIO space */ 1120 high_mmio_alias = g_new0(MemoryRegion, 1); 1121 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1122 mmio_reg, high_mmio_base, high_mmio_size); 1123 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1124 high_mmio_alias); 1125 1126 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1127 1128 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1129 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1130 1131 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1132 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1133 } 1134 1135 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1136 return dev; 1137 } 1138 1139 static FWCfgState *create_fw_cfg(const MachineState *ms) 1140 { 1141 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1142 FWCfgState *fw_cfg; 1143 1144 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1145 &address_space_memory); 1146 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1147 1148 return fw_cfg; 1149 } 1150 1151 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1152 int base_hartid, int hart_count) 1153 { 1154 DeviceState *ret; 1155 g_autofree char *plic_hart_config = NULL; 1156 1157 /* Per-socket PLIC hart topology configuration string */ 1158 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1159 1160 /* Per-socket PLIC */ 1161 ret = sifive_plic_create( 1162 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1163 plic_hart_config, hart_count, base_hartid, 1164 VIRT_IRQCHIP_NUM_SOURCES, 1165 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1166 VIRT_PLIC_PRIORITY_BASE, 1167 VIRT_PLIC_PENDING_BASE, 1168 VIRT_PLIC_ENABLE_BASE, 1169 VIRT_PLIC_ENABLE_STRIDE, 1170 VIRT_PLIC_CONTEXT_BASE, 1171 VIRT_PLIC_CONTEXT_STRIDE, 1172 memmap[VIRT_PLIC].size); 1173 1174 return ret; 1175 } 1176 1177 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1178 const MemMapEntry *memmap, int socket, 1179 int base_hartid, int hart_count) 1180 { 1181 int i; 1182 hwaddr addr; 1183 uint32_t guest_bits; 1184 DeviceState *aplic_s = NULL; 1185 DeviceState *aplic_m = NULL; 1186 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1187 1188 if (msimode) { 1189 if (!kvm_enabled()) { 1190 /* Per-socket M-level IMSICs */ 1191 addr = memmap[VIRT_IMSIC_M].base + 1192 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1193 for (i = 0; i < hart_count; i++) { 1194 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1195 base_hartid + i, true, 1, 1196 VIRT_IRQCHIP_NUM_MSIS); 1197 } 1198 } 1199 1200 /* Per-socket S-level IMSICs */ 1201 guest_bits = imsic_num_bits(aia_guests + 1); 1202 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1203 for (i = 0; i < hart_count; i++) { 1204 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1205 base_hartid + i, false, 1 + aia_guests, 1206 VIRT_IRQCHIP_NUM_MSIS); 1207 } 1208 } 1209 1210 if (!kvm_enabled()) { 1211 /* Per-socket M-level APLIC */ 1212 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1213 socket * memmap[VIRT_APLIC_M].size, 1214 memmap[VIRT_APLIC_M].size, 1215 (msimode) ? 0 : base_hartid, 1216 (msimode) ? 0 : hart_count, 1217 VIRT_IRQCHIP_NUM_SOURCES, 1218 VIRT_IRQCHIP_NUM_PRIO_BITS, 1219 msimode, true, NULL); 1220 } 1221 1222 /* Per-socket S-level APLIC */ 1223 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1224 socket * memmap[VIRT_APLIC_S].size, 1225 memmap[VIRT_APLIC_S].size, 1226 (msimode) ? 0 : base_hartid, 1227 (msimode) ? 0 : hart_count, 1228 VIRT_IRQCHIP_NUM_SOURCES, 1229 VIRT_IRQCHIP_NUM_PRIO_BITS, 1230 msimode, false, aplic_m); 1231 1232 return kvm_enabled() ? aplic_s : aplic_m; 1233 } 1234 1235 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1236 { 1237 DeviceState *dev; 1238 SysBusDevice *sysbus; 1239 const MemMapEntry *memmap = virt_memmap; 1240 int i; 1241 MemoryRegion *sysmem = get_system_memory(); 1242 1243 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1244 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1245 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1246 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1247 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1248 s->platform_bus_dev = dev; 1249 1250 sysbus = SYS_BUS_DEVICE(dev); 1251 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1252 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1253 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1254 } 1255 1256 memory_region_add_subregion(sysmem, 1257 memmap[VIRT_PLATFORM_BUS].base, 1258 sysbus_mmio_get_region(sysbus, 0)); 1259 } 1260 1261 static void virt_build_smbios(RISCVVirtState *s) 1262 { 1263 MachineClass *mc = MACHINE_GET_CLASS(s); 1264 MachineState *ms = MACHINE(s); 1265 uint8_t *smbios_tables, *smbios_anchor; 1266 size_t smbios_tables_len, smbios_anchor_len; 1267 struct smbios_phys_mem_area mem_array; 1268 const char *product = "QEMU Virtual Machine"; 1269 1270 if (kvm_enabled()) { 1271 product = "KVM Virtual Machine"; 1272 } 1273 1274 smbios_set_defaults("QEMU", product, mc->name, false, 1275 true, SMBIOS_ENTRY_POINT_TYPE_64); 1276 1277 if (riscv_is_32bit(&s->soc[0])) { 1278 smbios_set_default_processor_family(0x200); 1279 } else { 1280 smbios_set_default_processor_family(0x201); 1281 } 1282 1283 /* build the array of physical mem area from base_memmap */ 1284 mem_array.address = s->memmap[VIRT_DRAM].base; 1285 mem_array.length = ms->ram_size; 1286 1287 smbios_get_tables(ms, &mem_array, 1, 1288 &smbios_tables, &smbios_tables_len, 1289 &smbios_anchor, &smbios_anchor_len, 1290 &error_fatal); 1291 1292 if (smbios_anchor) { 1293 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1294 smbios_tables, smbios_tables_len); 1295 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1296 smbios_anchor, smbios_anchor_len); 1297 } 1298 } 1299 1300 static void virt_machine_done(Notifier *notifier, void *data) 1301 { 1302 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1303 machine_done); 1304 const MemMapEntry *memmap = virt_memmap; 1305 MachineState *machine = MACHINE(s); 1306 target_ulong start_addr = memmap[VIRT_DRAM].base; 1307 target_ulong firmware_end_addr, kernel_start_addr; 1308 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1309 uint64_t fdt_load_addr; 1310 uint64_t kernel_entry = 0; 1311 BlockBackend *pflash_blk0; 1312 1313 /* 1314 * An user provided dtb must include everything, including 1315 * dynamic sysbus devices. Our FDT needs to be finalized. 1316 */ 1317 if (machine->dtb == NULL) { 1318 finalize_fdt(s); 1319 } 1320 1321 /* 1322 * Only direct boot kernel is currently supported for KVM VM, 1323 * so the "-bios" parameter is not supported when KVM is enabled. 1324 */ 1325 if (kvm_enabled()) { 1326 if (machine->firmware) { 1327 if (strcmp(machine->firmware, "none")) { 1328 error_report("Machine mode firmware is not supported in " 1329 "combination with KVM."); 1330 exit(1); 1331 } 1332 } else { 1333 machine->firmware = g_strdup("none"); 1334 } 1335 } 1336 1337 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1338 start_addr, NULL); 1339 1340 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1341 if (pflash_blk0) { 1342 if (machine->firmware && !strcmp(machine->firmware, "none") && 1343 !kvm_enabled()) { 1344 /* 1345 * Pflash was supplied but bios is none and not KVM guest, 1346 * let's overwrite the address we jump to after reset to 1347 * the base of the flash. 1348 */ 1349 start_addr = virt_memmap[VIRT_FLASH].base; 1350 } else { 1351 /* 1352 * Pflash was supplied but either KVM guest or bios is not none. 1353 * In this case, base of the flash would contain S-mode payload. 1354 */ 1355 riscv_setup_firmware_boot(machine); 1356 kernel_entry = virt_memmap[VIRT_FLASH].base; 1357 } 1358 } 1359 1360 if (machine->kernel_filename && !kernel_entry) { 1361 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1362 firmware_end_addr); 1363 1364 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1365 kernel_start_addr, true, NULL); 1366 } 1367 1368 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1369 memmap[VIRT_DRAM].size, 1370 machine); 1371 riscv_load_fdt(fdt_load_addr, machine->fdt); 1372 1373 /* load the reset vector */ 1374 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1375 virt_memmap[VIRT_MROM].base, 1376 virt_memmap[VIRT_MROM].size, kernel_entry, 1377 fdt_load_addr); 1378 1379 /* 1380 * Only direct boot kernel is currently supported for KVM VM, 1381 * So here setup kernel start address and fdt address. 1382 * TODO:Support firmware loading and integrate to TCG start 1383 */ 1384 if (kvm_enabled()) { 1385 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1386 } 1387 1388 virt_build_smbios(s); 1389 1390 if (virt_is_acpi_enabled(s)) { 1391 virt_acpi_setup(s); 1392 } 1393 } 1394 1395 static void virt_machine_init(MachineState *machine) 1396 { 1397 const MemMapEntry *memmap = virt_memmap; 1398 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1399 MemoryRegion *system_memory = get_system_memory(); 1400 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1401 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1402 int i, base_hartid, hart_count; 1403 int socket_count = riscv_socket_count(machine); 1404 1405 /* Check socket count limit */ 1406 if (VIRT_SOCKETS_MAX < socket_count) { 1407 error_report("number of sockets/nodes should be less than %d", 1408 VIRT_SOCKETS_MAX); 1409 exit(1); 1410 } 1411 1412 if (!tcg_enabled() && s->have_aclint) { 1413 error_report("'aclint' is only available with TCG acceleration"); 1414 exit(1); 1415 } 1416 1417 /* Initialize sockets */ 1418 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1419 for (i = 0; i < socket_count; i++) { 1420 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1421 1422 if (!riscv_socket_check_hartids(machine, i)) { 1423 error_report("discontinuous hartids in socket%d", i); 1424 exit(1); 1425 } 1426 1427 base_hartid = riscv_socket_first_hartid(machine, i); 1428 if (base_hartid < 0) { 1429 error_report("can't find hartid base for socket%d", i); 1430 exit(1); 1431 } 1432 1433 hart_count = riscv_socket_hart_count(machine, i); 1434 if (hart_count < 0) { 1435 error_report("can't find hart count for socket%d", i); 1436 exit(1); 1437 } 1438 1439 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1440 TYPE_RISCV_HART_ARRAY); 1441 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1442 machine->cpu_type, &error_abort); 1443 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1444 base_hartid, &error_abort); 1445 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1446 hart_count, &error_abort); 1447 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1448 1449 if (tcg_enabled()) { 1450 if (s->have_aclint) { 1451 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1452 /* Per-socket ACLINT MTIMER */ 1453 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1454 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1455 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1456 base_hartid, hart_count, 1457 RISCV_ACLINT_DEFAULT_MTIMECMP, 1458 RISCV_ACLINT_DEFAULT_MTIME, 1459 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1460 } else { 1461 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1462 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1463 i * memmap[VIRT_CLINT].size, 1464 base_hartid, hart_count, false); 1465 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1466 i * memmap[VIRT_CLINT].size + 1467 RISCV_ACLINT_SWI_SIZE, 1468 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1469 base_hartid, hart_count, 1470 RISCV_ACLINT_DEFAULT_MTIMECMP, 1471 RISCV_ACLINT_DEFAULT_MTIME, 1472 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1473 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1474 i * memmap[VIRT_ACLINT_SSWI].size, 1475 base_hartid, hart_count, true); 1476 } 1477 } else { 1478 /* Per-socket SiFive CLINT */ 1479 riscv_aclint_swi_create( 1480 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1481 base_hartid, hart_count, false); 1482 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1483 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1484 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1485 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1486 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1487 } 1488 } 1489 1490 /* Per-socket interrupt controller */ 1491 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1492 s->irqchip[i] = virt_create_plic(memmap, i, 1493 base_hartid, hart_count); 1494 } else { 1495 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1496 memmap, i, base_hartid, 1497 hart_count); 1498 } 1499 1500 /* Try to use different IRQCHIP instance based device type */ 1501 if (i == 0) { 1502 mmio_irqchip = s->irqchip[i]; 1503 virtio_irqchip = s->irqchip[i]; 1504 pcie_irqchip = s->irqchip[i]; 1505 } 1506 if (i == 1) { 1507 virtio_irqchip = s->irqchip[i]; 1508 pcie_irqchip = s->irqchip[i]; 1509 } 1510 if (i == 2) { 1511 pcie_irqchip = s->irqchip[i]; 1512 } 1513 } 1514 1515 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1516 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1517 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1518 memmap[VIRT_APLIC_S].base, 1519 memmap[VIRT_IMSIC_S].base, 1520 s->aia_guests); 1521 } 1522 1523 if (riscv_is_32bit(&s->soc[0])) { 1524 #if HOST_LONG_BITS == 64 1525 /* limit RAM size in a 32-bit system */ 1526 if (machine->ram_size > 10 * GiB) { 1527 machine->ram_size = 10 * GiB; 1528 error_report("Limiting RAM size to 10 GiB"); 1529 } 1530 #endif 1531 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1532 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1533 } else { 1534 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1535 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1536 virt_high_pcie_memmap.base = 1537 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1538 } 1539 1540 s->memmap = virt_memmap; 1541 1542 /* register system main memory (actual RAM) */ 1543 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1544 machine->ram); 1545 1546 /* boot rom */ 1547 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1548 memmap[VIRT_MROM].size, &error_fatal); 1549 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1550 mask_rom); 1551 1552 /* 1553 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1554 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1555 */ 1556 s->fw_cfg = create_fw_cfg(machine); 1557 rom_set_fw(s->fw_cfg); 1558 1559 /* SiFive Test MMIO device */ 1560 sifive_test_create(memmap[VIRT_TEST].base); 1561 1562 /* VirtIO MMIO devices */ 1563 for (i = 0; i < VIRTIO_COUNT; i++) { 1564 sysbus_create_simple("virtio-mmio", 1565 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1566 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1567 } 1568 1569 gpex_pcie_init(system_memory, pcie_irqchip, s); 1570 1571 create_platform_bus(s, mmio_irqchip); 1572 1573 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1574 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1575 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1576 1577 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1578 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1579 1580 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1581 /* Map legacy -drive if=pflash to machine properties */ 1582 pflash_cfi01_legacy_drive(s->flash[i], 1583 drive_get(IF_PFLASH, 0, i)); 1584 } 1585 virt_flash_map(s, system_memory); 1586 1587 /* load/create device tree */ 1588 if (machine->dtb) { 1589 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1590 if (!machine->fdt) { 1591 error_report("load_device_tree() failed"); 1592 exit(1); 1593 } 1594 } else { 1595 create_fdt(s, memmap); 1596 } 1597 1598 s->machine_done.notify = virt_machine_done; 1599 qemu_add_machine_init_done_notifier(&s->machine_done); 1600 } 1601 1602 static void virt_machine_instance_init(Object *obj) 1603 { 1604 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1605 1606 virt_flash_create(s); 1607 1608 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1609 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1610 s->acpi = ON_OFF_AUTO_AUTO; 1611 } 1612 1613 static char *virt_get_aia_guests(Object *obj, Error **errp) 1614 { 1615 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1616 char val[32]; 1617 1618 sprintf(val, "%d", s->aia_guests); 1619 return g_strdup(val); 1620 } 1621 1622 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1623 { 1624 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1625 1626 s->aia_guests = atoi(val); 1627 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1628 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1629 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1630 VIRT_IRQCHIP_MAX_GUESTS); 1631 } 1632 } 1633 1634 static char *virt_get_aia(Object *obj, Error **errp) 1635 { 1636 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1637 const char *val; 1638 1639 switch (s->aia_type) { 1640 case VIRT_AIA_TYPE_APLIC: 1641 val = "aplic"; 1642 break; 1643 case VIRT_AIA_TYPE_APLIC_IMSIC: 1644 val = "aplic-imsic"; 1645 break; 1646 default: 1647 val = "none"; 1648 break; 1649 }; 1650 1651 return g_strdup(val); 1652 } 1653 1654 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1655 { 1656 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1657 1658 if (!strcmp(val, "none")) { 1659 s->aia_type = VIRT_AIA_TYPE_NONE; 1660 } else if (!strcmp(val, "aplic")) { 1661 s->aia_type = VIRT_AIA_TYPE_APLIC; 1662 } else if (!strcmp(val, "aplic-imsic")) { 1663 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1664 } else { 1665 error_setg(errp, "Invalid AIA interrupt controller type"); 1666 error_append_hint(errp, "Valid values are none, aplic, and " 1667 "aplic-imsic.\n"); 1668 } 1669 } 1670 1671 static bool virt_get_aclint(Object *obj, Error **errp) 1672 { 1673 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1674 1675 return s->have_aclint; 1676 } 1677 1678 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1679 { 1680 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1681 1682 s->have_aclint = value; 1683 } 1684 1685 bool virt_is_acpi_enabled(RISCVVirtState *s) 1686 { 1687 return s->acpi != ON_OFF_AUTO_OFF; 1688 } 1689 1690 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1691 void *opaque, Error **errp) 1692 { 1693 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1694 OnOffAuto acpi = s->acpi; 1695 1696 visit_type_OnOffAuto(v, name, &acpi, errp); 1697 } 1698 1699 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1700 void *opaque, Error **errp) 1701 { 1702 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1703 1704 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1705 } 1706 1707 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1708 DeviceState *dev) 1709 { 1710 MachineClass *mc = MACHINE_GET_CLASS(machine); 1711 1712 if (device_is_dynamic_sysbus(mc, dev) || 1713 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1714 return HOTPLUG_HANDLER(machine); 1715 } 1716 return NULL; 1717 } 1718 1719 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1720 DeviceState *dev, Error **errp) 1721 { 1722 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1723 1724 if (s->platform_bus_dev) { 1725 MachineClass *mc = MACHINE_GET_CLASS(s); 1726 1727 if (device_is_dynamic_sysbus(mc, dev)) { 1728 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1729 SYS_BUS_DEVICE(dev)); 1730 } 1731 } 1732 1733 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1734 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1735 } 1736 } 1737 1738 static void virt_machine_class_init(ObjectClass *oc, void *data) 1739 { 1740 char str[128]; 1741 MachineClass *mc = MACHINE_CLASS(oc); 1742 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1743 1744 mc->desc = "RISC-V VirtIO board"; 1745 mc->init = virt_machine_init; 1746 mc->max_cpus = VIRT_CPUS_MAX; 1747 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1748 mc->pci_allow_0_address = true; 1749 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1750 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1751 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1752 mc->numa_mem_supported = true; 1753 /* platform instead of architectural choice */ 1754 mc->cpu_cluster_has_numa_boundary = true; 1755 mc->default_ram_id = "riscv_virt_board.ram"; 1756 assert(!mc->get_hotplug_handler); 1757 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1758 1759 hc->plug = virt_machine_device_plug_cb; 1760 1761 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1762 #ifdef CONFIG_TPM 1763 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1764 #endif 1765 1766 1767 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1768 virt_set_aclint); 1769 object_class_property_set_description(oc, "aclint", 1770 "(TCG only) Set on/off to " 1771 "enable/disable emulating " 1772 "ACLINT devices"); 1773 1774 object_class_property_add_str(oc, "aia", virt_get_aia, 1775 virt_set_aia); 1776 object_class_property_set_description(oc, "aia", 1777 "Set type of AIA interrupt " 1778 "controller. Valid values are " 1779 "none, aplic, and aplic-imsic."); 1780 1781 object_class_property_add_str(oc, "aia-guests", 1782 virt_get_aia_guests, 1783 virt_set_aia_guests); 1784 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1785 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1786 object_class_property_set_description(oc, "aia-guests", str); 1787 object_class_property_add(oc, "acpi", "OnOffAuto", 1788 virt_get_acpi, virt_set_acpi, 1789 NULL, NULL); 1790 object_class_property_set_description(oc, "acpi", 1791 "Enable ACPI"); 1792 } 1793 1794 static const TypeInfo virt_machine_typeinfo = { 1795 .name = MACHINE_TYPE_NAME("virt"), 1796 .parent = TYPE_MACHINE, 1797 .class_init = virt_machine_class_init, 1798 .instance_init = virt_machine_instance_init, 1799 .instance_size = sizeof(RISCVVirtState), 1800 .interfaces = (InterfaceInfo[]) { 1801 { TYPE_HOTPLUG_HANDLER }, 1802 { } 1803 }, 1804 }; 1805 1806 static void virt_machine_init_register_types(void) 1807 { 1808 type_register_static(&virt_machine_typeinfo); 1809 } 1810 1811 type_init(virt_machine_init_register_types) 1812