1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial-mm.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/iommu.h" 36 #include "hw/riscv/riscv-iommu-bits.h" 37 #include "hw/riscv/virt.h" 38 #include "hw/riscv/boot.h" 39 #include "hw/riscv/numa.h" 40 #include "kvm/kvm_riscv.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/intc/riscv_aclint.h" 43 #include "hw/intc/riscv_aplic.h" 44 #include "hw/intc/sifive_plic.h" 45 #include "hw/misc/sifive_test.h" 46 #include "hw/platform-bus.h" 47 #include "chardev/char.h" 48 #include "sysemu/device_tree.h" 49 #include "sysemu/sysemu.h" 50 #include "sysemu/tcg.h" 51 #include "sysemu/kvm.h" 52 #include "sysemu/tpm.h" 53 #include "sysemu/qtest.h" 54 #include "hw/pci/pci.h" 55 #include "hw/pci-host/gpex.h" 56 #include "hw/display/ramfb.h" 57 #include "hw/acpi/aml-build.h" 58 #include "qapi/qapi-visit-common.h" 59 #include "hw/virtio/virtio-iommu.h" 60 61 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 62 static bool virt_use_kvm_aia(RISCVVirtState *s) 63 { 64 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 65 } 66 67 static bool virt_aclint_allowed(void) 68 { 69 return tcg_enabled() || qtest_enabled(); 70 } 71 72 static const MemMapEntry virt_memmap[] = { 73 [VIRT_DEBUG] = { 0x0, 0x100 }, 74 [VIRT_MROM] = { 0x1000, 0xf000 }, 75 [VIRT_TEST] = { 0x100000, 0x1000 }, 76 [VIRT_RTC] = { 0x101000, 0x1000 }, 77 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 78 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 79 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 80 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, 81 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 82 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 83 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 84 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 85 [VIRT_UART0] = { 0x10000000, 0x100 }, 86 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 87 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 88 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 89 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 90 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 91 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 92 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 93 [VIRT_DRAM] = { 0x80000000, 0x0 }, 94 }; 95 96 /* PCIe high mmio is fixed for RV32 */ 97 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 98 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 99 100 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 101 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 102 103 static MemMapEntry virt_high_pcie_memmap; 104 105 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 106 107 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 108 const char *name, 109 const char *alias_prop_name) 110 { 111 /* 112 * Create a single flash device. We use the same parameters as 113 * the flash devices on the ARM virt board. 114 */ 115 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 116 117 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 118 qdev_prop_set_uint8(dev, "width", 4); 119 qdev_prop_set_uint8(dev, "device-width", 2); 120 qdev_prop_set_bit(dev, "big-endian", false); 121 qdev_prop_set_uint16(dev, "id0", 0x89); 122 qdev_prop_set_uint16(dev, "id1", 0x18); 123 qdev_prop_set_uint16(dev, "id2", 0x00); 124 qdev_prop_set_uint16(dev, "id3", 0x00); 125 qdev_prop_set_string(dev, "name", name); 126 127 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 128 object_property_add_alias(OBJECT(s), alias_prop_name, 129 OBJECT(dev), "drive"); 130 131 return PFLASH_CFI01(dev); 132 } 133 134 static void virt_flash_create(RISCVVirtState *s) 135 { 136 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 137 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 138 } 139 140 static void virt_flash_map1(PFlashCFI01 *flash, 141 hwaddr base, hwaddr size, 142 MemoryRegion *sysmem) 143 { 144 DeviceState *dev = DEVICE(flash); 145 146 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 147 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 148 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 149 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 150 151 memory_region_add_subregion(sysmem, base, 152 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 153 0)); 154 } 155 156 static void virt_flash_map(RISCVVirtState *s, 157 MemoryRegion *sysmem) 158 { 159 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 160 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 161 162 virt_flash_map1(s->flash[0], flashbase, flashsize, 163 sysmem); 164 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 165 sysmem); 166 } 167 168 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 169 uint32_t irqchip_phandle) 170 { 171 int pin, dev; 172 uint32_t irq_map_stride = 0; 173 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 174 FDT_MAX_INT_MAP_WIDTH] = {}; 175 uint32_t *irq_map = full_irq_map; 176 177 /* This code creates a standard swizzle of interrupts such that 178 * each device's first interrupt is based on it's PCI_SLOT number. 179 * (See pci_swizzle_map_irq_fn()) 180 * 181 * We only need one entry per interrupt in the table (not one per 182 * possible slot) seeing the interrupt-map-mask will allow the table 183 * to wrap to any number of devices. 184 */ 185 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 186 int devfn = dev * 0x8; 187 188 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 189 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 190 int i = 0; 191 192 /* Fill PCI address cells */ 193 irq_map[i] = cpu_to_be32(devfn << 8); 194 i += FDT_PCI_ADDR_CELLS; 195 196 /* Fill PCI Interrupt cells */ 197 irq_map[i] = cpu_to_be32(pin + 1); 198 i += FDT_PCI_INT_CELLS; 199 200 /* Fill interrupt controller phandle and cells */ 201 irq_map[i++] = cpu_to_be32(irqchip_phandle); 202 irq_map[i++] = cpu_to_be32(irq_nr); 203 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 204 irq_map[i++] = cpu_to_be32(0x4); 205 } 206 207 if (!irq_map_stride) { 208 irq_map_stride = i; 209 } 210 irq_map += irq_map_stride; 211 } 212 } 213 214 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 215 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 216 irq_map_stride * sizeof(uint32_t)); 217 218 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 219 0x1800, 0, 0, 0x7); 220 } 221 222 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 223 char *clust_name, uint32_t *phandle, 224 uint32_t *intc_phandles) 225 { 226 int cpu; 227 uint32_t cpu_phandle; 228 MachineState *ms = MACHINE(s); 229 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 230 uint8_t satp_mode_max; 231 232 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 233 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 234 g_autofree char *cpu_name = NULL; 235 g_autofree char *core_name = NULL; 236 g_autofree char *intc_name = NULL; 237 g_autofree char *sv_name = NULL; 238 239 cpu_phandle = (*phandle)++; 240 241 cpu_name = g_strdup_printf("/cpus/cpu@%d", 242 s->soc[socket].hartid_base + cpu); 243 qemu_fdt_add_subnode(ms->fdt, cpu_name); 244 245 if (cpu_ptr->cfg.satp_mode.supported != 0) { 246 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 247 sv_name = g_strdup_printf("riscv,%s", 248 satp_mode_str(satp_mode_max, is_32_bit)); 249 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 250 } 251 252 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 253 254 if (cpu_ptr->cfg.ext_zicbom) { 255 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 256 cpu_ptr->cfg.cbom_blocksize); 257 } 258 259 if (cpu_ptr->cfg.ext_zicboz) { 260 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 261 cpu_ptr->cfg.cboz_blocksize); 262 } 263 264 if (cpu_ptr->cfg.ext_zicbop) { 265 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 266 cpu_ptr->cfg.cbop_blocksize); 267 } 268 269 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 271 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 272 s->soc[socket].hartid_base + cpu); 273 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 274 riscv_socket_fdt_write_id(ms, cpu_name, socket); 275 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 276 277 intc_phandles[cpu] = (*phandle)++; 278 279 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 280 qemu_fdt_add_subnode(ms->fdt, intc_name); 281 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 282 intc_phandles[cpu]); 283 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 284 "riscv,cpu-intc"); 285 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 286 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 287 288 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 289 qemu_fdt_add_subnode(ms->fdt, core_name); 290 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 291 } 292 } 293 294 static void create_fdt_socket_memory(RISCVVirtState *s, 295 const MemMapEntry *memmap, int socket) 296 { 297 g_autofree char *mem_name = NULL; 298 uint64_t addr, size; 299 MachineState *ms = MACHINE(s); 300 301 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 302 size = riscv_socket_mem_size(ms, socket); 303 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 304 qemu_fdt_add_subnode(ms->fdt, mem_name); 305 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 306 addr >> 32, addr, size >> 32, size); 307 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 308 riscv_socket_fdt_write_id(ms, mem_name, socket); 309 } 310 311 static void create_fdt_socket_clint(RISCVVirtState *s, 312 const MemMapEntry *memmap, int socket, 313 uint32_t *intc_phandles) 314 { 315 int cpu; 316 g_autofree char *clint_name = NULL; 317 g_autofree uint32_t *clint_cells = NULL; 318 unsigned long clint_addr; 319 MachineState *ms = MACHINE(s); 320 static const char * const clint_compat[2] = { 321 "sifive,clint0", "riscv,clint0" 322 }; 323 324 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 325 326 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 327 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 328 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 329 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 330 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 331 } 332 333 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 334 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 335 qemu_fdt_add_subnode(ms->fdt, clint_name); 336 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 337 (char **)&clint_compat, 338 ARRAY_SIZE(clint_compat)); 339 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 340 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 341 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 342 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 343 riscv_socket_fdt_write_id(ms, clint_name, socket); 344 } 345 346 static void create_fdt_socket_aclint(RISCVVirtState *s, 347 const MemMapEntry *memmap, int socket, 348 uint32_t *intc_phandles) 349 { 350 int cpu; 351 char *name; 352 unsigned long addr, size; 353 uint32_t aclint_cells_size; 354 g_autofree uint32_t *aclint_mswi_cells = NULL; 355 g_autofree uint32_t *aclint_sswi_cells = NULL; 356 g_autofree uint32_t *aclint_mtimer_cells = NULL; 357 MachineState *ms = MACHINE(s); 358 359 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 360 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 361 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 362 363 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 364 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 365 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 366 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 367 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 368 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 369 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 370 } 371 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 372 373 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 374 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 375 name = g_strdup_printf("/soc/mswi@%lx", addr); 376 qemu_fdt_add_subnode(ms->fdt, name); 377 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 378 "riscv,aclint-mswi"); 379 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 380 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 381 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 382 aclint_mswi_cells, aclint_cells_size); 383 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 384 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 385 riscv_socket_fdt_write_id(ms, name, socket); 386 g_free(name); 387 } 388 389 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 390 addr = memmap[VIRT_CLINT].base + 391 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 392 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 393 } else { 394 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 395 (memmap[VIRT_CLINT].size * socket); 396 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 397 } 398 name = g_strdup_printf("/soc/mtimer@%lx", addr); 399 qemu_fdt_add_subnode(ms->fdt, name); 400 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 401 "riscv,aclint-mtimer"); 402 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 403 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 404 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 405 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 406 0x0, RISCV_ACLINT_DEFAULT_MTIME); 407 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 408 aclint_mtimer_cells, aclint_cells_size); 409 riscv_socket_fdt_write_id(ms, name, socket); 410 g_free(name); 411 412 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 413 addr = memmap[VIRT_ACLINT_SSWI].base + 414 (memmap[VIRT_ACLINT_SSWI].size * socket); 415 name = g_strdup_printf("/soc/sswi@%lx", addr); 416 qemu_fdt_add_subnode(ms->fdt, name); 417 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 418 "riscv,aclint-sswi"); 419 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 420 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 421 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 422 aclint_sswi_cells, aclint_cells_size); 423 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 424 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 425 riscv_socket_fdt_write_id(ms, name, socket); 426 g_free(name); 427 } 428 } 429 430 static void create_fdt_socket_plic(RISCVVirtState *s, 431 const MemMapEntry *memmap, int socket, 432 uint32_t *phandle, uint32_t *intc_phandles, 433 uint32_t *plic_phandles) 434 { 435 int cpu; 436 g_autofree char *plic_name = NULL; 437 g_autofree uint32_t *plic_cells; 438 unsigned long plic_addr; 439 MachineState *ms = MACHINE(s); 440 static const char * const plic_compat[2] = { 441 "sifive,plic-1.0.0", "riscv,plic0" 442 }; 443 444 plic_phandles[socket] = (*phandle)++; 445 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 446 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 447 qemu_fdt_add_subnode(ms->fdt, plic_name); 448 qemu_fdt_setprop_cell(ms->fdt, plic_name, 449 "#interrupt-cells", FDT_PLIC_INT_CELLS); 450 qemu_fdt_setprop_cell(ms->fdt, plic_name, 451 "#address-cells", FDT_PLIC_ADDR_CELLS); 452 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 453 (char **)&plic_compat, 454 ARRAY_SIZE(plic_compat)); 455 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 456 457 if (kvm_enabled()) { 458 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 459 460 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 461 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 462 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 463 } 464 465 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 466 plic_cells, 467 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 468 } else { 469 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 470 471 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 472 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 473 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 474 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 475 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 476 } 477 478 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 479 plic_cells, 480 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 481 } 482 483 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 484 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 486 VIRT_IRQCHIP_NUM_SOURCES - 1); 487 riscv_socket_fdt_write_id(ms, plic_name, socket); 488 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 489 plic_phandles[socket]); 490 491 if (!socket) { 492 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 493 memmap[VIRT_PLATFORM_BUS].base, 494 memmap[VIRT_PLATFORM_BUS].size, 495 VIRT_PLATFORM_BUS_IRQ); 496 } 497 } 498 499 uint32_t imsic_num_bits(uint32_t count) 500 { 501 uint32_t ret = 0; 502 503 while (BIT(ret) < count) { 504 ret++; 505 } 506 507 return ret; 508 } 509 510 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 511 uint32_t *intc_phandles, uint32_t msi_phandle, 512 bool m_mode, uint32_t imsic_guest_bits) 513 { 514 int cpu, socket; 515 g_autofree char *imsic_name = NULL; 516 MachineState *ms = MACHINE(s); 517 int socket_count = riscv_socket_count(ms); 518 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 519 g_autofree uint32_t *imsic_cells = NULL; 520 g_autofree uint32_t *imsic_regs = NULL; 521 static const char * const imsic_compat[2] = { 522 "qemu,imsics", "riscv,imsics" 523 }; 524 525 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 526 imsic_regs = g_new0(uint32_t, socket_count * 4); 527 528 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 529 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 530 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 531 } 532 533 imsic_max_hart_per_socket = 0; 534 for (socket = 0; socket < socket_count; socket++) { 535 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 536 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 537 s->soc[socket].num_harts; 538 imsic_regs[socket * 4 + 0] = 0; 539 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 540 imsic_regs[socket * 4 + 2] = 0; 541 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 542 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 543 imsic_max_hart_per_socket = s->soc[socket].num_harts; 544 } 545 } 546 547 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 548 (unsigned long)base_addr); 549 qemu_fdt_add_subnode(ms->fdt, imsic_name); 550 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 551 (char **)&imsic_compat, 552 ARRAY_SIZE(imsic_compat)); 553 554 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 555 FDT_IMSIC_INT_CELLS); 556 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 557 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 558 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 559 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 560 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 561 socket_count * sizeof(uint32_t) * 4); 562 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 563 VIRT_IRQCHIP_NUM_MSIS); 564 565 if (imsic_guest_bits) { 566 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 567 imsic_guest_bits); 568 } 569 570 if (socket_count > 1) { 571 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 572 imsic_num_bits(imsic_max_hart_per_socket)); 573 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 574 imsic_num_bits(socket_count)); 575 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 576 IMSIC_MMIO_GROUP_MIN_SHIFT); 577 } 578 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 579 } 580 581 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 582 uint32_t *phandle, uint32_t *intc_phandles, 583 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 584 { 585 *msi_m_phandle = (*phandle)++; 586 *msi_s_phandle = (*phandle)++; 587 588 if (!kvm_enabled()) { 589 /* M-level IMSIC node */ 590 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 591 *msi_m_phandle, true, 0); 592 } 593 594 /* S-level IMSIC node */ 595 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 596 *msi_s_phandle, false, 597 imsic_num_bits(s->aia_guests + 1)); 598 599 } 600 601 /* Caller must free string after use */ 602 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 603 { 604 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 605 } 606 607 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 608 unsigned long aplic_addr, uint32_t aplic_size, 609 uint32_t msi_phandle, 610 uint32_t *intc_phandles, 611 uint32_t aplic_phandle, 612 uint32_t aplic_child_phandle, 613 bool m_mode, int num_harts) 614 { 615 int cpu; 616 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 617 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 618 MachineState *ms = MACHINE(s); 619 static const char * const aplic_compat[2] = { 620 "qemu,aplic", "riscv,aplic" 621 }; 622 623 for (cpu = 0; cpu < num_harts; cpu++) { 624 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 625 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 626 } 627 628 qemu_fdt_add_subnode(ms->fdt, aplic_name); 629 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 630 (char **)&aplic_compat, 631 ARRAY_SIZE(aplic_compat)); 632 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 633 FDT_APLIC_ADDR_CELLS); 634 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 635 "#interrupt-cells", FDT_APLIC_INT_CELLS); 636 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 637 638 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 639 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 640 aplic_cells, num_harts * sizeof(uint32_t) * 2); 641 } else { 642 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 643 } 644 645 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 646 0x0, aplic_addr, 0x0, aplic_size); 647 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 648 VIRT_IRQCHIP_NUM_SOURCES); 649 650 if (aplic_child_phandle) { 651 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 652 aplic_child_phandle); 653 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 654 aplic_child_phandle, 0x1, 655 VIRT_IRQCHIP_NUM_SOURCES); 656 /* 657 * DEPRECATED_9.1: Compat property kept temporarily 658 * to allow old firmwares to work with AIA. Do *not* 659 * use 'riscv,delegate' in new code: use 660 * 'riscv,delegation' instead. 661 */ 662 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 663 aplic_child_phandle, 0x1, 664 VIRT_IRQCHIP_NUM_SOURCES); 665 } 666 667 riscv_socket_fdt_write_id(ms, aplic_name, socket); 668 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 669 } 670 671 static void create_fdt_socket_aplic(RISCVVirtState *s, 672 const MemMapEntry *memmap, int socket, 673 uint32_t msi_m_phandle, 674 uint32_t msi_s_phandle, 675 uint32_t *phandle, 676 uint32_t *intc_phandles, 677 uint32_t *aplic_phandles, 678 int num_harts) 679 { 680 unsigned long aplic_addr; 681 MachineState *ms = MACHINE(s); 682 uint32_t aplic_m_phandle, aplic_s_phandle; 683 684 aplic_m_phandle = (*phandle)++; 685 aplic_s_phandle = (*phandle)++; 686 687 if (!kvm_enabled()) { 688 /* M-level APLIC node */ 689 aplic_addr = memmap[VIRT_APLIC_M].base + 690 (memmap[VIRT_APLIC_M].size * socket); 691 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 692 msi_m_phandle, intc_phandles, 693 aplic_m_phandle, aplic_s_phandle, 694 true, num_harts); 695 } 696 697 /* S-level APLIC node */ 698 aplic_addr = memmap[VIRT_APLIC_S].base + 699 (memmap[VIRT_APLIC_S].size * socket); 700 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 701 msi_s_phandle, intc_phandles, 702 aplic_s_phandle, 0, 703 false, num_harts); 704 705 if (!socket) { 706 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 707 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 708 memmap[VIRT_PLATFORM_BUS].base, 709 memmap[VIRT_PLATFORM_BUS].size, 710 VIRT_PLATFORM_BUS_IRQ); 711 } 712 713 aplic_phandles[socket] = aplic_s_phandle; 714 } 715 716 static void create_fdt_pmu(RISCVVirtState *s) 717 { 718 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 719 MachineState *ms = MACHINE(s); 720 RISCVCPU hart = s->soc[0].harts[0]; 721 722 qemu_fdt_add_subnode(ms->fdt, pmu_name); 723 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 724 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 725 } 726 727 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 728 uint32_t *phandle, 729 uint32_t *irq_mmio_phandle, 730 uint32_t *irq_pcie_phandle, 731 uint32_t *irq_virtio_phandle, 732 uint32_t *msi_pcie_phandle) 733 { 734 int socket, phandle_pos; 735 MachineState *ms = MACHINE(s); 736 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 737 uint32_t xplic_phandles[MAX_NODES]; 738 g_autofree uint32_t *intc_phandles = NULL; 739 int socket_count = riscv_socket_count(ms); 740 741 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 742 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 743 kvm_enabled() ? 744 kvm_riscv_get_timebase_frequency(first_cpu) : 745 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 746 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 747 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 748 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 749 750 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 751 752 phandle_pos = ms->smp.cpus; 753 for (socket = (socket_count - 1); socket >= 0; socket--) { 754 g_autofree char *clust_name = NULL; 755 phandle_pos -= s->soc[socket].num_harts; 756 757 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 758 qemu_fdt_add_subnode(ms->fdt, clust_name); 759 760 create_fdt_socket_cpus(s, socket, clust_name, phandle, 761 &intc_phandles[phandle_pos]); 762 763 create_fdt_socket_memory(s, memmap, socket); 764 765 if (virt_aclint_allowed() && s->have_aclint) { 766 create_fdt_socket_aclint(s, memmap, socket, 767 &intc_phandles[phandle_pos]); 768 } else if (tcg_enabled()) { 769 create_fdt_socket_clint(s, memmap, socket, 770 &intc_phandles[phandle_pos]); 771 } 772 } 773 774 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 775 create_fdt_imsic(s, memmap, phandle, intc_phandles, 776 &msi_m_phandle, &msi_s_phandle); 777 *msi_pcie_phandle = msi_s_phandle; 778 } 779 780 /* KVM AIA only has one APLIC instance */ 781 if (kvm_enabled() && virt_use_kvm_aia(s)) { 782 create_fdt_socket_aplic(s, memmap, 0, 783 msi_m_phandle, msi_s_phandle, phandle, 784 &intc_phandles[0], xplic_phandles, 785 ms->smp.cpus); 786 } else { 787 phandle_pos = ms->smp.cpus; 788 for (socket = (socket_count - 1); socket >= 0; socket--) { 789 phandle_pos -= s->soc[socket].num_harts; 790 791 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 792 create_fdt_socket_plic(s, memmap, socket, phandle, 793 &intc_phandles[phandle_pos], 794 xplic_phandles); 795 } else { 796 create_fdt_socket_aplic(s, memmap, socket, 797 msi_m_phandle, msi_s_phandle, phandle, 798 &intc_phandles[phandle_pos], 799 xplic_phandles, 800 s->soc[socket].num_harts); 801 } 802 } 803 } 804 805 if (kvm_enabled() && virt_use_kvm_aia(s)) { 806 *irq_mmio_phandle = xplic_phandles[0]; 807 *irq_virtio_phandle = xplic_phandles[0]; 808 *irq_pcie_phandle = xplic_phandles[0]; 809 } else { 810 for (socket = 0; socket < socket_count; socket++) { 811 if (socket == 0) { 812 *irq_mmio_phandle = xplic_phandles[socket]; 813 *irq_virtio_phandle = xplic_phandles[socket]; 814 *irq_pcie_phandle = xplic_phandles[socket]; 815 } 816 if (socket == 1) { 817 *irq_virtio_phandle = xplic_phandles[socket]; 818 *irq_pcie_phandle = xplic_phandles[socket]; 819 } 820 if (socket == 2) { 821 *irq_pcie_phandle = xplic_phandles[socket]; 822 } 823 } 824 } 825 826 riscv_socket_fdt_write_distance_matrix(ms); 827 } 828 829 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 830 uint32_t irq_virtio_phandle) 831 { 832 int i; 833 MachineState *ms = MACHINE(s); 834 835 for (i = 0; i < VIRTIO_COUNT; i++) { 836 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 837 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 838 839 qemu_fdt_add_subnode(ms->fdt, name); 840 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 841 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 842 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 843 0x0, memmap[VIRT_VIRTIO].size); 844 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 845 irq_virtio_phandle); 846 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 847 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 848 VIRTIO_IRQ + i); 849 } else { 850 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 851 VIRTIO_IRQ + i, 0x4); 852 } 853 } 854 } 855 856 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 857 uint32_t irq_pcie_phandle, 858 uint32_t msi_pcie_phandle, 859 uint32_t iommu_sys_phandle) 860 { 861 g_autofree char *name = NULL; 862 MachineState *ms = MACHINE(s); 863 864 name = g_strdup_printf("/soc/pci@%lx", 865 (long) memmap[VIRT_PCIE_ECAM].base); 866 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 867 FDT_PCI_ADDR_CELLS); 868 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 869 FDT_PCI_INT_CELLS); 870 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 871 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 872 "pci-host-ecam-generic"); 873 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 874 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 875 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 876 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 877 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 878 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 879 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 880 } 881 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 882 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 883 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 884 1, FDT_PCI_RANGE_IOPORT, 2, 0, 885 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 886 1, FDT_PCI_RANGE_MMIO, 887 2, memmap[VIRT_PCIE_MMIO].base, 888 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 889 1, FDT_PCI_RANGE_MMIO_64BIT, 890 2, virt_high_pcie_memmap.base, 891 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 892 893 if (virt_is_iommu_sys_enabled(s)) { 894 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", 895 0, iommu_sys_phandle, 0, 0, 0, 896 iommu_sys_phandle, 0, 0xffff); 897 } 898 899 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 900 } 901 902 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 903 uint32_t *phandle) 904 { 905 char *name; 906 uint32_t test_phandle; 907 MachineState *ms = MACHINE(s); 908 909 test_phandle = (*phandle)++; 910 name = g_strdup_printf("/soc/test@%lx", 911 (long)memmap[VIRT_TEST].base); 912 qemu_fdt_add_subnode(ms->fdt, name); 913 { 914 static const char * const compat[3] = { 915 "sifive,test1", "sifive,test0", "syscon" 916 }; 917 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 918 (char **)&compat, ARRAY_SIZE(compat)); 919 } 920 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 921 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 922 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 923 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 924 g_free(name); 925 926 name = g_strdup_printf("/reboot"); 927 qemu_fdt_add_subnode(ms->fdt, name); 928 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 929 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 930 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 931 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 932 g_free(name); 933 934 name = g_strdup_printf("/poweroff"); 935 qemu_fdt_add_subnode(ms->fdt, name); 936 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 937 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 938 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 939 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 940 g_free(name); 941 } 942 943 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 944 uint32_t irq_mmio_phandle) 945 { 946 g_autofree char *name = NULL; 947 MachineState *ms = MACHINE(s); 948 949 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 950 qemu_fdt_add_subnode(ms->fdt, name); 951 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 952 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 953 0x0, memmap[VIRT_UART0].base, 954 0x0, memmap[VIRT_UART0].size); 955 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 956 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 957 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 958 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 959 } else { 960 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 961 } 962 963 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 964 } 965 966 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 967 uint32_t irq_mmio_phandle) 968 { 969 g_autofree char *name = NULL; 970 MachineState *ms = MACHINE(s); 971 972 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 973 qemu_fdt_add_subnode(ms->fdt, name); 974 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 975 "google,goldfish-rtc"); 976 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 977 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 978 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 979 irq_mmio_phandle); 980 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 981 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 982 } else { 983 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 984 } 985 } 986 987 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 988 { 989 MachineState *ms = MACHINE(s); 990 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 991 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 992 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 993 994 qemu_fdt_add_subnode(ms->fdt, name); 995 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 996 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 997 2, flashbase, 2, flashsize, 998 2, flashbase + flashsize, 2, flashsize); 999 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 1000 } 1001 1002 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 1003 { 1004 MachineState *ms = MACHINE(s); 1005 hwaddr base = memmap[VIRT_FW_CFG].base; 1006 hwaddr size = memmap[VIRT_FW_CFG].size; 1007 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1008 1009 qemu_fdt_add_subnode(ms->fdt, nodename); 1010 qemu_fdt_setprop_string(ms->fdt, nodename, 1011 "compatible", "qemu,fw-cfg-mmio"); 1012 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1013 2, base, 2, size); 1014 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1015 } 1016 1017 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1018 { 1019 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1020 void *fdt = MACHINE(s)->fdt; 1021 uint32_t iommu_phandle; 1022 g_autofree char *iommu_node = NULL; 1023 g_autofree char *pci_node = NULL; 1024 1025 pci_node = g_strdup_printf("/soc/pci@%lx", 1026 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1027 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1028 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1029 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1030 1031 qemu_fdt_add_subnode(fdt, iommu_node); 1032 1033 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1034 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1035 1, bdf << 8, 1, 0, 1, 0, 1036 1, 0, 1, 0); 1037 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1038 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1039 1040 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1041 0, iommu_phandle, 0, bdf, 1042 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1043 } 1044 1045 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, 1046 uint32_t msi_phandle, 1047 uint32_t *iommu_sys_phandle) 1048 { 1049 const char comp[] = "riscv,iommu"; 1050 void *fdt = MACHINE(s)->fdt; 1051 uint32_t iommu_phandle; 1052 g_autofree char *iommu_node = NULL; 1053 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; 1054 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; 1055 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { 1056 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, 1057 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, 1058 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, 1059 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, 1060 }; 1061 1062 iommu_node = g_strdup_printf("/soc/iommu@%x", 1063 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); 1064 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1065 qemu_fdt_add_subnode(fdt, iommu_node); 1066 1067 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1068 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1069 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1070 1071 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1072 addr >> 32, addr, size >> 32, size); 1073 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); 1074 1075 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", 1076 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, 1077 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, 1078 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, 1079 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); 1080 1081 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); 1082 1083 *iommu_sys_phandle = iommu_phandle; 1084 } 1085 1086 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) 1087 { 1088 const char comp[] = "riscv,pci-iommu"; 1089 void *fdt = MACHINE(s)->fdt; 1090 uint32_t iommu_phandle; 1091 g_autofree char *iommu_node = NULL; 1092 g_autofree char *pci_node = NULL; 1093 1094 pci_node = g_strdup_printf("/soc/pci@%lx", 1095 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1096 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); 1097 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1098 qemu_fdt_add_subnode(fdt, iommu_node); 1099 1100 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1101 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1102 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1103 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1104 bdf << 8, 0, 0, 0, 0); 1105 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1106 0, iommu_phandle, 0, bdf, 1107 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1108 } 1109 1110 static void finalize_fdt(RISCVVirtState *s) 1111 { 1112 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1113 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1114 uint32_t iommu_sys_phandle = 1; 1115 1116 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1117 &irq_pcie_phandle, &irq_virtio_phandle, 1118 &msi_pcie_phandle); 1119 1120 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1121 1122 if (virt_is_iommu_sys_enabled(s)) { 1123 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, 1124 &iommu_sys_phandle); 1125 } 1126 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, 1127 iommu_sys_phandle); 1128 1129 create_fdt_reset(s, virt_memmap, &phandle); 1130 1131 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1132 1133 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1134 } 1135 1136 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1137 { 1138 MachineState *ms = MACHINE(s); 1139 uint8_t rng_seed[32]; 1140 g_autofree char *name = NULL; 1141 1142 ms->fdt = create_device_tree(&s->fdt_size); 1143 if (!ms->fdt) { 1144 error_report("create_device_tree() failed"); 1145 exit(1); 1146 } 1147 1148 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1149 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1150 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1151 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1152 1153 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1154 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1155 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1156 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1157 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1158 1159 /* 1160 * The "/soc/pci@..." node is needed for PCIE hotplugs 1161 * that might happen before finalize_fdt(). 1162 */ 1163 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1164 qemu_fdt_add_subnode(ms->fdt, name); 1165 1166 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1167 1168 /* Pass seed to RNG */ 1169 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1170 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1171 rng_seed, sizeof(rng_seed)); 1172 1173 create_fdt_flash(s, memmap); 1174 create_fdt_fw_cfg(s, memmap); 1175 create_fdt_pmu(s); 1176 } 1177 1178 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1179 DeviceState *irqchip, 1180 RISCVVirtState *s) 1181 { 1182 DeviceState *dev; 1183 MemoryRegion *ecam_alias, *ecam_reg; 1184 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1185 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1186 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1187 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1188 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1189 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1190 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1191 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1192 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1193 qemu_irq irq; 1194 int i; 1195 1196 dev = qdev_new(TYPE_GPEX_HOST); 1197 1198 /* Set GPEX object properties for the virt machine */ 1199 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, 1200 ecam_base, NULL); 1201 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, 1202 ecam_size, NULL); 1203 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, 1204 mmio_base, NULL); 1205 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, 1206 mmio_size, NULL); 1207 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, 1208 high_mmio_base, NULL); 1209 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1210 high_mmio_size, NULL); 1211 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, 1212 pio_base, NULL); 1213 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, 1214 pio_size, NULL); 1215 1216 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1217 1218 ecam_alias = g_new0(MemoryRegion, 1); 1219 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1220 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1221 ecam_reg, 0, ecam_size); 1222 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1223 1224 mmio_alias = g_new0(MemoryRegion, 1); 1225 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1226 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1227 mmio_reg, mmio_base, mmio_size); 1228 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1229 1230 /* Map high MMIO space */ 1231 high_mmio_alias = g_new0(MemoryRegion, 1); 1232 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1233 mmio_reg, high_mmio_base, high_mmio_size); 1234 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1235 high_mmio_alias); 1236 1237 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1238 1239 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1240 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1241 1242 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1243 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1244 } 1245 1246 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; 1247 return dev; 1248 } 1249 1250 static FWCfgState *create_fw_cfg(const MachineState *ms) 1251 { 1252 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1253 FWCfgState *fw_cfg; 1254 1255 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1256 &address_space_memory); 1257 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1258 1259 return fw_cfg; 1260 } 1261 1262 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1263 int base_hartid, int hart_count) 1264 { 1265 DeviceState *ret; 1266 g_autofree char *plic_hart_config = NULL; 1267 1268 /* Per-socket PLIC hart topology configuration string */ 1269 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1270 1271 /* Per-socket PLIC */ 1272 ret = sifive_plic_create( 1273 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1274 plic_hart_config, hart_count, base_hartid, 1275 VIRT_IRQCHIP_NUM_SOURCES, 1276 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1277 VIRT_PLIC_PRIORITY_BASE, 1278 VIRT_PLIC_PENDING_BASE, 1279 VIRT_PLIC_ENABLE_BASE, 1280 VIRT_PLIC_ENABLE_STRIDE, 1281 VIRT_PLIC_CONTEXT_BASE, 1282 VIRT_PLIC_CONTEXT_STRIDE, 1283 memmap[VIRT_PLIC].size); 1284 1285 return ret; 1286 } 1287 1288 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1289 const MemMapEntry *memmap, int socket, 1290 int base_hartid, int hart_count) 1291 { 1292 int i; 1293 hwaddr addr; 1294 uint32_t guest_bits; 1295 DeviceState *aplic_s = NULL; 1296 DeviceState *aplic_m = NULL; 1297 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1298 1299 if (msimode) { 1300 if (!kvm_enabled()) { 1301 /* Per-socket M-level IMSICs */ 1302 addr = memmap[VIRT_IMSIC_M].base + 1303 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1304 for (i = 0; i < hart_count; i++) { 1305 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1306 base_hartid + i, true, 1, 1307 VIRT_IRQCHIP_NUM_MSIS); 1308 } 1309 } 1310 1311 /* Per-socket S-level IMSICs */ 1312 guest_bits = imsic_num_bits(aia_guests + 1); 1313 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1314 for (i = 0; i < hart_count; i++) { 1315 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1316 base_hartid + i, false, 1 + aia_guests, 1317 VIRT_IRQCHIP_NUM_MSIS); 1318 } 1319 } 1320 1321 if (!kvm_enabled()) { 1322 /* Per-socket M-level APLIC */ 1323 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1324 socket * memmap[VIRT_APLIC_M].size, 1325 memmap[VIRT_APLIC_M].size, 1326 (msimode) ? 0 : base_hartid, 1327 (msimode) ? 0 : hart_count, 1328 VIRT_IRQCHIP_NUM_SOURCES, 1329 VIRT_IRQCHIP_NUM_PRIO_BITS, 1330 msimode, true, NULL); 1331 } 1332 1333 /* Per-socket S-level APLIC */ 1334 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1335 socket * memmap[VIRT_APLIC_S].size, 1336 memmap[VIRT_APLIC_S].size, 1337 (msimode) ? 0 : base_hartid, 1338 (msimode) ? 0 : hart_count, 1339 VIRT_IRQCHIP_NUM_SOURCES, 1340 VIRT_IRQCHIP_NUM_PRIO_BITS, 1341 msimode, false, aplic_m); 1342 1343 return kvm_enabled() ? aplic_s : aplic_m; 1344 } 1345 1346 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1347 { 1348 DeviceState *dev; 1349 SysBusDevice *sysbus; 1350 const MemMapEntry *memmap = virt_memmap; 1351 int i; 1352 MemoryRegion *sysmem = get_system_memory(); 1353 1354 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1355 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1356 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1357 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1358 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1359 s->platform_bus_dev = dev; 1360 1361 sysbus = SYS_BUS_DEVICE(dev); 1362 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1363 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1364 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1365 } 1366 1367 memory_region_add_subregion(sysmem, 1368 memmap[VIRT_PLATFORM_BUS].base, 1369 sysbus_mmio_get_region(sysbus, 0)); 1370 } 1371 1372 static void virt_build_smbios(RISCVVirtState *s) 1373 { 1374 MachineClass *mc = MACHINE_GET_CLASS(s); 1375 MachineState *ms = MACHINE(s); 1376 uint8_t *smbios_tables, *smbios_anchor; 1377 size_t smbios_tables_len, smbios_anchor_len; 1378 struct smbios_phys_mem_area mem_array; 1379 const char *product = "QEMU Virtual Machine"; 1380 1381 if (kvm_enabled()) { 1382 product = "KVM Virtual Machine"; 1383 } 1384 1385 smbios_set_defaults("QEMU", product, mc->name); 1386 1387 if (riscv_is_32bit(&s->soc[0])) { 1388 smbios_set_default_processor_family(0x200); 1389 } else { 1390 smbios_set_default_processor_family(0x201); 1391 } 1392 1393 /* build the array of physical mem area from base_memmap */ 1394 mem_array.address = s->memmap[VIRT_DRAM].base; 1395 mem_array.length = ms->ram_size; 1396 1397 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1398 &mem_array, 1, 1399 &smbios_tables, &smbios_tables_len, 1400 &smbios_anchor, &smbios_anchor_len, 1401 &error_fatal); 1402 1403 if (smbios_anchor) { 1404 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1405 smbios_tables, smbios_tables_len); 1406 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1407 smbios_anchor, smbios_anchor_len); 1408 } 1409 } 1410 1411 static void virt_machine_done(Notifier *notifier, void *data) 1412 { 1413 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1414 machine_done); 1415 const MemMapEntry *memmap = virt_memmap; 1416 MachineState *machine = MACHINE(s); 1417 hwaddr start_addr = memmap[VIRT_DRAM].base; 1418 target_ulong firmware_end_addr, kernel_start_addr; 1419 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1420 uint64_t fdt_load_addr; 1421 uint64_t kernel_entry = 0; 1422 BlockBackend *pflash_blk0; 1423 1424 /* 1425 * An user provided dtb must include everything, including 1426 * dynamic sysbus devices. Our FDT needs to be finalized. 1427 */ 1428 if (machine->dtb == NULL) { 1429 finalize_fdt(s); 1430 } 1431 1432 /* 1433 * Only direct boot kernel is currently supported for KVM VM, 1434 * so the "-bios" parameter is not supported when KVM is enabled. 1435 */ 1436 if (kvm_enabled()) { 1437 if (machine->firmware) { 1438 if (strcmp(machine->firmware, "none")) { 1439 error_report("Machine mode firmware is not supported in " 1440 "combination with KVM."); 1441 exit(1); 1442 } 1443 } else { 1444 machine->firmware = g_strdup("none"); 1445 } 1446 } 1447 1448 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1449 &start_addr, NULL); 1450 1451 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1452 if (pflash_blk0) { 1453 if (machine->firmware && !strcmp(machine->firmware, "none") && 1454 !kvm_enabled()) { 1455 /* 1456 * Pflash was supplied but bios is none and not KVM guest, 1457 * let's overwrite the address we jump to after reset to 1458 * the base of the flash. 1459 */ 1460 start_addr = virt_memmap[VIRT_FLASH].base; 1461 } else { 1462 /* 1463 * Pflash was supplied but either KVM guest or bios is not none. 1464 * In this case, base of the flash would contain S-mode payload. 1465 */ 1466 riscv_setup_firmware_boot(machine); 1467 kernel_entry = virt_memmap[VIRT_FLASH].base; 1468 } 1469 } 1470 1471 if (machine->kernel_filename && !kernel_entry) { 1472 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1473 firmware_end_addr); 1474 1475 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1476 kernel_start_addr, true, NULL); 1477 } 1478 1479 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1480 memmap[VIRT_DRAM].size, 1481 machine); 1482 riscv_load_fdt(fdt_load_addr, machine->fdt); 1483 1484 /* load the reset vector */ 1485 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1486 virt_memmap[VIRT_MROM].base, 1487 virt_memmap[VIRT_MROM].size, kernel_entry, 1488 fdt_load_addr); 1489 1490 /* 1491 * Only direct boot kernel is currently supported for KVM VM, 1492 * So here setup kernel start address and fdt address. 1493 * TODO:Support firmware loading and integrate to TCG start 1494 */ 1495 if (kvm_enabled()) { 1496 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1497 } 1498 1499 virt_build_smbios(s); 1500 1501 if (virt_is_acpi_enabled(s)) { 1502 virt_acpi_setup(s); 1503 } 1504 } 1505 1506 static void virt_machine_init(MachineState *machine) 1507 { 1508 const MemMapEntry *memmap = virt_memmap; 1509 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1510 MemoryRegion *system_memory = get_system_memory(); 1511 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1512 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1513 int i, base_hartid, hart_count; 1514 int socket_count = riscv_socket_count(machine); 1515 1516 /* Check socket count limit */ 1517 if (VIRT_SOCKETS_MAX < socket_count) { 1518 error_report("number of sockets/nodes should be less than %d", 1519 VIRT_SOCKETS_MAX); 1520 exit(1); 1521 } 1522 1523 if (!virt_aclint_allowed() && s->have_aclint) { 1524 error_report("'aclint' is only available with TCG acceleration"); 1525 exit(1); 1526 } 1527 1528 /* Initialize sockets */ 1529 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1530 for (i = 0; i < socket_count; i++) { 1531 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1532 1533 if (!riscv_socket_check_hartids(machine, i)) { 1534 error_report("discontinuous hartids in socket%d", i); 1535 exit(1); 1536 } 1537 1538 base_hartid = riscv_socket_first_hartid(machine, i); 1539 if (base_hartid < 0) { 1540 error_report("can't find hartid base for socket%d", i); 1541 exit(1); 1542 } 1543 1544 hart_count = riscv_socket_hart_count(machine, i); 1545 if (hart_count < 0) { 1546 error_report("can't find hart count for socket%d", i); 1547 exit(1); 1548 } 1549 1550 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1551 TYPE_RISCV_HART_ARRAY); 1552 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1553 machine->cpu_type, &error_abort); 1554 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1555 base_hartid, &error_abort); 1556 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1557 hart_count, &error_abort); 1558 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1559 1560 if (virt_aclint_allowed() && s->have_aclint) { 1561 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1562 /* Per-socket ACLINT MTIMER */ 1563 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1564 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1565 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1566 base_hartid, hart_count, 1567 RISCV_ACLINT_DEFAULT_MTIMECMP, 1568 RISCV_ACLINT_DEFAULT_MTIME, 1569 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1570 } else { 1571 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1572 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1573 i * memmap[VIRT_CLINT].size, 1574 base_hartid, hart_count, false); 1575 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1576 i * memmap[VIRT_CLINT].size + 1577 RISCV_ACLINT_SWI_SIZE, 1578 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1579 base_hartid, hart_count, 1580 RISCV_ACLINT_DEFAULT_MTIMECMP, 1581 RISCV_ACLINT_DEFAULT_MTIME, 1582 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1583 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1584 i * memmap[VIRT_ACLINT_SSWI].size, 1585 base_hartid, hart_count, true); 1586 } 1587 } else if (tcg_enabled()) { 1588 /* Per-socket SiFive CLINT */ 1589 riscv_aclint_swi_create( 1590 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1591 base_hartid, hart_count, false); 1592 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1593 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1594 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1595 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1596 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1597 } 1598 1599 /* Per-socket interrupt controller */ 1600 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1601 s->irqchip[i] = virt_create_plic(memmap, i, 1602 base_hartid, hart_count); 1603 } else { 1604 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1605 memmap, i, base_hartid, 1606 hart_count); 1607 } 1608 1609 /* Try to use different IRQCHIP instance based device type */ 1610 if (i == 0) { 1611 mmio_irqchip = s->irqchip[i]; 1612 virtio_irqchip = s->irqchip[i]; 1613 pcie_irqchip = s->irqchip[i]; 1614 } 1615 if (i == 1) { 1616 virtio_irqchip = s->irqchip[i]; 1617 pcie_irqchip = s->irqchip[i]; 1618 } 1619 if (i == 2) { 1620 pcie_irqchip = s->irqchip[i]; 1621 } 1622 } 1623 1624 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1625 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1626 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1627 memmap[VIRT_APLIC_S].base, 1628 memmap[VIRT_IMSIC_S].base, 1629 s->aia_guests); 1630 } 1631 1632 if (riscv_is_32bit(&s->soc[0])) { 1633 #if HOST_LONG_BITS == 64 1634 /* limit RAM size in a 32-bit system */ 1635 if (machine->ram_size > 10 * GiB) { 1636 machine->ram_size = 10 * GiB; 1637 error_report("Limiting RAM size to 10 GiB"); 1638 } 1639 #endif 1640 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1641 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1642 } else { 1643 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1644 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1645 virt_high_pcie_memmap.base = 1646 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1647 } 1648 1649 s->memmap = virt_memmap; 1650 1651 /* register system main memory (actual RAM) */ 1652 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1653 machine->ram); 1654 1655 /* boot rom */ 1656 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1657 memmap[VIRT_MROM].size, &error_fatal); 1658 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1659 mask_rom); 1660 1661 /* 1662 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1663 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1664 */ 1665 s->fw_cfg = create_fw_cfg(machine); 1666 rom_set_fw(s->fw_cfg); 1667 1668 /* SiFive Test MMIO device */ 1669 sifive_test_create(memmap[VIRT_TEST].base); 1670 1671 /* VirtIO MMIO devices */ 1672 for (i = 0; i < VIRTIO_COUNT; i++) { 1673 sysbus_create_simple("virtio-mmio", 1674 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1675 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1676 } 1677 1678 gpex_pcie_init(system_memory, pcie_irqchip, s); 1679 1680 create_platform_bus(s, mmio_irqchip); 1681 1682 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1683 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1684 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1685 1686 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1687 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1688 1689 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1690 /* Map legacy -drive if=pflash to machine properties */ 1691 pflash_cfi01_legacy_drive(s->flash[i], 1692 drive_get(IF_PFLASH, 0, i)); 1693 } 1694 virt_flash_map(s, system_memory); 1695 1696 /* load/create device tree */ 1697 if (machine->dtb) { 1698 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1699 if (!machine->fdt) { 1700 error_report("load_device_tree() failed"); 1701 exit(1); 1702 } 1703 } else { 1704 create_fdt(s, memmap); 1705 } 1706 1707 if (virt_is_iommu_sys_enabled(s)) { 1708 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); 1709 1710 object_property_set_uint(OBJECT(iommu_sys), "addr", 1711 s->memmap[VIRT_IOMMU_SYS].base, 1712 &error_fatal); 1713 object_property_set_uint(OBJECT(iommu_sys), "base-irq", 1714 IOMMU_SYS_IRQ, 1715 &error_fatal); 1716 object_property_set_link(OBJECT(iommu_sys), "irqchip", 1717 OBJECT(mmio_irqchip), 1718 &error_fatal); 1719 1720 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); 1721 } 1722 1723 s->machine_done.notify = virt_machine_done; 1724 qemu_add_machine_init_done_notifier(&s->machine_done); 1725 } 1726 1727 static void virt_machine_instance_init(Object *obj) 1728 { 1729 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1730 1731 virt_flash_create(s); 1732 1733 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1734 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1735 s->acpi = ON_OFF_AUTO_AUTO; 1736 s->iommu_sys = ON_OFF_AUTO_AUTO; 1737 } 1738 1739 static char *virt_get_aia_guests(Object *obj, Error **errp) 1740 { 1741 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1742 1743 return g_strdup_printf("%d", s->aia_guests); 1744 } 1745 1746 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1747 { 1748 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1749 1750 s->aia_guests = atoi(val); 1751 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1752 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1753 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1754 VIRT_IRQCHIP_MAX_GUESTS); 1755 } 1756 } 1757 1758 static char *virt_get_aia(Object *obj, Error **errp) 1759 { 1760 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1761 const char *val; 1762 1763 switch (s->aia_type) { 1764 case VIRT_AIA_TYPE_APLIC: 1765 val = "aplic"; 1766 break; 1767 case VIRT_AIA_TYPE_APLIC_IMSIC: 1768 val = "aplic-imsic"; 1769 break; 1770 default: 1771 val = "none"; 1772 break; 1773 }; 1774 1775 return g_strdup(val); 1776 } 1777 1778 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1779 { 1780 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1781 1782 if (!strcmp(val, "none")) { 1783 s->aia_type = VIRT_AIA_TYPE_NONE; 1784 } else if (!strcmp(val, "aplic")) { 1785 s->aia_type = VIRT_AIA_TYPE_APLIC; 1786 } else if (!strcmp(val, "aplic-imsic")) { 1787 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1788 } else { 1789 error_setg(errp, "Invalid AIA interrupt controller type"); 1790 error_append_hint(errp, "Valid values are none, aplic, and " 1791 "aplic-imsic.\n"); 1792 } 1793 } 1794 1795 static bool virt_get_aclint(Object *obj, Error **errp) 1796 { 1797 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1798 1799 return s->have_aclint; 1800 } 1801 1802 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1803 { 1804 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1805 1806 s->have_aclint = value; 1807 } 1808 1809 bool virt_is_iommu_sys_enabled(RISCVVirtState *s) 1810 { 1811 return s->iommu_sys == ON_OFF_AUTO_ON; 1812 } 1813 1814 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, 1815 void *opaque, Error **errp) 1816 { 1817 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1818 OnOffAuto iommu_sys = s->iommu_sys; 1819 1820 visit_type_OnOffAuto(v, name, &iommu_sys, errp); 1821 } 1822 1823 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, 1824 void *opaque, Error **errp) 1825 { 1826 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1827 1828 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); 1829 } 1830 1831 bool virt_is_acpi_enabled(RISCVVirtState *s) 1832 { 1833 return s->acpi != ON_OFF_AUTO_OFF; 1834 } 1835 1836 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1837 void *opaque, Error **errp) 1838 { 1839 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1840 OnOffAuto acpi = s->acpi; 1841 1842 visit_type_OnOffAuto(v, name, &acpi, errp); 1843 } 1844 1845 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1846 void *opaque, Error **errp) 1847 { 1848 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1849 1850 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1851 } 1852 1853 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1854 DeviceState *dev) 1855 { 1856 MachineClass *mc = MACHINE_GET_CLASS(machine); 1857 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1858 1859 if (device_is_dynamic_sysbus(mc, dev) || 1860 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1861 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1862 s->iommu_sys = ON_OFF_AUTO_OFF; 1863 return HOTPLUG_HANDLER(machine); 1864 } 1865 1866 return NULL; 1867 } 1868 1869 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1870 DeviceState *dev, Error **errp) 1871 { 1872 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1873 1874 if (s->platform_bus_dev) { 1875 MachineClass *mc = MACHINE_GET_CLASS(s); 1876 1877 if (device_is_dynamic_sysbus(mc, dev)) { 1878 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1879 SYS_BUS_DEVICE(dev)); 1880 } 1881 } 1882 1883 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1884 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1885 } 1886 1887 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1888 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1889 s->iommu_sys = ON_OFF_AUTO_OFF; 1890 } 1891 } 1892 1893 static void virt_machine_class_init(ObjectClass *oc, void *data) 1894 { 1895 MachineClass *mc = MACHINE_CLASS(oc); 1896 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1897 1898 mc->desc = "RISC-V VirtIO board"; 1899 mc->init = virt_machine_init; 1900 mc->max_cpus = VIRT_CPUS_MAX; 1901 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1902 mc->block_default_type = IF_VIRTIO; 1903 mc->no_cdrom = 1; 1904 mc->pci_allow_0_address = true; 1905 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1906 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1907 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1908 mc->numa_mem_supported = true; 1909 /* platform instead of architectural choice */ 1910 mc->cpu_cluster_has_numa_boundary = true; 1911 mc->default_ram_id = "riscv_virt_board.ram"; 1912 assert(!mc->get_hotplug_handler); 1913 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1914 1915 hc->plug = virt_machine_device_plug_cb; 1916 1917 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1918 #ifdef CONFIG_TPM 1919 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1920 #endif 1921 1922 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1923 virt_set_aclint); 1924 object_class_property_set_description(oc, "aclint", 1925 "(TCG only) Set on/off to " 1926 "enable/disable emulating " 1927 "ACLINT devices"); 1928 1929 object_class_property_add_str(oc, "aia", virt_get_aia, 1930 virt_set_aia); 1931 object_class_property_set_description(oc, "aia", 1932 "Set type of AIA interrupt " 1933 "controller. Valid values are " 1934 "none, aplic, and aplic-imsic."); 1935 1936 object_class_property_add_str(oc, "aia-guests", 1937 virt_get_aia_guests, 1938 virt_set_aia_guests); 1939 { 1940 g_autofree char *str = 1941 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1942 "Valid value should be between 0 and %d.", 1943 VIRT_IRQCHIP_MAX_GUESTS); 1944 object_class_property_set_description(oc, "aia-guests", str); 1945 } 1946 1947 object_class_property_add(oc, "acpi", "OnOffAuto", 1948 virt_get_acpi, virt_set_acpi, 1949 NULL, NULL); 1950 object_class_property_set_description(oc, "acpi", 1951 "Enable ACPI"); 1952 1953 object_class_property_add(oc, "iommu-sys", "OnOffAuto", 1954 virt_get_iommu_sys, virt_set_iommu_sys, 1955 NULL, NULL); 1956 object_class_property_set_description(oc, "iommu-sys", 1957 "Enable IOMMU platform device"); 1958 } 1959 1960 static const TypeInfo virt_machine_typeinfo = { 1961 .name = MACHINE_TYPE_NAME("virt"), 1962 .parent = TYPE_MACHINE, 1963 .class_init = virt_machine_class_init, 1964 .instance_init = virt_machine_instance_init, 1965 .instance_size = sizeof(RISCVVirtState), 1966 .interfaces = (InterfaceInfo[]) { 1967 { TYPE_HOTPLUG_HANDLER }, 1968 { } 1969 }, 1970 }; 1971 1972 static void virt_machine_init_register_types(void) 1973 { 1974 type_register_static(&virt_machine_typeinfo); 1975 } 1976 1977 type_init(virt_machine_init_register_types) 1978