1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/firmware/smbios.h" 40 #include "hw/intc/riscv_aclint.h" 41 #include "hw/intc/riscv_aplic.h" 42 #include "hw/intc/sifive_plic.h" 43 #include "hw/misc/sifive_test.h" 44 #include "hw/platform-bus.h" 45 #include "chardev/char.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/tcg.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/tpm.h" 51 #include "sysemu/qtest.h" 52 #include "hw/pci/pci.h" 53 #include "hw/pci-host/gpex.h" 54 #include "hw/display/ramfb.h" 55 #include "hw/acpi/aml-build.h" 56 #include "qapi/qapi-visit-common.h" 57 #include "hw/virtio/virtio-iommu.h" 58 59 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 60 static bool virt_use_kvm_aia(RISCVVirtState *s) 61 { 62 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 63 } 64 65 static bool virt_aclint_allowed(void) 66 { 67 return tcg_enabled() || qtest_enabled(); 68 } 69 70 static const MemMapEntry virt_memmap[] = { 71 [VIRT_DEBUG] = { 0x0, 0x100 }, 72 [VIRT_MROM] = { 0x1000, 0xf000 }, 73 [VIRT_TEST] = { 0x100000, 0x1000 }, 74 [VIRT_RTC] = { 0x101000, 0x1000 }, 75 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 78 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 79 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 80 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 81 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 82 [VIRT_UART0] = { 0x10000000, 0x100 }, 83 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 84 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 85 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 86 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 87 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 88 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 89 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 90 [VIRT_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 /* PCIe high mmio is fixed for RV32 */ 94 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 95 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 96 97 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 98 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 99 100 static MemMapEntry virt_high_pcie_memmap; 101 102 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 103 104 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 105 const char *name, 106 const char *alias_prop_name) 107 { 108 /* 109 * Create a single flash device. We use the same parameters as 110 * the flash devices on the ARM virt board. 111 */ 112 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 113 114 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 115 qdev_prop_set_uint8(dev, "width", 4); 116 qdev_prop_set_uint8(dev, "device-width", 2); 117 qdev_prop_set_bit(dev, "big-endian", false); 118 qdev_prop_set_uint16(dev, "id0", 0x89); 119 qdev_prop_set_uint16(dev, "id1", 0x18); 120 qdev_prop_set_uint16(dev, "id2", 0x00); 121 qdev_prop_set_uint16(dev, "id3", 0x00); 122 qdev_prop_set_string(dev, "name", name); 123 124 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 125 object_property_add_alias(OBJECT(s), alias_prop_name, 126 OBJECT(dev), "drive"); 127 128 return PFLASH_CFI01(dev); 129 } 130 131 static void virt_flash_create(RISCVVirtState *s) 132 { 133 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 134 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 135 } 136 137 static void virt_flash_map1(PFlashCFI01 *flash, 138 hwaddr base, hwaddr size, 139 MemoryRegion *sysmem) 140 { 141 DeviceState *dev = DEVICE(flash); 142 143 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 144 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 145 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 147 148 memory_region_add_subregion(sysmem, base, 149 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 150 0)); 151 } 152 153 static void virt_flash_map(RISCVVirtState *s, 154 MemoryRegion *sysmem) 155 { 156 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 157 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 158 159 virt_flash_map1(s->flash[0], flashbase, flashsize, 160 sysmem); 161 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 162 sysmem); 163 } 164 165 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 166 uint32_t irqchip_phandle) 167 { 168 int pin, dev; 169 uint32_t irq_map_stride = 0; 170 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 171 FDT_MAX_INT_MAP_WIDTH] = {}; 172 uint32_t *irq_map = full_irq_map; 173 174 /* This code creates a standard swizzle of interrupts such that 175 * each device's first interrupt is based on it's PCI_SLOT number. 176 * (See pci_swizzle_map_irq_fn()) 177 * 178 * We only need one entry per interrupt in the table (not one per 179 * possible slot) seeing the interrupt-map-mask will allow the table 180 * to wrap to any number of devices. 181 */ 182 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 183 int devfn = dev * 0x8; 184 185 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 186 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 187 int i = 0; 188 189 /* Fill PCI address cells */ 190 irq_map[i] = cpu_to_be32(devfn << 8); 191 i += FDT_PCI_ADDR_CELLS; 192 193 /* Fill PCI Interrupt cells */ 194 irq_map[i] = cpu_to_be32(pin + 1); 195 i += FDT_PCI_INT_CELLS; 196 197 /* Fill interrupt controller phandle and cells */ 198 irq_map[i++] = cpu_to_be32(irqchip_phandle); 199 irq_map[i++] = cpu_to_be32(irq_nr); 200 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 201 irq_map[i++] = cpu_to_be32(0x4); 202 } 203 204 if (!irq_map_stride) { 205 irq_map_stride = i; 206 } 207 irq_map += irq_map_stride; 208 } 209 } 210 211 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 212 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 213 irq_map_stride * sizeof(uint32_t)); 214 215 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 216 0x1800, 0, 0, 0x7); 217 } 218 219 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 220 char *clust_name, uint32_t *phandle, 221 uint32_t *intc_phandles) 222 { 223 int cpu; 224 uint32_t cpu_phandle; 225 MachineState *ms = MACHINE(s); 226 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 227 uint8_t satp_mode_max; 228 229 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 230 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 231 g_autofree char *cpu_name = NULL; 232 g_autofree char *core_name = NULL; 233 g_autofree char *intc_name = NULL; 234 g_autofree char *sv_name = NULL; 235 236 cpu_phandle = (*phandle)++; 237 238 cpu_name = g_strdup_printf("/cpus/cpu@%d", 239 s->soc[socket].hartid_base + cpu); 240 qemu_fdt_add_subnode(ms->fdt, cpu_name); 241 242 if (cpu_ptr->cfg.satp_mode.supported != 0) { 243 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 244 sv_name = g_strdup_printf("riscv,%s", 245 satp_mode_str(satp_mode_max, is_32_bit)); 246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 247 } 248 249 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 250 251 if (cpu_ptr->cfg.ext_zicbom) { 252 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 253 cpu_ptr->cfg.cbom_blocksize); 254 } 255 256 if (cpu_ptr->cfg.ext_zicboz) { 257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 258 cpu_ptr->cfg.cboz_blocksize); 259 } 260 261 if (cpu_ptr->cfg.ext_zicbop) { 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 263 cpu_ptr->cfg.cbop_blocksize); 264 } 265 266 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 268 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 269 s->soc[socket].hartid_base + cpu); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 271 riscv_socket_fdt_write_id(ms, cpu_name, socket); 272 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 273 274 intc_phandles[cpu] = (*phandle)++; 275 276 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 277 qemu_fdt_add_subnode(ms->fdt, intc_name); 278 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 279 intc_phandles[cpu]); 280 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 281 "riscv,cpu-intc"); 282 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 283 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 284 285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 286 qemu_fdt_add_subnode(ms->fdt, core_name); 287 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 288 } 289 } 290 291 static void create_fdt_socket_memory(RISCVVirtState *s, 292 const MemMapEntry *memmap, int socket) 293 { 294 g_autofree char *mem_name = NULL; 295 uint64_t addr, size; 296 MachineState *ms = MACHINE(s); 297 298 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 299 size = riscv_socket_mem_size(ms, socket); 300 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 301 qemu_fdt_add_subnode(ms->fdt, mem_name); 302 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 303 addr >> 32, addr, size >> 32, size); 304 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 305 riscv_socket_fdt_write_id(ms, mem_name, socket); 306 } 307 308 static void create_fdt_socket_clint(RISCVVirtState *s, 309 const MemMapEntry *memmap, int socket, 310 uint32_t *intc_phandles) 311 { 312 int cpu; 313 g_autofree char *clint_name = NULL; 314 g_autofree uint32_t *clint_cells = NULL; 315 unsigned long clint_addr; 316 MachineState *ms = MACHINE(s); 317 static const char * const clint_compat[2] = { 318 "sifive,clint0", "riscv,clint0" 319 }; 320 321 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 322 323 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 324 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 325 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 326 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 327 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 328 } 329 330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 331 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 332 qemu_fdt_add_subnode(ms->fdt, clint_name); 333 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 334 (char **)&clint_compat, 335 ARRAY_SIZE(clint_compat)); 336 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 337 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 338 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 339 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 340 riscv_socket_fdt_write_id(ms, clint_name, socket); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 g_autofree uint32_t *aclint_mswi_cells = NULL; 352 g_autofree uint32_t *aclint_sswi_cells = NULL; 353 g_autofree uint32_t *aclint_mtimer_cells = NULL; 354 MachineState *ms = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(ms->fdt, name); 374 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(ms, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(ms->fdt, name); 397 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(ms, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(ms->fdt, name); 414 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 } 425 } 426 427 static void create_fdt_socket_plic(RISCVVirtState *s, 428 const MemMapEntry *memmap, int socket, 429 uint32_t *phandle, uint32_t *intc_phandles, 430 uint32_t *plic_phandles) 431 { 432 int cpu; 433 g_autofree char *plic_name = NULL; 434 g_autofree uint32_t *plic_cells; 435 unsigned long plic_addr; 436 MachineState *ms = MACHINE(s); 437 static const char * const plic_compat[2] = { 438 "sifive,plic-1.0.0", "riscv,plic0" 439 }; 440 441 plic_phandles[socket] = (*phandle)++; 442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 443 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 444 qemu_fdt_add_subnode(ms->fdt, plic_name); 445 qemu_fdt_setprop_cell(ms->fdt, plic_name, 446 "#interrupt-cells", FDT_PLIC_INT_CELLS); 447 qemu_fdt_setprop_cell(ms->fdt, plic_name, 448 "#address-cells", FDT_PLIC_ADDR_CELLS); 449 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 450 (char **)&plic_compat, 451 ARRAY_SIZE(plic_compat)); 452 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 453 454 if (kvm_enabled()) { 455 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 456 457 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 460 } 461 462 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 463 plic_cells, 464 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 465 } else { 466 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 467 468 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 469 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 470 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 471 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 472 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 473 } 474 475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 476 plic_cells, 477 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 478 } 479 480 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 481 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 482 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 483 VIRT_IRQCHIP_NUM_SOURCES - 1); 484 riscv_socket_fdt_write_id(ms, plic_name, socket); 485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 486 plic_phandles[socket]); 487 488 if (!socket) { 489 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 490 memmap[VIRT_PLATFORM_BUS].base, 491 memmap[VIRT_PLATFORM_BUS].size, 492 VIRT_PLATFORM_BUS_IRQ); 493 } 494 } 495 496 uint32_t imsic_num_bits(uint32_t count) 497 { 498 uint32_t ret = 0; 499 500 while (BIT(ret) < count) { 501 ret++; 502 } 503 504 return ret; 505 } 506 507 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 508 uint32_t *intc_phandles, uint32_t msi_phandle, 509 bool m_mode, uint32_t imsic_guest_bits) 510 { 511 int cpu, socket; 512 g_autofree char *imsic_name = NULL; 513 MachineState *ms = MACHINE(s); 514 int socket_count = riscv_socket_count(ms); 515 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 516 g_autofree uint32_t *imsic_cells = NULL; 517 g_autofree uint32_t *imsic_regs = NULL; 518 519 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 520 imsic_regs = g_new0(uint32_t, socket_count * 4); 521 522 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 523 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 524 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 525 } 526 527 imsic_max_hart_per_socket = 0; 528 for (socket = 0; socket < socket_count; socket++) { 529 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 530 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 531 s->soc[socket].num_harts; 532 imsic_regs[socket * 4 + 0] = 0; 533 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 534 imsic_regs[socket * 4 + 2] = 0; 535 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 536 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 537 imsic_max_hart_per_socket = s->soc[socket].num_harts; 538 } 539 } 540 541 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 542 qemu_fdt_add_subnode(ms->fdt, imsic_name); 543 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 544 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 545 FDT_IMSIC_INT_CELLS); 546 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 547 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 548 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 549 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 550 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 551 socket_count * sizeof(uint32_t) * 4); 552 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 553 VIRT_IRQCHIP_NUM_MSIS); 554 555 if (imsic_guest_bits) { 556 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 557 imsic_guest_bits); 558 } 559 560 if (socket_count > 1) { 561 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 562 imsic_num_bits(imsic_max_hart_per_socket)); 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 564 imsic_num_bits(socket_count)); 565 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 566 IMSIC_MMIO_GROUP_MIN_SHIFT); 567 } 568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 569 } 570 571 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 572 uint32_t *phandle, uint32_t *intc_phandles, 573 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 574 { 575 *msi_m_phandle = (*phandle)++; 576 *msi_s_phandle = (*phandle)++; 577 578 if (!kvm_enabled()) { 579 /* M-level IMSIC node */ 580 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 581 *msi_m_phandle, true, 0); 582 } 583 584 /* S-level IMSIC node */ 585 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 586 *msi_s_phandle, false, 587 imsic_num_bits(s->aia_guests + 1)); 588 589 } 590 591 /* Caller must free string after use */ 592 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 593 { 594 return g_strdup_printf("/soc/aplic@%lx", aplic_addr); 595 } 596 597 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 598 unsigned long aplic_addr, uint32_t aplic_size, 599 uint32_t msi_phandle, 600 uint32_t *intc_phandles, 601 uint32_t aplic_phandle, 602 uint32_t aplic_child_phandle, 603 bool m_mode, int num_harts) 604 { 605 int cpu; 606 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 607 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 608 MachineState *ms = MACHINE(s); 609 610 for (cpu = 0; cpu < num_harts; cpu++) { 611 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 612 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 613 } 614 615 qemu_fdt_add_subnode(ms->fdt, aplic_name); 616 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 617 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 618 FDT_APLIC_ADDR_CELLS); 619 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 620 "#interrupt-cells", FDT_APLIC_INT_CELLS); 621 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 622 623 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 624 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 625 aplic_cells, num_harts * sizeof(uint32_t) * 2); 626 } else { 627 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 628 } 629 630 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 631 0x0, aplic_addr, 0x0, aplic_size); 632 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 633 VIRT_IRQCHIP_NUM_SOURCES); 634 635 if (aplic_child_phandle) { 636 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 637 aplic_child_phandle); 638 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 639 aplic_child_phandle, 0x1, 640 VIRT_IRQCHIP_NUM_SOURCES); 641 } 642 643 riscv_socket_fdt_write_id(ms, aplic_name, socket); 644 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 645 } 646 647 static void create_fdt_socket_aplic(RISCVVirtState *s, 648 const MemMapEntry *memmap, int socket, 649 uint32_t msi_m_phandle, 650 uint32_t msi_s_phandle, 651 uint32_t *phandle, 652 uint32_t *intc_phandles, 653 uint32_t *aplic_phandles, 654 int num_harts) 655 { 656 unsigned long aplic_addr; 657 MachineState *ms = MACHINE(s); 658 uint32_t aplic_m_phandle, aplic_s_phandle; 659 660 aplic_m_phandle = (*phandle)++; 661 aplic_s_phandle = (*phandle)++; 662 663 if (!kvm_enabled()) { 664 /* M-level APLIC node */ 665 aplic_addr = memmap[VIRT_APLIC_M].base + 666 (memmap[VIRT_APLIC_M].size * socket); 667 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 668 msi_m_phandle, intc_phandles, 669 aplic_m_phandle, aplic_s_phandle, 670 true, num_harts); 671 } 672 673 /* S-level APLIC node */ 674 aplic_addr = memmap[VIRT_APLIC_S].base + 675 (memmap[VIRT_APLIC_S].size * socket); 676 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 677 msi_s_phandle, intc_phandles, 678 aplic_s_phandle, 0, 679 false, num_harts); 680 681 if (!socket) { 682 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 683 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 684 memmap[VIRT_PLATFORM_BUS].base, 685 memmap[VIRT_PLATFORM_BUS].size, 686 VIRT_PLATFORM_BUS_IRQ); 687 } 688 689 aplic_phandles[socket] = aplic_s_phandle; 690 } 691 692 static void create_fdt_pmu(RISCVVirtState *s) 693 { 694 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 695 MachineState *ms = MACHINE(s); 696 RISCVCPU hart = s->soc[0].harts[0]; 697 698 qemu_fdt_add_subnode(ms->fdt, pmu_name); 699 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 700 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 701 } 702 703 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 704 uint32_t *phandle, 705 uint32_t *irq_mmio_phandle, 706 uint32_t *irq_pcie_phandle, 707 uint32_t *irq_virtio_phandle, 708 uint32_t *msi_pcie_phandle) 709 { 710 int socket, phandle_pos; 711 MachineState *ms = MACHINE(s); 712 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 713 uint32_t xplic_phandles[MAX_NODES]; 714 g_autofree uint32_t *intc_phandles = NULL; 715 int socket_count = riscv_socket_count(ms); 716 717 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 718 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 719 kvm_enabled() ? 720 kvm_riscv_get_timebase_frequency(first_cpu) : 721 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 722 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 723 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 724 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 725 726 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 727 728 phandle_pos = ms->smp.cpus; 729 for (socket = (socket_count - 1); socket >= 0; socket--) { 730 g_autofree char *clust_name = NULL; 731 phandle_pos -= s->soc[socket].num_harts; 732 733 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 734 qemu_fdt_add_subnode(ms->fdt, clust_name); 735 736 create_fdt_socket_cpus(s, socket, clust_name, phandle, 737 &intc_phandles[phandle_pos]); 738 739 create_fdt_socket_memory(s, memmap, socket); 740 741 if (virt_aclint_allowed() && s->have_aclint) { 742 create_fdt_socket_aclint(s, memmap, socket, 743 &intc_phandles[phandle_pos]); 744 } else if (tcg_enabled()) { 745 create_fdt_socket_clint(s, memmap, socket, 746 &intc_phandles[phandle_pos]); 747 } 748 } 749 750 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 751 create_fdt_imsic(s, memmap, phandle, intc_phandles, 752 &msi_m_phandle, &msi_s_phandle); 753 *msi_pcie_phandle = msi_s_phandle; 754 } 755 756 /* KVM AIA only has one APLIC instance */ 757 if (kvm_enabled() && virt_use_kvm_aia(s)) { 758 create_fdt_socket_aplic(s, memmap, 0, 759 msi_m_phandle, msi_s_phandle, phandle, 760 &intc_phandles[0], xplic_phandles, 761 ms->smp.cpus); 762 } else { 763 phandle_pos = ms->smp.cpus; 764 for (socket = (socket_count - 1); socket >= 0; socket--) { 765 phandle_pos -= s->soc[socket].num_harts; 766 767 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 768 create_fdt_socket_plic(s, memmap, socket, phandle, 769 &intc_phandles[phandle_pos], 770 xplic_phandles); 771 } else { 772 create_fdt_socket_aplic(s, memmap, socket, 773 msi_m_phandle, msi_s_phandle, phandle, 774 &intc_phandles[phandle_pos], 775 xplic_phandles, 776 s->soc[socket].num_harts); 777 } 778 } 779 } 780 781 if (kvm_enabled() && virt_use_kvm_aia(s)) { 782 *irq_mmio_phandle = xplic_phandles[0]; 783 *irq_virtio_phandle = xplic_phandles[0]; 784 *irq_pcie_phandle = xplic_phandles[0]; 785 } else { 786 for (socket = 0; socket < socket_count; socket++) { 787 if (socket == 0) { 788 *irq_mmio_phandle = xplic_phandles[socket]; 789 *irq_virtio_phandle = xplic_phandles[socket]; 790 *irq_pcie_phandle = xplic_phandles[socket]; 791 } 792 if (socket == 1) { 793 *irq_virtio_phandle = xplic_phandles[socket]; 794 *irq_pcie_phandle = xplic_phandles[socket]; 795 } 796 if (socket == 2) { 797 *irq_pcie_phandle = xplic_phandles[socket]; 798 } 799 } 800 } 801 802 riscv_socket_fdt_write_distance_matrix(ms); 803 } 804 805 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 806 uint32_t irq_virtio_phandle) 807 { 808 int i; 809 MachineState *ms = MACHINE(s); 810 811 for (i = 0; i < VIRTIO_COUNT; i++) { 812 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 813 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 814 815 qemu_fdt_add_subnode(ms->fdt, name); 816 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 817 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 818 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 819 0x0, memmap[VIRT_VIRTIO].size); 820 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 821 irq_virtio_phandle); 822 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 823 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 824 VIRTIO_IRQ + i); 825 } else { 826 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 827 VIRTIO_IRQ + i, 0x4); 828 } 829 } 830 } 831 832 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 833 uint32_t irq_pcie_phandle, 834 uint32_t msi_pcie_phandle) 835 { 836 g_autofree char *name = NULL; 837 MachineState *ms = MACHINE(s); 838 839 name = g_strdup_printf("/soc/pci@%lx", 840 (long) memmap[VIRT_PCIE_ECAM].base); 841 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 842 FDT_PCI_ADDR_CELLS); 843 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 844 FDT_PCI_INT_CELLS); 845 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 846 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 847 "pci-host-ecam-generic"); 848 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 849 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 850 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 851 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 852 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 853 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 854 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 855 } 856 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 857 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 858 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 859 1, FDT_PCI_RANGE_IOPORT, 2, 0, 860 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 861 1, FDT_PCI_RANGE_MMIO, 862 2, memmap[VIRT_PCIE_MMIO].base, 863 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 864 1, FDT_PCI_RANGE_MMIO_64BIT, 865 2, virt_high_pcie_memmap.base, 866 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 867 868 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 869 } 870 871 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 872 uint32_t *phandle) 873 { 874 char *name; 875 uint32_t test_phandle; 876 MachineState *ms = MACHINE(s); 877 878 test_phandle = (*phandle)++; 879 name = g_strdup_printf("/soc/test@%lx", 880 (long)memmap[VIRT_TEST].base); 881 qemu_fdt_add_subnode(ms->fdt, name); 882 { 883 static const char * const compat[3] = { 884 "sifive,test1", "sifive,test0", "syscon" 885 }; 886 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 887 (char **)&compat, ARRAY_SIZE(compat)); 888 } 889 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 890 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 891 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 892 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 893 g_free(name); 894 895 name = g_strdup_printf("/reboot"); 896 qemu_fdt_add_subnode(ms->fdt, name); 897 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 898 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 899 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 900 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 901 g_free(name); 902 903 name = g_strdup_printf("/poweroff"); 904 qemu_fdt_add_subnode(ms->fdt, name); 905 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 906 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 907 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 908 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 909 g_free(name); 910 } 911 912 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 913 uint32_t irq_mmio_phandle) 914 { 915 g_autofree char *name = NULL; 916 MachineState *ms = MACHINE(s); 917 918 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 919 qemu_fdt_add_subnode(ms->fdt, name); 920 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 921 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 922 0x0, memmap[VIRT_UART0].base, 923 0x0, memmap[VIRT_UART0].size); 924 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 925 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 926 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 927 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 928 } else { 929 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 930 } 931 932 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 933 } 934 935 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 936 uint32_t irq_mmio_phandle) 937 { 938 g_autofree char *name = NULL; 939 MachineState *ms = MACHINE(s); 940 941 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 942 qemu_fdt_add_subnode(ms->fdt, name); 943 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 944 "google,goldfish-rtc"); 945 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 946 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 947 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 948 irq_mmio_phandle); 949 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 950 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 951 } else { 952 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 953 } 954 } 955 956 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 957 { 958 MachineState *ms = MACHINE(s); 959 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 960 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 961 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 962 963 qemu_fdt_add_subnode(ms->fdt, name); 964 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 965 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 966 2, flashbase, 2, flashsize, 967 2, flashbase + flashsize, 2, flashsize); 968 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 969 } 970 971 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 972 { 973 MachineState *ms = MACHINE(s); 974 hwaddr base = memmap[VIRT_FW_CFG].base; 975 hwaddr size = memmap[VIRT_FW_CFG].size; 976 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 977 978 qemu_fdt_add_subnode(ms->fdt, nodename); 979 qemu_fdt_setprop_string(ms->fdt, nodename, 980 "compatible", "qemu,fw-cfg-mmio"); 981 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 982 2, base, 2, size); 983 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 984 } 985 986 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 987 { 988 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 989 void *fdt = MACHINE(s)->fdt; 990 uint32_t iommu_phandle; 991 g_autofree char *iommu_node = NULL; 992 g_autofree char *pci_node = NULL; 993 994 pci_node = g_strdup_printf("/soc/pci@%lx", 995 (long) virt_memmap[VIRT_PCIE_ECAM].base); 996 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 997 PCI_SLOT(bdf), PCI_FUNC(bdf)); 998 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 999 1000 qemu_fdt_add_subnode(fdt, iommu_node); 1001 1002 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1003 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1004 1, bdf << 8, 1, 0, 1, 0, 1005 1, 0, 1, 0); 1006 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1007 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1008 1009 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1010 0, iommu_phandle, 0, bdf, 1011 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1012 } 1013 1014 static void finalize_fdt(RISCVVirtState *s) 1015 { 1016 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1017 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1018 1019 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1020 &irq_pcie_phandle, &irq_virtio_phandle, 1021 &msi_pcie_phandle); 1022 1023 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1024 1025 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1026 1027 create_fdt_reset(s, virt_memmap, &phandle); 1028 1029 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1030 1031 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1032 } 1033 1034 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1035 { 1036 MachineState *ms = MACHINE(s); 1037 uint8_t rng_seed[32]; 1038 g_autofree char *name = NULL; 1039 1040 ms->fdt = create_device_tree(&s->fdt_size); 1041 if (!ms->fdt) { 1042 error_report("create_device_tree() failed"); 1043 exit(1); 1044 } 1045 1046 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1047 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1048 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1049 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1050 1051 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1052 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1053 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1054 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1055 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1056 1057 /* 1058 * The "/soc/pci@..." node is needed for PCIE hotplugs 1059 * that might happen before finalize_fdt(). 1060 */ 1061 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1062 qemu_fdt_add_subnode(ms->fdt, name); 1063 1064 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1065 1066 /* Pass seed to RNG */ 1067 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1068 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1069 rng_seed, sizeof(rng_seed)); 1070 1071 create_fdt_flash(s, memmap); 1072 create_fdt_fw_cfg(s, memmap); 1073 create_fdt_pmu(s); 1074 } 1075 1076 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1077 DeviceState *irqchip, 1078 RISCVVirtState *s) 1079 { 1080 DeviceState *dev; 1081 MemoryRegion *ecam_alias, *ecam_reg; 1082 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1083 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1084 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1085 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1086 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1087 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1088 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1089 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1090 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1091 qemu_irq irq; 1092 int i; 1093 1094 dev = qdev_new(TYPE_GPEX_HOST); 1095 1096 /* Set GPEX object properties for the virt machine */ 1097 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1098 ecam_base, NULL); 1099 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1100 ecam_size, NULL); 1101 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1102 PCI_HOST_BELOW_4G_MMIO_BASE, 1103 mmio_base, NULL); 1104 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1105 mmio_size, NULL); 1106 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1107 PCI_HOST_ABOVE_4G_MMIO_BASE, 1108 high_mmio_base, NULL); 1109 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1110 high_mmio_size, NULL); 1111 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1112 pio_base, NULL); 1113 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1114 pio_size, NULL); 1115 1116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1117 1118 ecam_alias = g_new0(MemoryRegion, 1); 1119 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1120 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1121 ecam_reg, 0, ecam_size); 1122 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1123 1124 mmio_alias = g_new0(MemoryRegion, 1); 1125 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1126 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1127 mmio_reg, mmio_base, mmio_size); 1128 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1129 1130 /* Map high MMIO space */ 1131 high_mmio_alias = g_new0(MemoryRegion, 1); 1132 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1133 mmio_reg, high_mmio_base, high_mmio_size); 1134 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1135 high_mmio_alias); 1136 1137 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1138 1139 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1140 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1141 1142 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1143 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1144 } 1145 1146 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1147 return dev; 1148 } 1149 1150 static FWCfgState *create_fw_cfg(const MachineState *ms) 1151 { 1152 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1153 FWCfgState *fw_cfg; 1154 1155 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1156 &address_space_memory); 1157 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1158 1159 return fw_cfg; 1160 } 1161 1162 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1163 int base_hartid, int hart_count) 1164 { 1165 DeviceState *ret; 1166 g_autofree char *plic_hart_config = NULL; 1167 1168 /* Per-socket PLIC hart topology configuration string */ 1169 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1170 1171 /* Per-socket PLIC */ 1172 ret = sifive_plic_create( 1173 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1174 plic_hart_config, hart_count, base_hartid, 1175 VIRT_IRQCHIP_NUM_SOURCES, 1176 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1177 VIRT_PLIC_PRIORITY_BASE, 1178 VIRT_PLIC_PENDING_BASE, 1179 VIRT_PLIC_ENABLE_BASE, 1180 VIRT_PLIC_ENABLE_STRIDE, 1181 VIRT_PLIC_CONTEXT_BASE, 1182 VIRT_PLIC_CONTEXT_STRIDE, 1183 memmap[VIRT_PLIC].size); 1184 1185 return ret; 1186 } 1187 1188 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1189 const MemMapEntry *memmap, int socket, 1190 int base_hartid, int hart_count) 1191 { 1192 int i; 1193 hwaddr addr; 1194 uint32_t guest_bits; 1195 DeviceState *aplic_s = NULL; 1196 DeviceState *aplic_m = NULL; 1197 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1198 1199 if (msimode) { 1200 if (!kvm_enabled()) { 1201 /* Per-socket M-level IMSICs */ 1202 addr = memmap[VIRT_IMSIC_M].base + 1203 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1204 for (i = 0; i < hart_count; i++) { 1205 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1206 base_hartid + i, true, 1, 1207 VIRT_IRQCHIP_NUM_MSIS); 1208 } 1209 } 1210 1211 /* Per-socket S-level IMSICs */ 1212 guest_bits = imsic_num_bits(aia_guests + 1); 1213 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1214 for (i = 0; i < hart_count; i++) { 1215 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1216 base_hartid + i, false, 1 + aia_guests, 1217 VIRT_IRQCHIP_NUM_MSIS); 1218 } 1219 } 1220 1221 if (!kvm_enabled()) { 1222 /* Per-socket M-level APLIC */ 1223 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1224 socket * memmap[VIRT_APLIC_M].size, 1225 memmap[VIRT_APLIC_M].size, 1226 (msimode) ? 0 : base_hartid, 1227 (msimode) ? 0 : hart_count, 1228 VIRT_IRQCHIP_NUM_SOURCES, 1229 VIRT_IRQCHIP_NUM_PRIO_BITS, 1230 msimode, true, NULL); 1231 } 1232 1233 /* Per-socket S-level APLIC */ 1234 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1235 socket * memmap[VIRT_APLIC_S].size, 1236 memmap[VIRT_APLIC_S].size, 1237 (msimode) ? 0 : base_hartid, 1238 (msimode) ? 0 : hart_count, 1239 VIRT_IRQCHIP_NUM_SOURCES, 1240 VIRT_IRQCHIP_NUM_PRIO_BITS, 1241 msimode, false, aplic_m); 1242 1243 return kvm_enabled() ? aplic_s : aplic_m; 1244 } 1245 1246 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1247 { 1248 DeviceState *dev; 1249 SysBusDevice *sysbus; 1250 const MemMapEntry *memmap = virt_memmap; 1251 int i; 1252 MemoryRegion *sysmem = get_system_memory(); 1253 1254 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1255 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1256 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1257 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1258 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1259 s->platform_bus_dev = dev; 1260 1261 sysbus = SYS_BUS_DEVICE(dev); 1262 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1263 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1264 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1265 } 1266 1267 memory_region_add_subregion(sysmem, 1268 memmap[VIRT_PLATFORM_BUS].base, 1269 sysbus_mmio_get_region(sysbus, 0)); 1270 } 1271 1272 static void virt_build_smbios(RISCVVirtState *s) 1273 { 1274 MachineClass *mc = MACHINE_GET_CLASS(s); 1275 MachineState *ms = MACHINE(s); 1276 uint8_t *smbios_tables, *smbios_anchor; 1277 size_t smbios_tables_len, smbios_anchor_len; 1278 struct smbios_phys_mem_area mem_array; 1279 const char *product = "QEMU Virtual Machine"; 1280 1281 if (kvm_enabled()) { 1282 product = "KVM Virtual Machine"; 1283 } 1284 1285 smbios_set_defaults("QEMU", product, mc->name); 1286 1287 if (riscv_is_32bit(&s->soc[0])) { 1288 smbios_set_default_processor_family(0x200); 1289 } else { 1290 smbios_set_default_processor_family(0x201); 1291 } 1292 1293 /* build the array of physical mem area from base_memmap */ 1294 mem_array.address = s->memmap[VIRT_DRAM].base; 1295 mem_array.length = ms->ram_size; 1296 1297 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1298 &mem_array, 1, 1299 &smbios_tables, &smbios_tables_len, 1300 &smbios_anchor, &smbios_anchor_len, 1301 &error_fatal); 1302 1303 if (smbios_anchor) { 1304 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1305 smbios_tables, smbios_tables_len); 1306 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1307 smbios_anchor, smbios_anchor_len); 1308 } 1309 } 1310 1311 static void virt_machine_done(Notifier *notifier, void *data) 1312 { 1313 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1314 machine_done); 1315 const MemMapEntry *memmap = virt_memmap; 1316 MachineState *machine = MACHINE(s); 1317 target_ulong start_addr = memmap[VIRT_DRAM].base; 1318 target_ulong firmware_end_addr, kernel_start_addr; 1319 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1320 uint64_t fdt_load_addr; 1321 uint64_t kernel_entry = 0; 1322 BlockBackend *pflash_blk0; 1323 1324 /* 1325 * An user provided dtb must include everything, including 1326 * dynamic sysbus devices. Our FDT needs to be finalized. 1327 */ 1328 if (machine->dtb == NULL) { 1329 finalize_fdt(s); 1330 } 1331 1332 /* 1333 * Only direct boot kernel is currently supported for KVM VM, 1334 * so the "-bios" parameter is not supported when KVM is enabled. 1335 */ 1336 if (kvm_enabled()) { 1337 if (machine->firmware) { 1338 if (strcmp(machine->firmware, "none")) { 1339 error_report("Machine mode firmware is not supported in " 1340 "combination with KVM."); 1341 exit(1); 1342 } 1343 } else { 1344 machine->firmware = g_strdup("none"); 1345 } 1346 } 1347 1348 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1349 start_addr, NULL); 1350 1351 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1352 if (pflash_blk0) { 1353 if (machine->firmware && !strcmp(machine->firmware, "none") && 1354 !kvm_enabled()) { 1355 /* 1356 * Pflash was supplied but bios is none and not KVM guest, 1357 * let's overwrite the address we jump to after reset to 1358 * the base of the flash. 1359 */ 1360 start_addr = virt_memmap[VIRT_FLASH].base; 1361 } else { 1362 /* 1363 * Pflash was supplied but either KVM guest or bios is not none. 1364 * In this case, base of the flash would contain S-mode payload. 1365 */ 1366 riscv_setup_firmware_boot(machine); 1367 kernel_entry = virt_memmap[VIRT_FLASH].base; 1368 } 1369 } 1370 1371 if (machine->kernel_filename && !kernel_entry) { 1372 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1373 firmware_end_addr); 1374 1375 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1376 kernel_start_addr, true, NULL); 1377 } 1378 1379 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1380 memmap[VIRT_DRAM].size, 1381 machine); 1382 riscv_load_fdt(fdt_load_addr, machine->fdt); 1383 1384 /* load the reset vector */ 1385 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1386 virt_memmap[VIRT_MROM].base, 1387 virt_memmap[VIRT_MROM].size, kernel_entry, 1388 fdt_load_addr); 1389 1390 /* 1391 * Only direct boot kernel is currently supported for KVM VM, 1392 * So here setup kernel start address and fdt address. 1393 * TODO:Support firmware loading and integrate to TCG start 1394 */ 1395 if (kvm_enabled()) { 1396 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1397 } 1398 1399 virt_build_smbios(s); 1400 1401 if (virt_is_acpi_enabled(s)) { 1402 virt_acpi_setup(s); 1403 } 1404 } 1405 1406 static void virt_machine_init(MachineState *machine) 1407 { 1408 const MemMapEntry *memmap = virt_memmap; 1409 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1410 MemoryRegion *system_memory = get_system_memory(); 1411 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1412 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1413 int i, base_hartid, hart_count; 1414 int socket_count = riscv_socket_count(machine); 1415 1416 /* Check socket count limit */ 1417 if (VIRT_SOCKETS_MAX < socket_count) { 1418 error_report("number of sockets/nodes should be less than %d", 1419 VIRT_SOCKETS_MAX); 1420 exit(1); 1421 } 1422 1423 if (!virt_aclint_allowed() && s->have_aclint) { 1424 error_report("'aclint' is only available with TCG acceleration"); 1425 exit(1); 1426 } 1427 1428 /* Initialize sockets */ 1429 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1430 for (i = 0; i < socket_count; i++) { 1431 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1432 1433 if (!riscv_socket_check_hartids(machine, i)) { 1434 error_report("discontinuous hartids in socket%d", i); 1435 exit(1); 1436 } 1437 1438 base_hartid = riscv_socket_first_hartid(machine, i); 1439 if (base_hartid < 0) { 1440 error_report("can't find hartid base for socket%d", i); 1441 exit(1); 1442 } 1443 1444 hart_count = riscv_socket_hart_count(machine, i); 1445 if (hart_count < 0) { 1446 error_report("can't find hart count for socket%d", i); 1447 exit(1); 1448 } 1449 1450 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1451 TYPE_RISCV_HART_ARRAY); 1452 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1453 machine->cpu_type, &error_abort); 1454 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1455 base_hartid, &error_abort); 1456 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1457 hart_count, &error_abort); 1458 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1459 1460 if (virt_aclint_allowed() && s->have_aclint) { 1461 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1462 /* Per-socket ACLINT MTIMER */ 1463 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1464 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1465 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1466 base_hartid, hart_count, 1467 RISCV_ACLINT_DEFAULT_MTIMECMP, 1468 RISCV_ACLINT_DEFAULT_MTIME, 1469 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1470 } else { 1471 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1472 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1473 i * memmap[VIRT_CLINT].size, 1474 base_hartid, hart_count, false); 1475 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1476 i * memmap[VIRT_CLINT].size + 1477 RISCV_ACLINT_SWI_SIZE, 1478 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1479 base_hartid, hart_count, 1480 RISCV_ACLINT_DEFAULT_MTIMECMP, 1481 RISCV_ACLINT_DEFAULT_MTIME, 1482 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1483 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1484 i * memmap[VIRT_ACLINT_SSWI].size, 1485 base_hartid, hart_count, true); 1486 } 1487 } else if (tcg_enabled()) { 1488 /* Per-socket SiFive CLINT */ 1489 riscv_aclint_swi_create( 1490 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1491 base_hartid, hart_count, false); 1492 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1493 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1494 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1495 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1496 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1497 } 1498 1499 /* Per-socket interrupt controller */ 1500 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1501 s->irqchip[i] = virt_create_plic(memmap, i, 1502 base_hartid, hart_count); 1503 } else { 1504 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1505 memmap, i, base_hartid, 1506 hart_count); 1507 } 1508 1509 /* Try to use different IRQCHIP instance based device type */ 1510 if (i == 0) { 1511 mmio_irqchip = s->irqchip[i]; 1512 virtio_irqchip = s->irqchip[i]; 1513 pcie_irqchip = s->irqchip[i]; 1514 } 1515 if (i == 1) { 1516 virtio_irqchip = s->irqchip[i]; 1517 pcie_irqchip = s->irqchip[i]; 1518 } 1519 if (i == 2) { 1520 pcie_irqchip = s->irqchip[i]; 1521 } 1522 } 1523 1524 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1525 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1526 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1527 memmap[VIRT_APLIC_S].base, 1528 memmap[VIRT_IMSIC_S].base, 1529 s->aia_guests); 1530 } 1531 1532 if (riscv_is_32bit(&s->soc[0])) { 1533 #if HOST_LONG_BITS == 64 1534 /* limit RAM size in a 32-bit system */ 1535 if (machine->ram_size > 10 * GiB) { 1536 machine->ram_size = 10 * GiB; 1537 error_report("Limiting RAM size to 10 GiB"); 1538 } 1539 #endif 1540 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1541 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1542 } else { 1543 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1544 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1545 virt_high_pcie_memmap.base = 1546 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1547 } 1548 1549 s->memmap = virt_memmap; 1550 1551 /* register system main memory (actual RAM) */ 1552 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1553 machine->ram); 1554 1555 /* boot rom */ 1556 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1557 memmap[VIRT_MROM].size, &error_fatal); 1558 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1559 mask_rom); 1560 1561 /* 1562 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1563 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1564 */ 1565 s->fw_cfg = create_fw_cfg(machine); 1566 rom_set_fw(s->fw_cfg); 1567 1568 /* SiFive Test MMIO device */ 1569 sifive_test_create(memmap[VIRT_TEST].base); 1570 1571 /* VirtIO MMIO devices */ 1572 for (i = 0; i < VIRTIO_COUNT; i++) { 1573 sysbus_create_simple("virtio-mmio", 1574 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1575 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1576 } 1577 1578 gpex_pcie_init(system_memory, pcie_irqchip, s); 1579 1580 create_platform_bus(s, mmio_irqchip); 1581 1582 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1583 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1584 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1585 1586 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1587 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1588 1589 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1590 /* Map legacy -drive if=pflash to machine properties */ 1591 pflash_cfi01_legacy_drive(s->flash[i], 1592 drive_get(IF_PFLASH, 0, i)); 1593 } 1594 virt_flash_map(s, system_memory); 1595 1596 /* load/create device tree */ 1597 if (machine->dtb) { 1598 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1599 if (!machine->fdt) { 1600 error_report("load_device_tree() failed"); 1601 exit(1); 1602 } 1603 } else { 1604 create_fdt(s, memmap); 1605 } 1606 1607 s->machine_done.notify = virt_machine_done; 1608 qemu_add_machine_init_done_notifier(&s->machine_done); 1609 } 1610 1611 static void virt_machine_instance_init(Object *obj) 1612 { 1613 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1614 1615 virt_flash_create(s); 1616 1617 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1618 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1619 s->acpi = ON_OFF_AUTO_AUTO; 1620 } 1621 1622 static char *virt_get_aia_guests(Object *obj, Error **errp) 1623 { 1624 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1625 1626 return g_strdup_printf("%d", s->aia_guests); 1627 } 1628 1629 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1630 { 1631 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1632 1633 s->aia_guests = atoi(val); 1634 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1635 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1636 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1637 VIRT_IRQCHIP_MAX_GUESTS); 1638 } 1639 } 1640 1641 static char *virt_get_aia(Object *obj, Error **errp) 1642 { 1643 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1644 const char *val; 1645 1646 switch (s->aia_type) { 1647 case VIRT_AIA_TYPE_APLIC: 1648 val = "aplic"; 1649 break; 1650 case VIRT_AIA_TYPE_APLIC_IMSIC: 1651 val = "aplic-imsic"; 1652 break; 1653 default: 1654 val = "none"; 1655 break; 1656 }; 1657 1658 return g_strdup(val); 1659 } 1660 1661 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1662 { 1663 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1664 1665 if (!strcmp(val, "none")) { 1666 s->aia_type = VIRT_AIA_TYPE_NONE; 1667 } else if (!strcmp(val, "aplic")) { 1668 s->aia_type = VIRT_AIA_TYPE_APLIC; 1669 } else if (!strcmp(val, "aplic-imsic")) { 1670 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1671 } else { 1672 error_setg(errp, "Invalid AIA interrupt controller type"); 1673 error_append_hint(errp, "Valid values are none, aplic, and " 1674 "aplic-imsic.\n"); 1675 } 1676 } 1677 1678 static bool virt_get_aclint(Object *obj, Error **errp) 1679 { 1680 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1681 1682 return s->have_aclint; 1683 } 1684 1685 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1686 { 1687 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1688 1689 s->have_aclint = value; 1690 } 1691 1692 bool virt_is_acpi_enabled(RISCVVirtState *s) 1693 { 1694 return s->acpi != ON_OFF_AUTO_OFF; 1695 } 1696 1697 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1698 void *opaque, Error **errp) 1699 { 1700 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1701 OnOffAuto acpi = s->acpi; 1702 1703 visit_type_OnOffAuto(v, name, &acpi, errp); 1704 } 1705 1706 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1707 void *opaque, Error **errp) 1708 { 1709 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1710 1711 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1712 } 1713 1714 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1715 DeviceState *dev) 1716 { 1717 MachineClass *mc = MACHINE_GET_CLASS(machine); 1718 1719 if (device_is_dynamic_sysbus(mc, dev) || 1720 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1721 return HOTPLUG_HANDLER(machine); 1722 } 1723 return NULL; 1724 } 1725 1726 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1727 DeviceState *dev, Error **errp) 1728 { 1729 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1730 1731 if (s->platform_bus_dev) { 1732 MachineClass *mc = MACHINE_GET_CLASS(s); 1733 1734 if (device_is_dynamic_sysbus(mc, dev)) { 1735 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1736 SYS_BUS_DEVICE(dev)); 1737 } 1738 } 1739 1740 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1741 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1742 } 1743 } 1744 1745 static void virt_machine_class_init(ObjectClass *oc, void *data) 1746 { 1747 MachineClass *mc = MACHINE_CLASS(oc); 1748 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1749 1750 mc->desc = "RISC-V VirtIO board"; 1751 mc->init = virt_machine_init; 1752 mc->max_cpus = VIRT_CPUS_MAX; 1753 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1754 mc->pci_allow_0_address = true; 1755 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1756 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1757 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1758 mc->numa_mem_supported = true; 1759 /* platform instead of architectural choice */ 1760 mc->cpu_cluster_has_numa_boundary = true; 1761 mc->default_ram_id = "riscv_virt_board.ram"; 1762 assert(!mc->get_hotplug_handler); 1763 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1764 1765 hc->plug = virt_machine_device_plug_cb; 1766 1767 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1768 #ifdef CONFIG_TPM 1769 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1770 #endif 1771 1772 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1773 virt_set_aclint); 1774 object_class_property_set_description(oc, "aclint", 1775 "(TCG only) Set on/off to " 1776 "enable/disable emulating " 1777 "ACLINT devices"); 1778 1779 object_class_property_add_str(oc, "aia", virt_get_aia, 1780 virt_set_aia); 1781 object_class_property_set_description(oc, "aia", 1782 "Set type of AIA interrupt " 1783 "controller. Valid values are " 1784 "none, aplic, and aplic-imsic."); 1785 1786 object_class_property_add_str(oc, "aia-guests", 1787 virt_get_aia_guests, 1788 virt_set_aia_guests); 1789 { 1790 g_autofree char *str = 1791 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1792 "Valid value should be between 0 and %d.", 1793 VIRT_IRQCHIP_MAX_GUESTS); 1794 object_class_property_set_description(oc, "aia-guests", str); 1795 } 1796 1797 object_class_property_add(oc, "acpi", "OnOffAuto", 1798 virt_get_acpi, virt_set_acpi, 1799 NULL, NULL); 1800 object_class_property_set_description(oc, "acpi", 1801 "Enable ACPI"); 1802 } 1803 1804 static const TypeInfo virt_machine_typeinfo = { 1805 .name = MACHINE_TYPE_NAME("virt"), 1806 .parent = TYPE_MACHINE, 1807 .class_init = virt_machine_class_init, 1808 .instance_init = virt_machine_instance_init, 1809 .instance_size = sizeof(RISCVVirtState), 1810 .interfaces = (InterfaceInfo[]) { 1811 { TYPE_HOTPLUG_HANDLER }, 1812 { } 1813 }, 1814 }; 1815 1816 static void virt_machine_init_register_types(void) 1817 { 1818 type_register_static(&virt_machine_typeinfo); 1819 } 1820 1821 type_init(virt_machine_init_register_types) 1822