1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/iommu.h"
36 #include "hw/riscv/riscv-iommu-bits.h"
37 #include "hw/riscv/virt.h"
38 #include "hw/riscv/boot.h"
39 #include "hw/riscv/numa.h"
40 #include "kvm/kvm_riscv.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/intc/riscv_aclint.h"
43 #include "hw/intc/riscv_aplic.h"
44 #include "hw/intc/sifive_plic.h"
45 #include "hw/misc/sifive_test.h"
46 #include "hw/platform-bus.h"
47 #include "chardev/char.h"
48 #include "system/device_tree.h"
49 #include "system/system.h"
50 #include "system/tcg.h"
51 #include "system/kvm.h"
52 #include "system/tpm.h"
53 #include "system/qtest.h"
54 #include "hw/pci/pci.h"
55 #include "hw/pci-host/gpex.h"
56 #include "hw/display/ramfb.h"
57 #include "hw/acpi/aml-build.h"
58 #include "qapi/qapi-visit-common.h"
59 #include "hw/virtio/virtio-iommu.h"
60 #include "hw/uefi/var-service-api.h"
61
62 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)63 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
64 {
65 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
66
67 return riscv_is_kvm_aia_aplic_imsic(msimode);
68 }
69
virt_use_emulated_aplic(RISCVVirtAIAType aia_type)70 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
71 {
72 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
73
74 return riscv_use_emulated_aplic(msimode);
75 }
76
virt_aclint_allowed(void)77 static bool virt_aclint_allowed(void)
78 {
79 return tcg_enabled() || qtest_enabled();
80 }
81
82 static const MemMapEntry virt_memmap[] = {
83 [VIRT_DEBUG] = { 0x0, 0x100 },
84 [VIRT_MROM] = { 0x1000, 0xf000 },
85 [VIRT_TEST] = { 0x100000, 0x1000 },
86 [VIRT_RTC] = { 0x101000, 0x1000 },
87 [VIRT_CLINT] = { 0x2000000, 0x10000 },
88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 },
91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
95 [VIRT_UART0] = { 0x10000000, 0x100 },
96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
97 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
98 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
103 [VIRT_DRAM] = { 0x80000000, 0x0 },
104 };
105
106 /* PCIe high mmio is fixed for RV32 */
107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
108 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
109
110 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
111 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
112
113 static MemMapEntry virt_high_pcie_memmap;
114
115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
116
virt_flash_create1(RISCVVirtState * s,const char * name,const char * alias_prop_name)117 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
118 const char *name,
119 const char *alias_prop_name)
120 {
121 /*
122 * Create a single flash device. We use the same parameters as
123 * the flash devices on the ARM virt board.
124 */
125 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
126
127 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
128 qdev_prop_set_uint8(dev, "width", 4);
129 qdev_prop_set_uint8(dev, "device-width", 2);
130 qdev_prop_set_bit(dev, "big-endian", false);
131 qdev_prop_set_uint16(dev, "id0", 0x89);
132 qdev_prop_set_uint16(dev, "id1", 0x18);
133 qdev_prop_set_uint16(dev, "id2", 0x00);
134 qdev_prop_set_uint16(dev, "id3", 0x00);
135 qdev_prop_set_string(dev, "name", name);
136
137 object_property_add_child(OBJECT(s), name, OBJECT(dev));
138 object_property_add_alias(OBJECT(s), alias_prop_name,
139 OBJECT(dev), "drive");
140
141 return PFLASH_CFI01(dev);
142 }
143
virt_flash_create(RISCVVirtState * s)144 static void virt_flash_create(RISCVVirtState *s)
145 {
146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
147 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
148 }
149
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)150 static void virt_flash_map1(PFlashCFI01 *flash,
151 hwaddr base, hwaddr size,
152 MemoryRegion *sysmem)
153 {
154 DeviceState *dev = DEVICE(flash);
155
156 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
157 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
158 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
160
161 memory_region_add_subregion(sysmem, base,
162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
163 0));
164 }
165
virt_flash_map(RISCVVirtState * s,MemoryRegion * sysmem)166 static void virt_flash_map(RISCVVirtState *s,
167 MemoryRegion *sysmem)
168 {
169 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2;
170 hwaddr flashbase = s->memmap[VIRT_FLASH].base;
171
172 virt_flash_map1(s->flash[0], flashbase, flashsize,
173 sysmem);
174 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
175 sysmem);
176 }
177
create_pcie_irq_map(RISCVVirtState * s,void * fdt,char * nodename,uint32_t irqchip_phandle)178 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
179 uint32_t irqchip_phandle)
180 {
181 int pin, dev;
182 uint32_t irq_map_stride = 0;
183 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *
184 FDT_MAX_INT_MAP_WIDTH] = {};
185 uint32_t *irq_map = full_irq_map;
186
187 /* This code creates a standard swizzle of interrupts such that
188 * each device's first interrupt is based on it's PCI_SLOT number.
189 * (See pci_swizzle_map_irq_fn())
190 *
191 * We only need one entry per interrupt in the table (not one per
192 * possible slot) seeing the interrupt-map-mask will allow the table
193 * to wrap to any number of devices.
194 */
195 for (dev = 0; dev < PCI_NUM_PINS; dev++) {
196 int devfn = dev * 0x8;
197
198 for (pin = 0; pin < PCI_NUM_PINS; pin++) {
199 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
200 int i = 0;
201
202 /* Fill PCI address cells */
203 irq_map[i] = cpu_to_be32(devfn << 8);
204 i += FDT_PCI_ADDR_CELLS;
205
206 /* Fill PCI Interrupt cells */
207 irq_map[i] = cpu_to_be32(pin + 1);
208 i += FDT_PCI_INT_CELLS;
209
210 /* Fill interrupt controller phandle and cells */
211 irq_map[i++] = cpu_to_be32(irqchip_phandle);
212 irq_map[i++] = cpu_to_be32(irq_nr);
213 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
214 irq_map[i++] = cpu_to_be32(0x4);
215 }
216
217 if (!irq_map_stride) {
218 irq_map_stride = i;
219 }
220 irq_map += irq_map_stride;
221 }
222 }
223
224 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
225 PCI_NUM_PINS * PCI_NUM_PINS *
226 irq_map_stride * sizeof(uint32_t));
227
228 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
229 0x1800, 0, 0, 0x7);
230 }
231
create_fdt_socket_cpus(RISCVVirtState * s,int socket,char * clust_name,uint32_t * phandle,uint32_t * intc_phandles)232 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
233 char *clust_name, uint32_t *phandle,
234 uint32_t *intc_phandles)
235 {
236 int cpu;
237 uint32_t cpu_phandle;
238 MachineState *ms = MACHINE(s);
239 bool is_32_bit = riscv_is_32bit(&s->soc[0]);
240
241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
242 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
243 int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode;
244 g_autofree char *cpu_name = NULL;
245 g_autofree char *core_name = NULL;
246 g_autofree char *intc_name = NULL;
247 g_autofree char *sv_name = NULL;
248
249 cpu_phandle = (*phandle)++;
250
251 cpu_name = g_strdup_printf("/cpus/cpu@%d",
252 s->soc[socket].hartid_base + cpu);
253 qemu_fdt_add_subnode(ms->fdt, cpu_name);
254
255 if (satp_mode_max != -1) {
256 sv_name = g_strdup_printf("riscv,%s",
257 satp_mode_str(satp_mode_max, is_32_bit));
258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
259 }
260
261 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name);
262
263 if (cpu_ptr->cfg.ext_zicbom) {
264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
265 cpu_ptr->cfg.cbom_blocksize);
266 }
267
268 if (cpu_ptr->cfg.ext_zicboz) {
269 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
270 cpu_ptr->cfg.cboz_blocksize);
271 }
272
273 if (cpu_ptr->cfg.ext_zicbop) {
274 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size",
275 cpu_ptr->cfg.cbop_blocksize);
276 }
277
278 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
280 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
281 s->soc[socket].hartid_base + cpu);
282 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
283 riscv_socket_fdt_write_id(ms, cpu_name, socket);
284 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
285
286 intc_phandles[cpu] = (*phandle)++;
287
288 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
289 qemu_fdt_add_subnode(ms->fdt, intc_name);
290 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
291 intc_phandles[cpu]);
292 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
293 "riscv,cpu-intc");
294 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
295 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
296
297 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
298 qemu_fdt_add_subnode(ms->fdt, core_name);
299 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
300 }
301 }
302
create_fdt_socket_memory(RISCVVirtState * s,int socket)303 static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
304 {
305 g_autofree char *mem_name = NULL;
306 hwaddr addr;
307 uint64_t size;
308 MachineState *ms = MACHINE(s);
309
310 addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
311 size = riscv_socket_mem_size(ms, socket);
312 mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr);
313 qemu_fdt_add_subnode(ms->fdt, mem_name);
314 qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, size);
315 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
316 riscv_socket_fdt_write_id(ms, mem_name, socket);
317 }
318
create_fdt_socket_clint(RISCVVirtState * s,int socket,uint32_t * intc_phandles)319 static void create_fdt_socket_clint(RISCVVirtState *s,
320 int socket,
321 uint32_t *intc_phandles)
322 {
323 int cpu;
324 g_autofree char *clint_name = NULL;
325 g_autofree uint32_t *clint_cells = NULL;
326 hwaddr clint_addr;
327 MachineState *ms = MACHINE(s);
328 static const char * const clint_compat[2] = {
329 "sifive,clint0", "riscv,clint0"
330 };
331
332 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
333
334 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
335 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
336 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
337 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
338 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
339 }
340
341 clint_addr = s->memmap[VIRT_CLINT].base +
342 s->memmap[VIRT_CLINT].size * socket;
343 clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
344 qemu_fdt_add_subnode(ms->fdt, clint_name);
345 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
346 (char **)&clint_compat,
347 ARRAY_SIZE(clint_compat));
348 qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg",
349 2, clint_addr, 2, s->memmap[VIRT_CLINT].size);
350 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
351 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
352 riscv_socket_fdt_write_id(ms, clint_name, socket);
353 }
354
create_fdt_socket_aclint(RISCVVirtState * s,int socket,uint32_t * intc_phandles)355 static void create_fdt_socket_aclint(RISCVVirtState *s,
356 int socket,
357 uint32_t *intc_phandles)
358 {
359 int cpu;
360 char *name;
361 unsigned long addr, size;
362 uint32_t aclint_cells_size;
363 g_autofree uint32_t *aclint_mswi_cells = NULL;
364 g_autofree uint32_t *aclint_sswi_cells = NULL;
365 g_autofree uint32_t *aclint_mtimer_cells = NULL;
366 MachineState *ms = MACHINE(s);
367
368 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
369 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
370 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
371
372 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
373 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
374 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
375 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
376 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
377 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
378 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
379 }
380 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
381
382 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
383 addr = s->memmap[VIRT_CLINT].base +
384 (s->memmap[VIRT_CLINT].size * socket);
385 name = g_strdup_printf("/soc/mswi@%lx", addr);
386
387 qemu_fdt_add_subnode(ms->fdt, name);
388 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
389 "riscv,aclint-mswi");
390 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
391 2, addr, 2, RISCV_ACLINT_SWI_SIZE);
392 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
393 aclint_mswi_cells, aclint_cells_size);
394 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
395 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
396 riscv_socket_fdt_write_id(ms, name, socket);
397 g_free(name);
398 }
399
400 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
401 addr = s->memmap[VIRT_CLINT].base +
402 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
403 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
404 } else {
405 addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
406 (s->memmap[VIRT_CLINT].size * socket);
407 size = s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
408 }
409 name = g_strdup_printf("/soc/mtimer@%lx", addr);
410 qemu_fdt_add_subnode(ms->fdt, name);
411 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
412 "riscv,aclint-mtimer");
413 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
414 2, addr + RISCV_ACLINT_DEFAULT_MTIME,
415 2, size - RISCV_ACLINT_DEFAULT_MTIME,
416 2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
417 2, RISCV_ACLINT_DEFAULT_MTIME);
418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
419 aclint_mtimer_cells, aclint_cells_size);
420 riscv_socket_fdt_write_id(ms, name, socket);
421 g_free(name);
422
423 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
424 addr = s->memmap[VIRT_ACLINT_SSWI].base +
425 (s->memmap[VIRT_ACLINT_SSWI].size * socket);
426
427 name = g_strdup_printf("/soc/sswi@%lx", addr);
428 qemu_fdt_add_subnode(ms->fdt, name);
429 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
430 "riscv,aclint-sswi");
431 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
432 2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size);
433 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
434 aclint_sswi_cells, aclint_cells_size);
435 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
436 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
437 riscv_socket_fdt_write_id(ms, name, socket);
438 g_free(name);
439 }
440 }
441
create_fdt_socket_plic(RISCVVirtState * s,int socket,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * plic_phandles)442 static void create_fdt_socket_plic(RISCVVirtState *s,
443 int socket,
444 uint32_t *phandle, uint32_t *intc_phandles,
445 uint32_t *plic_phandles)
446 {
447 int cpu;
448 g_autofree char *plic_name = NULL;
449 g_autofree uint32_t *plic_cells;
450 unsigned long plic_addr;
451 MachineState *ms = MACHINE(s);
452 static const char * const plic_compat[2] = {
453 "sifive,plic-1.0.0", "riscv,plic0"
454 };
455
456 plic_phandles[socket] = (*phandle)++;
457 plic_addr = s->memmap[VIRT_PLIC].base +
458 (s->memmap[VIRT_PLIC].size * socket);
459 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
460 qemu_fdt_add_subnode(ms->fdt, plic_name);
461 qemu_fdt_setprop_cell(ms->fdt, plic_name,
462 "#interrupt-cells", FDT_PLIC_INT_CELLS);
463 qemu_fdt_setprop_cell(ms->fdt, plic_name,
464 "#address-cells", FDT_PLIC_ADDR_CELLS);
465 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
466 (char **)&plic_compat,
467 ARRAY_SIZE(plic_compat));
468 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
469
470 if (kvm_enabled()) {
471 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
472
473 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
474 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
475 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
476 }
477
478 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
479 plic_cells,
480 s->soc[socket].num_harts * sizeof(uint32_t) * 2);
481 } else {
482 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
483
484 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
485 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
486 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
487 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
488 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
489 }
490
491 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
492 plic_cells,
493 s->soc[socket].num_harts * sizeof(uint32_t) * 4);
494 }
495
496 qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg",
497 2, plic_addr, 2, s->memmap[VIRT_PLIC].size);
498 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
499 VIRT_IRQCHIP_NUM_SOURCES - 1);
500 riscv_socket_fdt_write_id(ms, plic_name, socket);
501 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
502 plic_phandles[socket]);
503
504 if (!socket) {
505 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
506 s->memmap[VIRT_PLATFORM_BUS].base,
507 s->memmap[VIRT_PLATFORM_BUS].size,
508 VIRT_PLATFORM_BUS_IRQ);
509 }
510 }
511
imsic_num_bits(uint32_t count)512 uint32_t imsic_num_bits(uint32_t count)
513 {
514 uint32_t ret = 0;
515
516 while (BIT(ret) < count) {
517 ret++;
518 }
519
520 return ret;
521 }
522
create_fdt_one_imsic(RISCVVirtState * s,hwaddr base_addr,uint32_t * intc_phandles,uint32_t msi_phandle,bool m_mode,uint32_t imsic_guest_bits)523 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
524 uint32_t *intc_phandles, uint32_t msi_phandle,
525 bool m_mode, uint32_t imsic_guest_bits)
526 {
527 int cpu, socket;
528 g_autofree char *imsic_name = NULL;
529 MachineState *ms = MACHINE(s);
530 int socket_count = riscv_socket_count(ms);
531 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size;
532 g_autofree uint32_t *imsic_cells = NULL;
533 g_autofree uint32_t *imsic_regs = NULL;
534 static const char * const imsic_compat[2] = {
535 "qemu,imsics", "riscv,imsics"
536 };
537
538 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
539 imsic_regs = g_new0(uint32_t, socket_count * 4);
540
541 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
542 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
543 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
544 }
545
546 imsic_max_hart_per_socket = 0;
547 for (socket = 0; socket < socket_count; socket++) {
548 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
549 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
550 s->soc[socket].num_harts;
551 imsic_regs[socket * 4 + 0] = 0;
552 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
553 imsic_regs[socket * 4 + 2] = 0;
554 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
555 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
556 imsic_max_hart_per_socket = s->soc[socket].num_harts;
557 }
558 }
559
560 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx",
561 (unsigned long)base_addr);
562 qemu_fdt_add_subnode(ms->fdt, imsic_name);
563 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible",
564 (char **)&imsic_compat,
565 ARRAY_SIZE(imsic_compat));
566
567 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
568 FDT_IMSIC_INT_CELLS);
569 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
570 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
571 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
572 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
573 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
574 socket_count * sizeof(uint32_t) * 4);
575 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
576 VIRT_IRQCHIP_NUM_MSIS);
577
578 if (imsic_guest_bits) {
579 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
580 imsic_guest_bits);
581 }
582
583 if (socket_count > 1) {
584 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
585 imsic_num_bits(imsic_max_hart_per_socket));
586 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
587 imsic_num_bits(socket_count));
588 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
589 IMSIC_MMIO_GROUP_MIN_SHIFT);
590 }
591 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
592 }
593
create_fdt_imsic(RISCVVirtState * s,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * msi_m_phandle,uint32_t * msi_s_phandle)594 static void create_fdt_imsic(RISCVVirtState *s,
595 uint32_t *phandle, uint32_t *intc_phandles,
596 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
597 {
598 *msi_m_phandle = (*phandle)++;
599 *msi_s_phandle = (*phandle)++;
600
601 if (!kvm_enabled()) {
602 /* M-level IMSIC node */
603 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandles,
604 *msi_m_phandle, true, 0);
605 }
606
607 /* S-level IMSIC node */
608 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles,
609 *msi_s_phandle, false,
610 imsic_num_bits(s->aia_guests + 1));
611
612 }
613
614 /* Caller must free string after use */
fdt_get_aplic_nodename(unsigned long aplic_addr)615 static char *fdt_get_aplic_nodename(unsigned long aplic_addr)
616 {
617 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr);
618 }
619
create_fdt_one_aplic(RISCVVirtState * s,int socket,unsigned long aplic_addr,uint32_t aplic_size,uint32_t msi_phandle,uint32_t * intc_phandles,uint32_t aplic_phandle,uint32_t aplic_child_phandle,bool m_mode,int num_harts)620 static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
621 unsigned long aplic_addr, uint32_t aplic_size,
622 uint32_t msi_phandle,
623 uint32_t *intc_phandles,
624 uint32_t aplic_phandle,
625 uint32_t aplic_child_phandle,
626 bool m_mode, int num_harts)
627 {
628 int cpu;
629 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr);
630 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2);
631 MachineState *ms = MACHINE(s);
632 static const char * const aplic_compat[2] = {
633 "qemu,aplic", "riscv,aplic"
634 };
635
636 for (cpu = 0; cpu < num_harts; cpu++) {
637 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
638 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
639 }
640
641 qemu_fdt_add_subnode(ms->fdt, aplic_name);
642 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible",
643 (char **)&aplic_compat,
644 ARRAY_SIZE(aplic_compat));
645 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells",
646 FDT_APLIC_ADDR_CELLS);
647 qemu_fdt_setprop_cell(ms->fdt, aplic_name,
648 "#interrupt-cells", FDT_APLIC_INT_CELLS);
649 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
650
651 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
652 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
653 aplic_cells, num_harts * sizeof(uint32_t) * 2);
654 } else {
655 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
656 }
657
658 qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg",
659 2, aplic_addr, 2, aplic_size);
660 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
661 VIRT_IRQCHIP_NUM_SOURCES);
662
663 if (aplic_child_phandle) {
664 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
665 aplic_child_phandle);
666 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation",
667 aplic_child_phandle, 0x1,
668 VIRT_IRQCHIP_NUM_SOURCES);
669 /*
670 * DEPRECATED_9.1: Compat property kept temporarily
671 * to allow old firmwares to work with AIA. Do *not*
672 * use 'riscv,delegate' in new code: use
673 * 'riscv,delegation' instead.
674 */
675 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
676 aplic_child_phandle, 0x1,
677 VIRT_IRQCHIP_NUM_SOURCES);
678 }
679
680 riscv_socket_fdt_write_id(ms, aplic_name, socket);
681 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
682 }
683
create_fdt_socket_aplic(RISCVVirtState * s,int socket,uint32_t msi_m_phandle,uint32_t msi_s_phandle,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * aplic_phandles,int num_harts)684 static void create_fdt_socket_aplic(RISCVVirtState *s,
685 int socket,
686 uint32_t msi_m_phandle,
687 uint32_t msi_s_phandle,
688 uint32_t *phandle,
689 uint32_t *intc_phandles,
690 uint32_t *aplic_phandles,
691 int num_harts)
692 {
693 unsigned long aplic_addr;
694 MachineState *ms = MACHINE(s);
695 uint32_t aplic_m_phandle, aplic_s_phandle;
696
697 aplic_m_phandle = (*phandle)++;
698 aplic_s_phandle = (*phandle)++;
699
700 if (!kvm_enabled()) {
701 /* M-level APLIC node */
702 aplic_addr = s->memmap[VIRT_APLIC_M].base +
703 (s->memmap[VIRT_APLIC_M].size * socket);
704 create_fdt_one_aplic(s, socket, aplic_addr,
705 s->memmap[VIRT_APLIC_M].size,
706 msi_m_phandle, intc_phandles,
707 aplic_m_phandle, aplic_s_phandle,
708 true, num_harts);
709 }
710
711 /* S-level APLIC node */
712 aplic_addr = s->memmap[VIRT_APLIC_S].base +
713 (s->memmap[VIRT_APLIC_S].size * socket);
714 create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].size,
715 msi_s_phandle, intc_phandles,
716 aplic_s_phandle, 0,
717 false, num_harts);
718
719 if (!socket) {
720 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr);
721 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
722 s->memmap[VIRT_PLATFORM_BUS].base,
723 s->memmap[VIRT_PLATFORM_BUS].size,
724 VIRT_PLATFORM_BUS_IRQ);
725 }
726
727 aplic_phandles[socket] = aplic_s_phandle;
728 }
729
create_fdt_pmu(RISCVVirtState * s)730 static void create_fdt_pmu(RISCVVirtState *s)
731 {
732 g_autofree char *pmu_name = g_strdup_printf("/pmu");
733 MachineState *ms = MACHINE(s);
734 RISCVCPU hart = s->soc[0].harts[0];
735
736 qemu_fdt_add_subnode(ms->fdt, pmu_name);
737 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
738 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);
739 }
740
create_fdt_sockets(RISCVVirtState * s,uint32_t * phandle,uint32_t * irq_mmio_phandle,uint32_t * irq_pcie_phandle,uint32_t * irq_virtio_phandle,uint32_t * msi_pcie_phandle)741 static void create_fdt_sockets(RISCVVirtState *s,
742 uint32_t *phandle,
743 uint32_t *irq_mmio_phandle,
744 uint32_t *irq_pcie_phandle,
745 uint32_t *irq_virtio_phandle,
746 uint32_t *msi_pcie_phandle)
747 {
748 int socket, phandle_pos;
749 MachineState *ms = MACHINE(s);
750 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
751 uint32_t xplic_phandles[MAX_NODES];
752 g_autofree uint32_t *intc_phandles = NULL;
753 int socket_count = riscv_socket_count(ms);
754
755 qemu_fdt_add_subnode(ms->fdt, "/cpus");
756 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
757 kvm_enabled() ?
758 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) :
759 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
760 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
761 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
762 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
763
764 intc_phandles = g_new0(uint32_t, ms->smp.cpus);
765
766 phandle_pos = ms->smp.cpus;
767 for (socket = (socket_count - 1); socket >= 0; socket--) {
768 g_autofree char *clust_name = NULL;
769 phandle_pos -= s->soc[socket].num_harts;
770
771 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
772 qemu_fdt_add_subnode(ms->fdt, clust_name);
773
774 create_fdt_socket_cpus(s, socket, clust_name, phandle,
775 &intc_phandles[phandle_pos]);
776
777 create_fdt_socket_memory(s, socket);
778
779 if (virt_aclint_allowed() && s->have_aclint) {
780 create_fdt_socket_aclint(s, socket,
781 &intc_phandles[phandle_pos]);
782 } else if (tcg_enabled()) {
783 create_fdt_socket_clint(s, socket,
784 &intc_phandles[phandle_pos]);
785 }
786 }
787
788 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
789 create_fdt_imsic(s, phandle, intc_phandles,
790 &msi_m_phandle, &msi_s_phandle);
791 *msi_pcie_phandle = msi_s_phandle;
792 }
793
794 /*
795 * With KVM AIA aplic-imsic, using an irqchip without split
796 * mode, we'll use only one APLIC instance.
797 */
798 if (!virt_use_emulated_aplic(s->aia_type)) {
799 create_fdt_socket_aplic(s, 0,
800 msi_m_phandle, msi_s_phandle, phandle,
801 &intc_phandles[0], xplic_phandles,
802 ms->smp.cpus);
803
804 *irq_mmio_phandle = xplic_phandles[0];
805 *irq_virtio_phandle = xplic_phandles[0];
806 *irq_pcie_phandle = xplic_phandles[0];
807 } else {
808 phandle_pos = ms->smp.cpus;
809 for (socket = (socket_count - 1); socket >= 0; socket--) {
810 phandle_pos -= s->soc[socket].num_harts;
811
812 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
813 create_fdt_socket_plic(s, socket, phandle,
814 &intc_phandles[phandle_pos],
815 xplic_phandles);
816 } else {
817 create_fdt_socket_aplic(s, socket,
818 msi_m_phandle, msi_s_phandle, phandle,
819 &intc_phandles[phandle_pos],
820 xplic_phandles,
821 s->soc[socket].num_harts);
822 }
823 }
824
825 for (socket = 0; socket < socket_count; socket++) {
826 if (socket == 0) {
827 *irq_mmio_phandle = xplic_phandles[socket];
828 *irq_virtio_phandle = xplic_phandles[socket];
829 *irq_pcie_phandle = xplic_phandles[socket];
830 }
831 if (socket == 1) {
832 *irq_virtio_phandle = xplic_phandles[socket];
833 *irq_pcie_phandle = xplic_phandles[socket];
834 }
835 if (socket == 2) {
836 *irq_pcie_phandle = xplic_phandles[socket];
837 }
838 }
839 }
840
841 riscv_socket_fdt_write_distance_matrix(ms);
842 }
843
create_fdt_virtio(RISCVVirtState * s,uint32_t irq_virtio_phandle)844 static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle)
845 {
846 int i;
847 MachineState *ms = MACHINE(s);
848 hwaddr virtio_base = s->memmap[VIRT_VIRTIO].base;
849
850 for (i = 0; i < VIRTIO_COUNT; i++) {
851 g_autofree char *name = NULL;
852 uint64_t size = s->memmap[VIRT_VIRTIO].size;
853 hwaddr addr = virtio_base + i * size;
854
855 name = g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr);
856
857 qemu_fdt_add_subnode(ms->fdt, name);
858 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
859 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size);
860 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
861 irq_virtio_phandle);
862 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
863 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
864 VIRTIO_IRQ + i);
865 } else {
866 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
867 VIRTIO_IRQ + i, 0x4);
868 }
869 }
870 }
871
create_fdt_pcie(RISCVVirtState * s,uint32_t irq_pcie_phandle,uint32_t msi_pcie_phandle,uint32_t iommu_sys_phandle)872 static void create_fdt_pcie(RISCVVirtState *s,
873 uint32_t irq_pcie_phandle,
874 uint32_t msi_pcie_phandle,
875 uint32_t iommu_sys_phandle)
876 {
877 g_autofree char *name = NULL;
878 MachineState *ms = MACHINE(s);
879
880 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
881 s->memmap[VIRT_PCIE_ECAM].base);
882 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
883 FDT_PCI_ADDR_CELLS);
884 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
885 FDT_PCI_INT_CELLS);
886 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
887 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
888 "pci-host-ecam-generic");
889 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
890 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
891 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
892 s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
893 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
894 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
895 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
896 }
897 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2,
898 s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size);
899 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
900 1, FDT_PCI_RANGE_IOPORT, 2, 0,
901 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,
902 1, FDT_PCI_RANGE_MMIO,
903 2, s->memmap[VIRT_PCIE_MMIO].base,
904 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size,
905 1, FDT_PCI_RANGE_MMIO_64BIT,
906 2, virt_high_pcie_memmap.base,
907 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
908
909 if (virt_is_iommu_sys_enabled(s)) {
910 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map",
911 0, iommu_sys_phandle, 0, 0, 0,
912 iommu_sys_phandle, 0, 0xffff);
913 }
914
915 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
916 }
917
create_fdt_reset(RISCVVirtState * s,uint32_t * phandle)918 static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle)
919 {
920 char *name;
921 uint32_t test_phandle;
922 MachineState *ms = MACHINE(s);
923
924 test_phandle = (*phandle)++;
925 name = g_strdup_printf("/soc/test@%"HWADDR_PRIx,
926 s->memmap[VIRT_TEST].base);
927 qemu_fdt_add_subnode(ms->fdt, name);
928 {
929 static const char * const compat[3] = {
930 "sifive,test1", "sifive,test0", "syscon"
931 };
932 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
933 (char **)&compat, ARRAY_SIZE(compat));
934 }
935 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
936 2, s->memmap[VIRT_TEST].base,
937 2, s->memmap[VIRT_TEST].size);
938 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
939 test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
940 g_free(name);
941
942 name = g_strdup_printf("/reboot");
943 qemu_fdt_add_subnode(ms->fdt, name);
944 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
945 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
946 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
947 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
948 g_free(name);
949
950 name = g_strdup_printf("/poweroff");
951 qemu_fdt_add_subnode(ms->fdt, name);
952 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
953 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
954 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
955 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
956 g_free(name);
957 }
958
create_fdt_uart(RISCVVirtState * s,uint32_t irq_mmio_phandle)959 static void create_fdt_uart(RISCVVirtState *s,
960 uint32_t irq_mmio_phandle)
961 {
962 g_autofree char *name = NULL;
963 MachineState *ms = MACHINE(s);
964
965 name = g_strdup_printf("/soc/serial@%"HWADDR_PRIx,
966 s->memmap[VIRT_UART0].base);
967 qemu_fdt_add_subnode(ms->fdt, name);
968 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
969 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
970 2, s->memmap[VIRT_UART0].base,
971 2, s->memmap[VIRT_UART0].size);
972 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
973 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
974 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
975 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
976 } else {
977 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
978 }
979
980 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
981 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name);
982 }
983
create_fdt_rtc(RISCVVirtState * s,uint32_t irq_mmio_phandle)984 static void create_fdt_rtc(RISCVVirtState *s,
985 uint32_t irq_mmio_phandle)
986 {
987 g_autofree char *name = NULL;
988 MachineState *ms = MACHINE(s);
989
990 name = g_strdup_printf("/soc/rtc@%"HWADDR_PRIx,
991 s->memmap[VIRT_RTC].base);
992 qemu_fdt_add_subnode(ms->fdt, name);
993 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
994 "google,goldfish-rtc");
995 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
996 2, s->memmap[VIRT_RTC].base,
997 2, s->memmap[VIRT_RTC].size);
998 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
999 irq_mmio_phandle);
1000 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1001 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
1002 } else {
1003 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
1004 }
1005 }
1006
create_fdt_flash(RISCVVirtState * s)1007 static void create_fdt_flash(RISCVVirtState *s)
1008 {
1009 MachineState *ms = MACHINE(s);
1010 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2;
1011 hwaddr flashbase = s->memmap[VIRT_FLASH].base;
1012 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase);
1013
1014 qemu_fdt_add_subnode(ms->fdt, name);
1015 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
1016 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
1017 2, flashbase, 2, flashsize,
1018 2, flashbase + flashsize, 2, flashsize);
1019 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
1020 }
1021
create_fdt_fw_cfg(RISCVVirtState * s)1022 static void create_fdt_fw_cfg(RISCVVirtState *s)
1023 {
1024 MachineState *ms = MACHINE(s);
1025 hwaddr base = s->memmap[VIRT_FW_CFG].base;
1026 hwaddr size = s->memmap[VIRT_FW_CFG].size;
1027 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1028
1029 qemu_fdt_add_subnode(ms->fdt, nodename);
1030 qemu_fdt_setprop_string(ms->fdt, nodename,
1031 "compatible", "qemu,fw-cfg-mmio");
1032 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1033 2, base, 2, size);
1034 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1035 }
1036
create_fdt_virtio_iommu(RISCVVirtState * s,uint16_t bdf)1037 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
1038 {
1039 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1040 void *fdt = MACHINE(s)->fdt;
1041 uint32_t iommu_phandle;
1042 g_autofree char *iommu_node = NULL;
1043 g_autofree char *pci_node = NULL;
1044
1045 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1046 s->memmap[VIRT_PCIE_ECAM].base);
1047 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
1048 PCI_SLOT(bdf), PCI_FUNC(bdf));
1049 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1050
1051 qemu_fdt_add_subnode(fdt, iommu_node);
1052
1053 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
1054 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
1055 1, bdf << 8, 1, 0, 1, 0,
1056 1, 0, 1, 0);
1057 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1058 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1059
1060 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
1061 0, iommu_phandle, 0, bdf,
1062 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
1063 }
1064
create_fdt_iommu_sys(RISCVVirtState * s,uint32_t irq_chip,uint32_t msi_phandle,uint32_t * iommu_sys_phandle)1065 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
1066 uint32_t msi_phandle,
1067 uint32_t *iommu_sys_phandle)
1068 {
1069 const char comp[] = "riscv,iommu";
1070 void *fdt = MACHINE(s)->fdt;
1071 uint32_t iommu_phandle;
1072 g_autofree char *iommu_node = NULL;
1073 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base;
1074 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size;
1075 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {
1076 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
1077 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
1078 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
1079 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
1080 };
1081
1082 iommu_node = g_strdup_printf("/soc/iommu@%x",
1083 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base);
1084 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1085 qemu_fdt_add_subnode(fdt, iommu_node);
1086
1087 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
1088 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1089 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1090
1091 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
1092 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
1093
1094 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
1095 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
1096 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
1097 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
1098 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
1099
1100 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
1101
1102 *iommu_sys_phandle = iommu_phandle;
1103 }
1104
create_fdt_iommu(RISCVVirtState * s,uint16_t bdf)1105 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
1106 {
1107 const char comp[] = "riscv,pci-iommu";
1108 void *fdt = MACHINE(s)->fdt;
1109 uint32_t iommu_phandle;
1110 g_autofree char *iommu_node = NULL;
1111 g_autofree char *pci_node = NULL;
1112
1113 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1114 s->memmap[VIRT_PCIE_ECAM].base);
1115 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf);
1116 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1117 qemu_fdt_add_subnode(fdt, iommu_node);
1118
1119 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
1120 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1121 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1122 qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
1123 bdf << 8, 0, 0, 0, 0);
1124 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
1125 0, iommu_phandle, 0, bdf,
1126 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
1127 s->pci_iommu_bdf = bdf;
1128 }
1129
finalize_fdt(RISCVVirtState * s)1130 static void finalize_fdt(RISCVVirtState *s)
1131 {
1132 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1133 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1134 uint32_t iommu_sys_phandle = 1;
1135
1136 create_fdt_sockets(s, &phandle, &irq_mmio_phandle,
1137 &irq_pcie_phandle, &irq_virtio_phandle,
1138 &msi_pcie_phandle);
1139
1140 create_fdt_virtio(s, irq_virtio_phandle);
1141
1142 if (virt_is_iommu_sys_enabled(s)) {
1143 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
1144 &iommu_sys_phandle);
1145 }
1146 create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle,
1147 iommu_sys_phandle);
1148
1149 create_fdt_reset(s, &phandle);
1150
1151 create_fdt_uart(s, irq_mmio_phandle);
1152
1153 create_fdt_rtc(s, irq_mmio_phandle);
1154 }
1155
create_fdt(RISCVVirtState * s)1156 static void create_fdt(RISCVVirtState *s)
1157 {
1158 MachineState *ms = MACHINE(s);
1159 uint8_t rng_seed[32];
1160 g_autofree char *name = NULL;
1161
1162 ms->fdt = create_device_tree(&s->fdt_size);
1163 if (!ms->fdt) {
1164 error_report("create_device_tree() failed");
1165 exit(1);
1166 }
1167
1168 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
1169 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
1170 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
1171 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
1172
1173 qemu_fdt_add_subnode(ms->fdt, "/soc");
1174 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
1175 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
1176 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
1177 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
1178
1179 /*
1180 * The "/soc/pci@..." node is needed for PCIE hotplugs
1181 * that might happen before finalize_fdt().
1182 */
1183 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1184 s->memmap[VIRT_PCIE_ECAM].base);
1185 qemu_fdt_add_subnode(ms->fdt, name);
1186
1187 qemu_fdt_add_subnode(ms->fdt, "/chosen");
1188
1189 /* Pass seed to RNG */
1190 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
1191 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
1192 rng_seed, sizeof(rng_seed));
1193
1194 qemu_fdt_add_subnode(ms->fdt, "/aliases");
1195
1196 create_fdt_flash(s);
1197 create_fdt_fw_cfg(s);
1198 create_fdt_pmu(s);
1199 }
1200
gpex_pcie_init(MemoryRegion * sys_mem,DeviceState * irqchip,RISCVVirtState * s)1201 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1202 DeviceState *irqchip,
1203 RISCVVirtState *s)
1204 {
1205 DeviceState *dev;
1206 MemoryRegion *ecam_alias, *ecam_reg;
1207 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1208 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
1209 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
1210 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
1211 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
1212 hwaddr high_mmio_base = virt_high_pcie_memmap.base;
1213 hwaddr high_mmio_size = virt_high_pcie_memmap.size;
1214 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
1215 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
1216 qemu_irq irq;
1217 int i;
1218
1219 dev = qdev_new(TYPE_GPEX_HOST);
1220
1221 /* Set GPEX object properties for the virt machine */
1222 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE,
1223 ecam_base, NULL);
1224 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE,
1225 ecam_size, NULL);
1226 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE,
1227 mmio_base, NULL);
1228 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE,
1229 mmio_size, NULL);
1230 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE,
1231 high_mmio_base, NULL);
1232 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE,
1233 high_mmio_size, NULL);
1234 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE,
1235 pio_base, NULL);
1236 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE,
1237 pio_size, NULL);
1238
1239 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1240
1241 ecam_alias = g_new0(MemoryRegion, 1);
1242 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1243 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1244 ecam_reg, 0, ecam_size);
1245 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1246
1247 mmio_alias = g_new0(MemoryRegion, 1);
1248 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1249 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1250 mmio_reg, mmio_base, mmio_size);
1251 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1252
1253 /* Map high MMIO space */
1254 high_mmio_alias = g_new0(MemoryRegion, 1);
1255 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1256 mmio_reg, high_mmio_base, high_mmio_size);
1257 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1258 high_mmio_alias);
1259
1260 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1261
1262 for (i = 0; i < PCI_NUM_PINS; i++) {
1263 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1264
1265 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1266 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1267 }
1268
1269 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus;
1270 return dev;
1271 }
1272
create_fw_cfg(const MachineState * ms,hwaddr base)1273 static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base)
1274 {
1275 FWCfgState *fw_cfg;
1276
1277 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1278 &address_space_memory);
1279 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1280
1281 return fw_cfg;
1282 }
1283
virt_create_plic(const MemMapEntry * memmap,int socket,int base_hartid,int hart_count)1284 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1285 int base_hartid, int hart_count)
1286 {
1287 g_autofree char *plic_hart_config = NULL;
1288
1289 /* Per-socket PLIC hart topology configuration string */
1290 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1291
1292 /* Per-socket PLIC */
1293 return sifive_plic_create(
1294 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1295 plic_hart_config, hart_count, base_hartid,
1296 VIRT_IRQCHIP_NUM_SOURCES,
1297 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1298 VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE,
1299 VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE,
1300 VIRT_PLIC_CONTEXT_BASE,
1301 VIRT_PLIC_CONTEXT_STRIDE,
1302 memmap[VIRT_PLIC].size);
1303 }
1304
virt_create_aia(RISCVVirtAIAType aia_type,int aia_guests,const MemMapEntry * memmap,int socket,int base_hartid,int hart_count)1305 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1306 const MemMapEntry *memmap, int socket,
1307 int base_hartid, int hart_count)
1308 {
1309 int i;
1310 hwaddr addr = 0;
1311 uint32_t guest_bits;
1312 DeviceState *aplic_s = NULL;
1313 DeviceState *aplic_m = NULL;
1314 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
1315
1316 if (msimode) {
1317 if (!kvm_enabled()) {
1318 /* Per-socket M-level IMSICs */
1319 addr = memmap[VIRT_IMSIC_M].base +
1320 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1321 for (i = 0; i < hart_count; i++) {
1322 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1323 base_hartid + i, true, 1,
1324 VIRT_IRQCHIP_NUM_MSIS);
1325 }
1326 }
1327
1328 /* Per-socket S-level IMSICs */
1329 guest_bits = imsic_num_bits(aia_guests + 1);
1330 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1331 for (i = 0; i < hart_count; i++) {
1332 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1333 base_hartid + i, false, 1 + aia_guests,
1334 VIRT_IRQCHIP_NUM_MSIS);
1335 }
1336 }
1337
1338 if (!kvm_enabled()) {
1339 /* Per-socket M-level APLIC */
1340 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
1341 socket * memmap[VIRT_APLIC_M].size,
1342 memmap[VIRT_APLIC_M].size,
1343 (msimode) ? 0 : base_hartid,
1344 (msimode) ? 0 : hart_count,
1345 VIRT_IRQCHIP_NUM_SOURCES,
1346 VIRT_IRQCHIP_NUM_PRIO_BITS,
1347 msimode, true, NULL);
1348 }
1349
1350 /* Per-socket S-level APLIC */
1351 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
1352 socket * memmap[VIRT_APLIC_S].size,
1353 memmap[VIRT_APLIC_S].size,
1354 (msimode) ? 0 : base_hartid,
1355 (msimode) ? 0 : hart_count,
1356 VIRT_IRQCHIP_NUM_SOURCES,
1357 VIRT_IRQCHIP_NUM_PRIO_BITS,
1358 msimode, false, aplic_m);
1359
1360 if (kvm_enabled() && msimode) {
1361 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
1362 }
1363
1364 return kvm_enabled() ? aplic_s : aplic_m;
1365 }
1366
create_platform_bus(RISCVVirtState * s,DeviceState * irqchip)1367 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1368 {
1369 DeviceState *dev;
1370 SysBusDevice *sysbus;
1371 int i;
1372 MemoryRegion *sysmem = get_system_memory();
1373
1374 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1375 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1376 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1377 qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size);
1378 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1379 s->platform_bus_dev = dev;
1380
1381 sysbus = SYS_BUS_DEVICE(dev);
1382 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1383 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1384 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1385 }
1386
1387 memory_region_add_subregion(sysmem,
1388 s->memmap[VIRT_PLATFORM_BUS].base,
1389 sysbus_mmio_get_region(sysbus, 0));
1390 }
1391
virt_build_smbios(RISCVVirtState * s)1392 static void virt_build_smbios(RISCVVirtState *s)
1393 {
1394 MachineClass *mc = MACHINE_GET_CLASS(s);
1395 MachineState *ms = MACHINE(s);
1396 uint8_t *smbios_tables, *smbios_anchor;
1397 size_t smbios_tables_len, smbios_anchor_len;
1398 struct smbios_phys_mem_area mem_array;
1399 const char *product = "QEMU Virtual Machine";
1400
1401 if (kvm_enabled()) {
1402 product = "KVM Virtual Machine";
1403 }
1404
1405 smbios_set_defaults("QEMU", product, mc->name);
1406
1407 if (riscv_is_32bit(&s->soc[0])) {
1408 smbios_set_default_processor_family(0x200);
1409 } else {
1410 smbios_set_default_processor_family(0x201);
1411 }
1412
1413 /* build the array of physical mem area from base_memmap */
1414 mem_array.address = s->memmap[VIRT_DRAM].base;
1415 mem_array.length = ms->ram_size;
1416
1417 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
1418 &mem_array, 1,
1419 &smbios_tables, &smbios_tables_len,
1420 &smbios_anchor, &smbios_anchor_len,
1421 &error_fatal);
1422
1423 if (smbios_anchor) {
1424 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables",
1425 smbios_tables, smbios_tables_len);
1426 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor",
1427 smbios_anchor, smbios_anchor_len);
1428 }
1429 }
1430
virt_machine_done(Notifier * notifier,void * data)1431 static void virt_machine_done(Notifier *notifier, void *data)
1432 {
1433 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1434 machine_done);
1435 MachineState *machine = MACHINE(s);
1436 hwaddr start_addr = s->memmap[VIRT_DRAM].base;
1437 target_ulong firmware_end_addr, kernel_start_addr;
1438 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
1439 uint64_t fdt_load_addr;
1440 uint64_t kernel_entry = 0;
1441 BlockBackend *pflash_blk0;
1442 RISCVBootInfo boot_info;
1443
1444 /*
1445 * An user provided dtb must include everything, including
1446 * dynamic sysbus devices. Our FDT needs to be finalized.
1447 */
1448 if (machine->dtb == NULL) {
1449 finalize_fdt(s);
1450 }
1451
1452 /*
1453 * Only direct boot kernel is currently supported for KVM VM,
1454 * so the "-bios" parameter is not supported when KVM is enabled.
1455 */
1456 if (kvm_enabled()) {
1457 if (machine->firmware) {
1458 if (strcmp(machine->firmware, "none")) {
1459 error_report("Machine mode firmware is not supported in "
1460 "combination with KVM.");
1461 exit(1);
1462 }
1463 } else {
1464 machine->firmware = g_strdup("none");
1465 }
1466 }
1467
1468 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
1469 &start_addr, NULL);
1470
1471 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
1472 if (pflash_blk0) {
1473 if (machine->firmware && !strcmp(machine->firmware, "none") &&
1474 !kvm_enabled()) {
1475 /*
1476 * Pflash was supplied but bios is none and not KVM guest,
1477 * let's overwrite the address we jump to after reset to
1478 * the base of the flash.
1479 */
1480 start_addr = s->memmap[VIRT_FLASH].base;
1481 } else {
1482 /*
1483 * Pflash was supplied but either KVM guest or bios is not none.
1484 * In this case, base of the flash would contain S-mode payload.
1485 */
1486 riscv_setup_firmware_boot(machine);
1487 kernel_entry = s->memmap[VIRT_FLASH].base;
1488 }
1489 }
1490
1491 riscv_boot_info_init(&boot_info, &s->soc[0]);
1492
1493 if (machine->kernel_filename && !kernel_entry) {
1494 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
1495 firmware_end_addr);
1496 riscv_load_kernel(machine, &boot_info, kernel_start_addr,
1497 true, NULL);
1498 kernel_entry = boot_info.image_low_addr;
1499 }
1500
1501 fdt_load_addr = riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base,
1502 s->memmap[VIRT_DRAM].size,
1503 machine, &boot_info);
1504 riscv_load_fdt(fdt_load_addr, machine->fdt);
1505
1506 /* load the reset vector */
1507 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1508 s->memmap[VIRT_MROM].base,
1509 s->memmap[VIRT_MROM].size, kernel_entry,
1510 fdt_load_addr);
1511
1512 /*
1513 * Only direct boot kernel is currently supported for KVM VM,
1514 * So here setup kernel start address and fdt address.
1515 * TODO:Support firmware loading and integrate to TCG start
1516 */
1517 if (kvm_enabled()) {
1518 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1519 }
1520
1521 virt_build_smbios(s);
1522
1523 if (virt_is_acpi_enabled(s)) {
1524 virt_acpi_setup(s);
1525 }
1526 }
1527
virt_machine_init(MachineState * machine)1528 static void virt_machine_init(MachineState *machine)
1529 {
1530 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1531 MemoryRegion *system_memory = get_system_memory();
1532 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1533 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1534 int i, base_hartid, hart_count;
1535 int socket_count = riscv_socket_count(machine);
1536
1537 s->memmap = virt_memmap;
1538
1539 /* Check socket count limit */
1540 if (VIRT_SOCKETS_MAX < socket_count) {
1541 error_report("number of sockets/nodes should be less than %d",
1542 VIRT_SOCKETS_MAX);
1543 exit(1);
1544 }
1545
1546 if (!virt_aclint_allowed() && s->have_aclint) {
1547 error_report("'aclint' is only available with TCG acceleration");
1548 exit(1);
1549 }
1550
1551 /* Initialize sockets */
1552 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1553 for (i = 0; i < socket_count; i++) {
1554 g_autofree char *soc_name = g_strdup_printf("soc%d", i);
1555
1556 if (!riscv_socket_check_hartids(machine, i)) {
1557 error_report("discontinuous hartids in socket%d", i);
1558 exit(1);
1559 }
1560
1561 base_hartid = riscv_socket_first_hartid(machine, i);
1562 if (base_hartid < 0) {
1563 error_report("can't find hartid base for socket%d", i);
1564 exit(1);
1565 }
1566
1567 hart_count = riscv_socket_hart_count(machine, i);
1568 if (hart_count < 0) {
1569 error_report("can't find hart count for socket%d", i);
1570 exit(1);
1571 }
1572
1573 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1574 TYPE_RISCV_HART_ARRAY);
1575 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1576 machine->cpu_type, &error_abort);
1577 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1578 base_hartid, &error_abort);
1579 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1580 hart_count, &error_abort);
1581 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1582
1583 if (virt_aclint_allowed() && s->have_aclint) {
1584 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1585 /* Per-socket ACLINT MTIMER */
1586 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1587 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1588 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1589 base_hartid, hart_count,
1590 RISCV_ACLINT_DEFAULT_MTIMECMP,
1591 RISCV_ACLINT_DEFAULT_MTIME,
1592 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1593 } else {
1594 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1595 riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base +
1596 i * s->memmap[VIRT_CLINT].size,
1597 base_hartid, hart_count, false);
1598 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1599 i * s->memmap[VIRT_CLINT].size +
1600 RISCV_ACLINT_SWI_SIZE,
1601 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1602 base_hartid, hart_count,
1603 RISCV_ACLINT_DEFAULT_MTIMECMP,
1604 RISCV_ACLINT_DEFAULT_MTIME,
1605 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1606 riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base +
1607 i * s->memmap[VIRT_ACLINT_SSWI].size,
1608 base_hartid, hart_count, true);
1609 }
1610 } else if (tcg_enabled()) {
1611 /* Per-socket SiFive CLINT */
1612 riscv_aclint_swi_create(
1613 s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size,
1614 base_hartid, hart_count, false);
1615 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1616 i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1617 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1618 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1619 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1620 }
1621
1622 /* Per-socket interrupt controller */
1623 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1624 s->irqchip[i] = virt_create_plic(s->memmap, i,
1625 base_hartid, hart_count);
1626 } else {
1627 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1628 s->memmap, i, base_hartid,
1629 hart_count);
1630 }
1631
1632 /* Try to use different IRQCHIP instance based device type */
1633 if (i == 0) {
1634 mmio_irqchip = s->irqchip[i];
1635 virtio_irqchip = s->irqchip[i];
1636 pcie_irqchip = s->irqchip[i];
1637 }
1638 if (i == 1) {
1639 virtio_irqchip = s->irqchip[i];
1640 pcie_irqchip = s->irqchip[i];
1641 }
1642 if (i == 2) {
1643 pcie_irqchip = s->irqchip[i];
1644 }
1645 }
1646
1647 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
1648 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
1649 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
1650 s->memmap[VIRT_APLIC_S].base,
1651 s->memmap[VIRT_IMSIC_S].base,
1652 s->aia_guests);
1653 }
1654
1655 if (riscv_is_32bit(&s->soc[0])) {
1656 #if HOST_LONG_BITS == 64
1657 /* limit RAM size in a 32-bit system */
1658 if (machine->ram_size > 10 * GiB) {
1659 machine->ram_size = 10 * GiB;
1660 error_report("Limiting RAM size to 10 GiB");
1661 }
1662 #endif
1663 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1664 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1665 } else {
1666 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1667 virt_high_pcie_memmap.base = s->memmap[VIRT_DRAM].base +
1668 machine->ram_size;
1669 virt_high_pcie_memmap.base =
1670 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1671 }
1672
1673 /* register system main memory (actual RAM) */
1674 memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base,
1675 machine->ram);
1676
1677 /* boot rom */
1678 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1679 s->memmap[VIRT_MROM].size, &error_fatal);
1680 memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base,
1681 mask_rom);
1682
1683 /*
1684 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1685 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1686 */
1687 s->fw_cfg = create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base);
1688 rom_set_fw(s->fw_cfg);
1689
1690 /* SiFive Test MMIO device */
1691 sifive_test_create(s->memmap[VIRT_TEST].base);
1692
1693 /* VirtIO MMIO devices */
1694 for (i = 0; i < VIRTIO_COUNT; i++) {
1695 sysbus_create_simple("virtio-mmio",
1696 s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size,
1697 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
1698 }
1699
1700 gpex_pcie_init(system_memory, pcie_irqchip, s);
1701
1702 create_platform_bus(s, mmio_irqchip);
1703
1704 serial_mm_init(system_memory, s->memmap[VIRT_UART0].base,
1705 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193,
1706 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1707
1708 sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base,
1709 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ));
1710
1711 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1712 /* Map legacy -drive if=pflash to machine properties */
1713 pflash_cfi01_legacy_drive(s->flash[i],
1714 drive_get(IF_PFLASH, 0, i));
1715 }
1716 virt_flash_map(s, system_memory);
1717
1718 /* load/create device tree */
1719 if (machine->dtb) {
1720 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
1721 if (!machine->fdt) {
1722 error_report("load_device_tree() failed");
1723 exit(1);
1724 }
1725 } else {
1726 create_fdt(s);
1727 }
1728
1729 if (virt_is_iommu_sys_enabled(s)) {
1730 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
1731
1732 object_property_set_uint(OBJECT(iommu_sys), "addr",
1733 s->memmap[VIRT_IOMMU_SYS].base,
1734 &error_fatal);
1735 object_property_set_uint(OBJECT(iommu_sys), "base-irq",
1736 IOMMU_SYS_IRQ,
1737 &error_fatal);
1738 object_property_set_link(OBJECT(iommu_sys), "irqchip",
1739 OBJECT(mmio_irqchip),
1740 &error_fatal);
1741
1742 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
1743 }
1744
1745 s->machine_done.notify = virt_machine_done;
1746 qemu_add_machine_init_done_notifier(&s->machine_done);
1747 }
1748
virt_machine_instance_init(Object * obj)1749 static void virt_machine_instance_init(Object *obj)
1750 {
1751 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1752
1753 virt_flash_create(s);
1754
1755 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
1756 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
1757 s->acpi = ON_OFF_AUTO_AUTO;
1758 s->iommu_sys = ON_OFF_AUTO_AUTO;
1759 }
1760
virt_get_aia_guests(Object * obj,Error ** errp)1761 static char *virt_get_aia_guests(Object *obj, Error **errp)
1762 {
1763 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1764
1765 return g_strdup_printf("%d", s->aia_guests);
1766 }
1767
virt_set_aia_guests(Object * obj,const char * val,Error ** errp)1768 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1769 {
1770 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1771
1772 s->aia_guests = atoi(val);
1773 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1774 error_setg(errp, "Invalid number of AIA IMSIC guests");
1775 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1776 VIRT_IRQCHIP_MAX_GUESTS);
1777 }
1778 }
1779
virt_get_aia(Object * obj,Error ** errp)1780 static char *virt_get_aia(Object *obj, Error **errp)
1781 {
1782 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1783 const char *val;
1784
1785 switch (s->aia_type) {
1786 case VIRT_AIA_TYPE_APLIC:
1787 val = "aplic";
1788 break;
1789 case VIRT_AIA_TYPE_APLIC_IMSIC:
1790 val = "aplic-imsic";
1791 break;
1792 default:
1793 val = "none";
1794 break;
1795 };
1796
1797 return g_strdup(val);
1798 }
1799
virt_set_aia(Object * obj,const char * val,Error ** errp)1800 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1801 {
1802 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1803
1804 if (!strcmp(val, "none")) {
1805 s->aia_type = VIRT_AIA_TYPE_NONE;
1806 } else if (!strcmp(val, "aplic")) {
1807 s->aia_type = VIRT_AIA_TYPE_APLIC;
1808 } else if (!strcmp(val, "aplic-imsic")) {
1809 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1810 } else {
1811 error_setg(errp, "Invalid AIA interrupt controller type");
1812 error_append_hint(errp, "Valid values are none, aplic, and "
1813 "aplic-imsic.\n");
1814 }
1815 }
1816
virt_get_aclint(Object * obj,Error ** errp)1817 static bool virt_get_aclint(Object *obj, Error **errp)
1818 {
1819 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1820
1821 return s->have_aclint;
1822 }
1823
virt_set_aclint(Object * obj,bool value,Error ** errp)1824 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1825 {
1826 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1827
1828 s->have_aclint = value;
1829 }
1830
virt_is_iommu_sys_enabled(RISCVVirtState * s)1831 bool virt_is_iommu_sys_enabled(RISCVVirtState *s)
1832 {
1833 return s->iommu_sys == ON_OFF_AUTO_ON;
1834 }
1835
virt_get_iommu_sys(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1836 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name,
1837 void *opaque, Error **errp)
1838 {
1839 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1840 OnOffAuto iommu_sys = s->iommu_sys;
1841
1842 visit_type_OnOffAuto(v, name, &iommu_sys, errp);
1843 }
1844
virt_set_iommu_sys(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1845 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
1846 void *opaque, Error **errp)
1847 {
1848 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1849
1850 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
1851 }
1852
virt_is_acpi_enabled(RISCVVirtState * s)1853 bool virt_is_acpi_enabled(RISCVVirtState *s)
1854 {
1855 return s->acpi != ON_OFF_AUTO_OFF;
1856 }
1857
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1858 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
1859 void *opaque, Error **errp)
1860 {
1861 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1862 OnOffAuto acpi = s->acpi;
1863
1864 visit_type_OnOffAuto(v, name, &acpi, errp);
1865 }
1866
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1867 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
1868 void *opaque, Error **errp)
1869 {
1870 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1871
1872 visit_type_OnOffAuto(v, name, &s->acpi, errp);
1873 }
1874
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)1875 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1876 DeviceState *dev)
1877 {
1878 MachineClass *mc = MACHINE_GET_CLASS(machine);
1879 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1880
1881 if (device_is_dynamic_sysbus(mc, dev) ||
1882 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1883 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
1884 s->iommu_sys = ON_OFF_AUTO_OFF;
1885 return HOTPLUG_HANDLER(machine);
1886 }
1887
1888 return NULL;
1889 }
1890
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1891 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1892 DeviceState *dev, Error **errp)
1893 {
1894 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1895
1896 if (s->platform_bus_dev) {
1897 MachineClass *mc = MACHINE_GET_CLASS(s);
1898
1899 if (device_is_dynamic_sysbus(mc, dev)) {
1900 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1901 SYS_BUS_DEVICE(dev));
1902 }
1903 }
1904
1905 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1906 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
1907 }
1908
1909 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
1910 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
1911 s->iommu_sys = ON_OFF_AUTO_OFF;
1912 }
1913 }
1914
virt_machine_class_init(ObjectClass * oc,const void * data)1915 static void virt_machine_class_init(ObjectClass *oc, const void *data)
1916 {
1917 MachineClass *mc = MACHINE_CLASS(oc);
1918 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1919
1920 mc->desc = "RISC-V VirtIO board";
1921 mc->init = virt_machine_init;
1922 mc->max_cpus = VIRT_CPUS_MAX;
1923 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1924 mc->block_default_type = IF_VIRTIO;
1925 mc->no_cdrom = 1;
1926 mc->pci_allow_0_address = true;
1927 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1928 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1929 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1930 mc->numa_mem_supported = true;
1931 /* platform instead of architectural choice */
1932 mc->cpu_cluster_has_numa_boundary = true;
1933 mc->default_ram_id = "riscv_virt_board.ram";
1934 assert(!mc->get_hotplug_handler);
1935 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1936
1937 hc->plug = virt_machine_device_plug_cb;
1938
1939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
1941 #ifdef CONFIG_TPM
1942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1943 #endif
1944
1945 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1946 virt_set_aclint);
1947 object_class_property_set_description(oc, "aclint",
1948 "(TCG only) Set on/off to "
1949 "enable/disable emulating "
1950 "ACLINT devices");
1951
1952 object_class_property_add_str(oc, "aia", virt_get_aia,
1953 virt_set_aia);
1954 object_class_property_set_description(oc, "aia",
1955 "Set type of AIA interrupt "
1956 "controller. Valid values are "
1957 "none, aplic, and aplic-imsic.");
1958
1959 object_class_property_add_str(oc, "aia-guests",
1960 virt_get_aia_guests,
1961 virt_set_aia_guests);
1962 {
1963 g_autofree char *str =
1964 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. "
1965 "Valid value should be between 0 and %d.",
1966 VIRT_IRQCHIP_MAX_GUESTS);
1967 object_class_property_set_description(oc, "aia-guests", str);
1968 }
1969
1970 object_class_property_add(oc, "acpi", "OnOffAuto",
1971 virt_get_acpi, virt_set_acpi,
1972 NULL, NULL);
1973 object_class_property_set_description(oc, "acpi",
1974 "Enable ACPI");
1975
1976 object_class_property_add(oc, "iommu-sys", "OnOffAuto",
1977 virt_get_iommu_sys, virt_set_iommu_sys,
1978 NULL, NULL);
1979 object_class_property_set_description(oc, "iommu-sys",
1980 "Enable IOMMU platform device");
1981 }
1982
1983 static const TypeInfo virt_machine_typeinfo = {
1984 .name = MACHINE_TYPE_NAME("virt"),
1985 .parent = TYPE_MACHINE,
1986 .class_init = virt_machine_class_init,
1987 .instance_init = virt_machine_instance_init,
1988 .instance_size = sizeof(RISCVVirtState),
1989 .interfaces = (const InterfaceInfo[]) {
1990 { TYPE_HOTPLUG_HANDLER },
1991 { }
1992 },
1993 };
1994
virt_machine_init_register_types(void)1995 static void virt_machine_init_register_types(void)
1996 {
1997 type_register_static(&virt_machine_typeinfo);
1998 }
1999
2000 type_init(virt_machine_init_register_types)
2001