104331d0bSMichael Clark /* 204331d0bSMichael Clark * QEMU RISC-V VirtIO Board 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * RISC-V machine with 16550a UART and VirtIO MMIO 704331d0bSMichael Clark * 804331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 904331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 1004331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 1104331d0bSMichael Clark * 1204331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1304331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1404331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1504331d0bSMichael Clark * more details. 1604331d0bSMichael Clark * 1704331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1804331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1904331d0bSMichael Clark */ 2004331d0bSMichael Clark 2104331d0bSMichael Clark #include "qemu/osdep.h" 2204331d0bSMichael Clark #include "qemu/log.h" 2304331d0bSMichael Clark #include "qemu/error-report.h" 2404331d0bSMichael Clark #include "qapi/error.h" 2504331d0bSMichael Clark #include "hw/hw.h" 2604331d0bSMichael Clark #include "hw/boards.h" 2704331d0bSMichael Clark #include "hw/loader.h" 2804331d0bSMichael Clark #include "hw/sysbus.h" 2904331d0bSMichael Clark #include "hw/char/serial.h" 3004331d0bSMichael Clark #include "target/riscv/cpu.h" 3104331d0bSMichael Clark #include "hw/riscv/riscv_htif.h" 3204331d0bSMichael Clark #include "hw/riscv/riscv_hart.h" 3304331d0bSMichael Clark #include "hw/riscv/sifive_plic.h" 3404331d0bSMichael Clark #include "hw/riscv/sifive_clint.h" 3504331d0bSMichael Clark #include "hw/riscv/sifive_test.h" 3604331d0bSMichael Clark #include "hw/riscv/virt.h" 3704331d0bSMichael Clark #include "chardev/char.h" 3804331d0bSMichael Clark #include "sysemu/arch_init.h" 3904331d0bSMichael Clark #include "sysemu/device_tree.h" 4004331d0bSMichael Clark #include "exec/address-spaces.h" 4104331d0bSMichael Clark #include "elf.h" 4204331d0bSMichael Clark 4304331d0bSMichael Clark static const struct MemmapEntry { 4404331d0bSMichael Clark hwaddr base; 4504331d0bSMichael Clark hwaddr size; 4604331d0bSMichael Clark } virt_memmap[] = { 4704331d0bSMichael Clark [VIRT_DEBUG] = { 0x0, 0x100 }, 4804331d0bSMichael Clark [VIRT_MROM] = { 0x1000, 0x2000 }, 4904331d0bSMichael Clark [VIRT_TEST] = { 0x4000, 0x1000 }, 5004331d0bSMichael Clark [VIRT_CLINT] = { 0x2000000, 0x10000 }, 5104331d0bSMichael Clark [VIRT_PLIC] = { 0xc000000, 0x4000000 }, 5204331d0bSMichael Clark [VIRT_UART0] = { 0x10000000, 0x100 }, 5304331d0bSMichael Clark [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 5404331d0bSMichael Clark [VIRT_DRAM] = { 0x80000000, 0x0 }, 5504331d0bSMichael Clark }; 5604331d0bSMichael Clark 5704331d0bSMichael Clark static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) 5804331d0bSMichael Clark { 5904331d0bSMichael Clark int i; 6004331d0bSMichael Clark for (i = 0; i < (len >> 2); i++) { 6104331d0bSMichael Clark stl_phys(&address_space_memory, pa + (i << 2), rom[i]); 6204331d0bSMichael Clark } 6304331d0bSMichael Clark } 6404331d0bSMichael Clark 6504331d0bSMichael Clark static uint64_t load_kernel(const char *kernel_filename) 6604331d0bSMichael Clark { 6704331d0bSMichael Clark uint64_t kernel_entry, kernel_high; 6804331d0bSMichael Clark 69b7938980SMichael Clark if (load_elf(kernel_filename, NULL, NULL, 7004331d0bSMichael Clark &kernel_entry, NULL, &kernel_high, 71*89854803SMichael Clark 0, EM_RISCV, 1, 0) < 0) { 7204331d0bSMichael Clark error_report("qemu: could not load kernel '%s'", kernel_filename); 7304331d0bSMichael Clark exit(1); 7404331d0bSMichael Clark } 7504331d0bSMichael Clark return kernel_entry; 7604331d0bSMichael Clark } 7704331d0bSMichael Clark 7804331d0bSMichael Clark static hwaddr load_initrd(const char *filename, uint64_t mem_size, 7904331d0bSMichael Clark uint64_t kernel_entry, hwaddr *start) 8004331d0bSMichael Clark { 8104331d0bSMichael Clark int size; 8204331d0bSMichael Clark 8304331d0bSMichael Clark /* We want to put the initrd far enough into RAM that when the 8404331d0bSMichael Clark * kernel is uncompressed it will not clobber the initrd. However 8504331d0bSMichael Clark * on boards without much RAM we must ensure that we still leave 8604331d0bSMichael Clark * enough room for a decent sized initrd, and on boards with large 8704331d0bSMichael Clark * amounts of RAM we must avoid the initrd being so far up in RAM 8804331d0bSMichael Clark * that it is outside lowmem and inaccessible to the kernel. 8904331d0bSMichael Clark * So for boards with less than 256MB of RAM we put the initrd 9004331d0bSMichael Clark * halfway into RAM, and for boards with 256MB of RAM or more we put 9104331d0bSMichael Clark * the initrd at 128MB. 9204331d0bSMichael Clark */ 9304331d0bSMichael Clark *start = kernel_entry + MIN(mem_size / 2, 128 * 1024 * 1024); 9404331d0bSMichael Clark 9504331d0bSMichael Clark size = load_ramdisk(filename, *start, mem_size - *start); 9604331d0bSMichael Clark if (size == -1) { 9704331d0bSMichael Clark size = load_image_targphys(filename, *start, mem_size - *start); 9804331d0bSMichael Clark if (size == -1) { 9904331d0bSMichael Clark error_report("qemu: could not load ramdisk '%s'", filename); 10004331d0bSMichael Clark exit(1); 10104331d0bSMichael Clark } 10204331d0bSMichael Clark } 10304331d0bSMichael Clark return *start + size; 10404331d0bSMichael Clark } 10504331d0bSMichael Clark 10604331d0bSMichael Clark static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 10704331d0bSMichael Clark uint64_t mem_size, const char *cmdline) 10804331d0bSMichael Clark { 10904331d0bSMichael Clark void *fdt; 11004331d0bSMichael Clark int cpu; 11104331d0bSMichael Clark uint32_t *cells; 11204331d0bSMichael Clark char *nodename; 11304331d0bSMichael Clark uint32_t plic_phandle, phandle = 1; 11404331d0bSMichael Clark int i; 11504331d0bSMichael Clark 11604331d0bSMichael Clark fdt = s->fdt = create_device_tree(&s->fdt_size); 11704331d0bSMichael Clark if (!fdt) { 11804331d0bSMichael Clark error_report("create_device_tree() failed"); 11904331d0bSMichael Clark exit(1); 12004331d0bSMichael Clark } 12104331d0bSMichael Clark 12204331d0bSMichael Clark qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 12304331d0bSMichael Clark qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 12404331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 12504331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 12604331d0bSMichael Clark 12704331d0bSMichael Clark qemu_fdt_add_subnode(fdt, "/soc"); 12804331d0bSMichael Clark qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 12904331d0bSMichael Clark qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc"); 13004331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 13104331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 13204331d0bSMichael Clark 13304331d0bSMichael Clark nodename = g_strdup_printf("/memory@%lx", 13404331d0bSMichael Clark (long)memmap[VIRT_DRAM].base); 13504331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 13604331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 13704331d0bSMichael Clark memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, 13804331d0bSMichael Clark mem_size >> 32, mem_size); 13904331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 14004331d0bSMichael Clark g_free(nodename); 14104331d0bSMichael Clark 14204331d0bSMichael Clark qemu_fdt_add_subnode(fdt, "/cpus"); 1432a8756edSMichael Clark qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 1442a8756edSMichael Clark SIFIVE_CLINT_TIMEBASE_FREQ); 14504331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 14604331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 14704331d0bSMichael Clark 14804331d0bSMichael Clark for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 14904331d0bSMichael Clark int cpu_phandle = phandle++; 15004331d0bSMichael Clark nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 15104331d0bSMichael Clark char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 15204331d0bSMichael Clark char *isa = riscv_isa_string(&s->soc.harts[cpu]); 15304331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 1542a8756edSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1552a8756edSMichael Clark VIRT_CLOCK_FREQ); 15604331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 15704331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 15804331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 15904331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 16004331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 16104331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 16204331d0bSMichael Clark qemu_fdt_add_subnode(fdt, intc); 16304331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 16404331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); 16504331d0bSMichael Clark qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 16604331d0bSMichael Clark qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 16704331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 16804331d0bSMichael Clark g_free(isa); 16904331d0bSMichael Clark g_free(intc); 17004331d0bSMichael Clark g_free(nodename); 17104331d0bSMichael Clark } 17204331d0bSMichael Clark 17304331d0bSMichael Clark cells = g_new0(uint32_t, s->soc.num_harts * 4); 17404331d0bSMichael Clark for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 17504331d0bSMichael Clark nodename = 17604331d0bSMichael Clark g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 17704331d0bSMichael Clark uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 17804331d0bSMichael Clark cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 17904331d0bSMichael Clark cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 18004331d0bSMichael Clark cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 18104331d0bSMichael Clark cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 18204331d0bSMichael Clark g_free(nodename); 18304331d0bSMichael Clark } 18404331d0bSMichael Clark nodename = g_strdup_printf("/soc/clint@%lx", 18504331d0bSMichael Clark (long)memmap[VIRT_CLINT].base); 18604331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 18704331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 18804331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 18904331d0bSMichael Clark 0x0, memmap[VIRT_CLINT].base, 19004331d0bSMichael Clark 0x0, memmap[VIRT_CLINT].size); 19104331d0bSMichael Clark qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 19204331d0bSMichael Clark cells, s->soc.num_harts * sizeof(uint32_t) * 4); 19304331d0bSMichael Clark g_free(cells); 19404331d0bSMichael Clark g_free(nodename); 19504331d0bSMichael Clark 19604331d0bSMichael Clark plic_phandle = phandle++; 19704331d0bSMichael Clark cells = g_new0(uint32_t, s->soc.num_harts * 4); 19804331d0bSMichael Clark for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 19904331d0bSMichael Clark nodename = 20004331d0bSMichael Clark g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 20104331d0bSMichael Clark uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 20204331d0bSMichael Clark cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 20304331d0bSMichael Clark cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 20404331d0bSMichael Clark cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 20504331d0bSMichael Clark cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 20604331d0bSMichael Clark g_free(nodename); 20704331d0bSMichael Clark } 20804331d0bSMichael Clark nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 20904331d0bSMichael Clark (long)memmap[VIRT_PLIC].base); 21004331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 21104331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 21204331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 21304331d0bSMichael Clark qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 21404331d0bSMichael Clark qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 21504331d0bSMichael Clark cells, s->soc.num_harts * sizeof(uint32_t) * 4); 21604331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 21704331d0bSMichael Clark 0x0, memmap[VIRT_PLIC].base, 21804331d0bSMichael Clark 0x0, memmap[VIRT_PLIC].size); 21904331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 22004331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 22104331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); 22204331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); 22304331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); 22404331d0bSMichael Clark plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 22504331d0bSMichael Clark g_free(cells); 22604331d0bSMichael Clark g_free(nodename); 22704331d0bSMichael Clark 22804331d0bSMichael Clark for (i = 0; i < VIRTIO_COUNT; i++) { 22904331d0bSMichael Clark nodename = g_strdup_printf("/virtio_mmio@%lx", 23004331d0bSMichael Clark (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 23104331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 23204331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); 23304331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 23404331d0bSMichael Clark 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 23504331d0bSMichael Clark 0x0, memmap[VIRT_VIRTIO].size); 23604331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 23704331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i); 23804331d0bSMichael Clark g_free(nodename); 23904331d0bSMichael Clark } 24004331d0bSMichael Clark 24104331d0bSMichael Clark nodename = g_strdup_printf("/test@%lx", 24204331d0bSMichael Clark (long)memmap[VIRT_TEST].base); 24304331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 24404331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0"); 24504331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 24604331d0bSMichael Clark 0x0, memmap[VIRT_TEST].base, 24704331d0bSMichael Clark 0x0, memmap[VIRT_TEST].size); 24804331d0bSMichael Clark 24904331d0bSMichael Clark nodename = g_strdup_printf("/uart@%lx", 25004331d0bSMichael Clark (long)memmap[VIRT_UART0].base); 25104331d0bSMichael Clark qemu_fdt_add_subnode(fdt, nodename); 25204331d0bSMichael Clark qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 25304331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "reg", 25404331d0bSMichael Clark 0x0, memmap[VIRT_UART0].base, 25504331d0bSMichael Clark 0x0, memmap[VIRT_UART0].size); 25604331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); 25704331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 25804331d0bSMichael Clark qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ); 25904331d0bSMichael Clark 26004331d0bSMichael Clark qemu_fdt_add_subnode(fdt, "/chosen"); 26104331d0bSMichael Clark qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 26204331d0bSMichael Clark qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 26304331d0bSMichael Clark g_free(nodename); 26404331d0bSMichael Clark 26504331d0bSMichael Clark return fdt; 26604331d0bSMichael Clark } 26704331d0bSMichael Clark 26804331d0bSMichael Clark static void riscv_virt_board_init(MachineState *machine) 26904331d0bSMichael Clark { 27004331d0bSMichael Clark const struct MemmapEntry *memmap = virt_memmap; 27104331d0bSMichael Clark 27204331d0bSMichael Clark RISCVVirtState *s = g_new0(RISCVVirtState, 1); 27304331d0bSMichael Clark MemoryRegion *system_memory = get_system_memory(); 27404331d0bSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 27504331d0bSMichael Clark MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 27604331d0bSMichael Clark char *plic_hart_config; 27704331d0bSMichael Clark size_t plic_hart_config_len; 27804331d0bSMichael Clark int i; 27904331d0bSMichael Clark void *fdt; 28004331d0bSMichael Clark 28104331d0bSMichael Clark /* Initialize SOC */ 28204331d0bSMichael Clark object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 28304331d0bSMichael Clark object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 28404331d0bSMichael Clark &error_abort); 28504331d0bSMichael Clark object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type", 28604331d0bSMichael Clark &error_abort); 28704331d0bSMichael Clark object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 28804331d0bSMichael Clark &error_abort); 28904331d0bSMichael Clark object_property_set_bool(OBJECT(&s->soc), true, "realized", 29004331d0bSMichael Clark &error_abort); 29104331d0bSMichael Clark 29204331d0bSMichael Clark /* register system main memory (actual RAM) */ 29304331d0bSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 29404331d0bSMichael Clark machine->ram_size, &error_fatal); 29504331d0bSMichael Clark memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 29604331d0bSMichael Clark main_mem); 29704331d0bSMichael Clark 29804331d0bSMichael Clark /* create device tree */ 29904331d0bSMichael Clark fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 30004331d0bSMichael Clark 30104331d0bSMichael Clark /* boot rom */ 30204331d0bSMichael Clark memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", 30304331d0bSMichael Clark s->fdt_size + 0x2000, &error_fatal); 30404331d0bSMichael Clark memory_region_add_subregion(system_memory, 0x0, boot_rom); 30504331d0bSMichael Clark 30604331d0bSMichael Clark if (machine->kernel_filename) { 30704331d0bSMichael Clark uint64_t kernel_entry = load_kernel(machine->kernel_filename); 30804331d0bSMichael Clark 30904331d0bSMichael Clark if (machine->initrd_filename) { 31004331d0bSMichael Clark hwaddr start; 31104331d0bSMichael Clark hwaddr end = load_initrd(machine->initrd_filename, 31204331d0bSMichael Clark machine->ram_size, kernel_entry, 31304331d0bSMichael Clark &start); 31404331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/chosen", 31504331d0bSMichael Clark "linux,initrd-start", start); 31604331d0bSMichael Clark qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 31704331d0bSMichael Clark end); 31804331d0bSMichael Clark } 31904331d0bSMichael Clark } 32004331d0bSMichael Clark 32104331d0bSMichael Clark /* reset vector */ 32204331d0bSMichael Clark uint32_t reset_vec[8] = { 32304331d0bSMichael Clark 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 32404331d0bSMichael Clark 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 32504331d0bSMichael Clark 0xf1402573, /* csrr a0, mhartid */ 32604331d0bSMichael Clark #if defined(TARGET_RISCV32) 32704331d0bSMichael Clark 0x0182a283, /* lw t0, 24(t0) */ 32804331d0bSMichael Clark #elif defined(TARGET_RISCV64) 32904331d0bSMichael Clark 0x0182b283, /* ld t0, 24(t0) */ 33004331d0bSMichael Clark #endif 33104331d0bSMichael Clark 0x00028067, /* jr t0 */ 33204331d0bSMichael Clark 0x00000000, 33304331d0bSMichael Clark memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */ 33404331d0bSMichael Clark 0x00000000, 33504331d0bSMichael Clark /* dtb: */ 33604331d0bSMichael Clark }; 33704331d0bSMichael Clark 33804331d0bSMichael Clark /* copy in the reset vector */ 3396b01e327SMichael Clark copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)); 34004331d0bSMichael Clark 34104331d0bSMichael Clark /* copy in the device tree */ 34204331d0bSMichael Clark qemu_fdt_dumpdtb(s->fdt, s->fdt_size); 3436b01e327SMichael Clark cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), 34404331d0bSMichael Clark s->fdt, s->fdt_size); 34504331d0bSMichael Clark 34604331d0bSMichael Clark /* create PLIC hart topology configuration string */ 34704331d0bSMichael Clark plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus; 34804331d0bSMichael Clark plic_hart_config = g_malloc0(plic_hart_config_len); 34904331d0bSMichael Clark for (i = 0; i < smp_cpus; i++) { 35004331d0bSMichael Clark if (i != 0) { 35104331d0bSMichael Clark strncat(plic_hart_config, ",", plic_hart_config_len); 35204331d0bSMichael Clark } 35304331d0bSMichael Clark strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len); 35404331d0bSMichael Clark plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 35504331d0bSMichael Clark } 35604331d0bSMichael Clark 35704331d0bSMichael Clark /* MMIO */ 35804331d0bSMichael Clark s->plic = sifive_plic_create(memmap[VIRT_PLIC].base, 35904331d0bSMichael Clark plic_hart_config, 36004331d0bSMichael Clark VIRT_PLIC_NUM_SOURCES, 36104331d0bSMichael Clark VIRT_PLIC_NUM_PRIORITIES, 36204331d0bSMichael Clark VIRT_PLIC_PRIORITY_BASE, 36304331d0bSMichael Clark VIRT_PLIC_PENDING_BASE, 36404331d0bSMichael Clark VIRT_PLIC_ENABLE_BASE, 36504331d0bSMichael Clark VIRT_PLIC_ENABLE_STRIDE, 36604331d0bSMichael Clark VIRT_PLIC_CONTEXT_BASE, 36704331d0bSMichael Clark VIRT_PLIC_CONTEXT_STRIDE, 36804331d0bSMichael Clark memmap[VIRT_PLIC].size); 36904331d0bSMichael Clark sifive_clint_create(memmap[VIRT_CLINT].base, 37004331d0bSMichael Clark memmap[VIRT_CLINT].size, smp_cpus, 37104331d0bSMichael Clark SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 37204331d0bSMichael Clark sifive_test_create(memmap[VIRT_TEST].base); 37304331d0bSMichael Clark 37404331d0bSMichael Clark for (i = 0; i < VIRTIO_COUNT; i++) { 37504331d0bSMichael Clark sysbus_create_simple("virtio-mmio", 37604331d0bSMichael Clark memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 37704331d0bSMichael Clark SIFIVE_PLIC(s->plic)->irqs[VIRTIO_IRQ + i]); 37804331d0bSMichael Clark } 37904331d0bSMichael Clark 38004331d0bSMichael Clark serial_mm_init(system_memory, memmap[VIRT_UART0].base, 38104331d0bSMichael Clark 0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193, 3829bca0edbSPeter Maydell serial_hd(0), DEVICE_LITTLE_ENDIAN); 38304331d0bSMichael Clark } 38404331d0bSMichael Clark 38504331d0bSMichael Clark static void riscv_virt_board_machine_init(MachineClass *mc) 38604331d0bSMichael Clark { 38777ff5bbaSMichael Clark mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; 38804331d0bSMichael Clark mc->init = riscv_virt_board_init; 38904331d0bSMichael Clark mc->max_cpus = 8; /* hardcoded limit in BBL */ 39004331d0bSMichael Clark } 39104331d0bSMichael Clark 39204331d0bSMichael Clark DEFINE_MACHINE("virt", riscv_virt_board_machine_init) 393