Searched refs:nfe (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/crypto/hisilicon/zip/ |
| H A D | zip_main.c | 681 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hisi_zip_hw_error_enable()
696 writel(dev_err->nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
709 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hisi_zip_hw_error_disable()
1186 u32 nfe_mask = qm->err_info.dev_err.nfe; in hisi_zip_disable_error_report()
1193 u32 nfe_mask = qm->err_info.dev_err.nfe; in hisi_zip_enable_error_report()
1279 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hisi_zip_disable_axi_error()
1293 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hisi_zip_enable_axi_error()
1312 qm_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1322 dev_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
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| /linux/drivers/crypto/hisilicon/sec2/ |
| H A D | sec_main.c | 744 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in sec_hw_error_enable()
758 writel(dev_err->nfe, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
1121 u32 nfe_mask = qm->err_info.dev_err.nfe; in sec_disable_error_report()
1128 u32 nfe_mask = qm->err_info.dev_err.nfe; in sec_enable_error_report()
1181 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in sec_disable_axi_error()
1193 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in sec_enable_axi_error()
1212 qm_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1221 dev_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
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| /linux/drivers/crypto/hisilicon/hpre/ |
| H A D | hpre_main.c | 817 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hpre_hw_error_disable()
828 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hpre_hw_error_enable()
835 writel(dev_err->nfe, qm->io_base + HPRE_RAS_NFE_ENB); in hpre_hw_error_enable()
1397 u32 nfe_mask = qm->err_info.dev_err.nfe; in hpre_disable_error_report()
1404 u32 nfe_mask = qm->err_info.dev_err.nfe; in hpre_enable_error_report()
1459 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hpre_disable_axi_error()
1473 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; in hpre_enable_axi_error()
1492 qm_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1501 dev_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
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| /linux/include/linux/ |
| H A D | hisi_acc_qm.h | 253 u32 nfe; member
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| /linux/drivers/crypto/hisilicon/ |
| H A D | qm.c | 1476 qm->error_mask = qm_err->nfe | qm_err->ce | qm_err->fe; in qm_hw_error_cfg()
1483 writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_cfg()
1586 writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_handle_v2()
1592 writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_handle_v2()
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