1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define CAP_FILE_PERMISSION 0444 18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 24 #define HZIP_FSM_MAX_CNT 0x301008 25 26 #define HZIP_PORT_ARCA_CHE_0 0x301040 27 #define HZIP_PORT_ARCA_CHE_1 0x301044 28 #define HZIP_PORT_AWCA_CHE_0 0x301060 29 #define HZIP_PORT_AWCA_CHE_1 0x301064 30 #define HZIP_CACHE_ALL_EN 0xffffffff 31 32 #define HZIP_BD_RUSER_32_63 0x301110 33 #define HZIP_SGL_RUSER_32_63 0x30111c 34 #define HZIP_DATA_RUSER_32_63 0x301128 35 #define HZIP_DATA_WUSER_32_63 0x301134 36 #define HZIP_BD_WUSER_32_63 0x301140 37 38 #define HZIP_QM_IDEL_STATUS 0x3040e4 39 40 #define HZIP_CORE_DFX_BASE 0x301000 41 #define HZIP_CORE_DFX_DECOMP_BASE 0x304000 42 #define HZIP_CORE_DFX_COMP_0 0x302000 43 #define HZIP_CORE_DFX_COMP_1 0x303000 44 #define HZIP_CORE_DFX_DECOMP_0 0x304000 45 #define HZIP_CORE_DFX_DECOMP_1 0x305000 46 #define HZIP_CORE_DFX_DECOMP_2 0x306000 47 #define HZIP_CORE_DFX_DECOMP_3 0x307000 48 #define HZIP_CORE_DFX_DECOMP_4 0x308000 49 #define HZIP_CORE_DFX_DECOMP_5 0x309000 50 #define HZIP_CORE_REGS_BASE_LEN 0xB0 51 #define HZIP_CORE_REGS_DFX_LEN 0x28 52 #define HZIP_CORE_ADDR_INTRVL 0x1000 53 54 #define HZIP_CORE_INT_SOURCE 0x3010A0 55 #define HZIP_CORE_INT_MASK_REG 0x3010A4 56 #define HZIP_CORE_INT_SET 0x3010A8 57 #define HZIP_CORE_INT_STATUS 0x3010AC 58 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 59 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 60 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 61 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 62 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 63 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 64 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 65 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 66 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 67 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 68 #define HZIP_SQE_SIZE 128 69 #define HZIP_PF_DEF_Q_NUM 64 70 #define HZIP_PF_DEF_Q_BASE 0 71 #define HZIP_CTX_Q_NUM_DEF 2 72 73 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 74 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 75 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 76 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 77 #define HZIP_WR_PORT BIT(11) 78 79 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 80 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 81 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 82 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 83 84 #define HZIP_BUF_SIZE 22 85 #define HZIP_SQE_MASK_OFFSET 64 86 #define HZIP_SQE_MASK_LEN 48 87 88 #define HZIP_CNT_CLR_CE_EN BIT(0) 89 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 90 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 91 HZIP_RO_CNT_CLR_CE_EN) 92 93 #define HZIP_PREFETCH_CFG 0x3011B0 94 #define HZIP_SVA_TRANS 0x3011C4 95 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 96 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 97 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 98 #define HZIP_SHAPER_RATE_COMPRESS 750 99 #define HZIP_SHAPER_RATE_DECOMPRESS 140 100 #define HZIP_DELAY_1_US 1 101 #define HZIP_POLL_TIMEOUT_US 1000 102 103 /* clock gating */ 104 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 105 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 106 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 107 #define HZIP_CORE_GATED_OOO_EN BIT(29) 108 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 109 HZIP_CORE_GATED_OOO_EN) 110 111 /* zip comp high performance */ 112 #define HZIP_HIGH_PERF_OFFSET 0x301208 113 114 enum { 115 HZIP_HIGH_COMP_RATE, 116 HZIP_HIGH_COMP_PERF, 117 }; 118 119 static const char hisi_zip_name[] = "hisi_zip"; 120 static struct dentry *hzip_debugfs_root; 121 122 struct hisi_zip_hw_error { 123 u32 int_msk; 124 const char *msg; 125 }; 126 127 struct zip_dfx_item { 128 const char *name; 129 u32 offset; 130 }; 131 132 static const struct qm_dev_alg zip_dev_algs[] = { { 133 .alg_msk = HZIP_ALG_ZLIB_BIT, 134 .alg = "zlib\n", 135 }, { 136 .alg_msk = HZIP_ALG_GZIP_BIT, 137 .alg = "gzip\n", 138 }, { 139 .alg_msk = HZIP_ALG_DEFLATE_BIT, 140 .alg = "deflate\n", 141 }, { 142 .alg_msk = HZIP_ALG_LZ77_BIT, 143 .alg = "lz77_zstd\n", 144 }, 145 }; 146 147 static struct hisi_qm_list zip_devices = { 148 .register_to_crypto = hisi_zip_register_to_crypto, 149 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 150 }; 151 152 static struct zip_dfx_item zip_dfx_files[] = { 153 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 154 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 155 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 156 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 157 }; 158 159 static const struct hisi_zip_hw_error zip_hw_error[] = { 160 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 161 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 162 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 163 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 164 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 165 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 166 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 167 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 168 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 169 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 170 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 171 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 172 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 173 { /* sentinel */ } 174 }; 175 176 enum ctrl_debug_file_index { 177 HZIP_CLEAR_ENABLE, 178 HZIP_DEBUG_FILE_NUM, 179 }; 180 181 static const char * const ctrl_debug_file_name[] = { 182 [HZIP_CLEAR_ENABLE] = "clear_enable", 183 }; 184 185 struct ctrl_debug_file { 186 enum ctrl_debug_file_index index; 187 spinlock_t lock; 188 struct hisi_zip_ctrl *ctrl; 189 }; 190 191 /* 192 * One ZIP controller has one PF and multiple VFs, some global configurations 193 * which PF has need this structure. 194 * 195 * Just relevant for PF. 196 */ 197 struct hisi_zip_ctrl { 198 struct hisi_zip *hisi_zip; 199 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 200 }; 201 202 enum zip_cap_type { 203 ZIP_QM_NFE_MASK_CAP = 0x0, 204 ZIP_QM_RESET_MASK_CAP, 205 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 206 ZIP_QM_CE_MASK_CAP, 207 ZIP_NFE_MASK_CAP, 208 ZIP_RESET_MASK_CAP, 209 ZIP_OOO_SHUTDOWN_MASK_CAP, 210 ZIP_CE_MASK_CAP, 211 ZIP_CLUSTER_NUM_CAP, 212 ZIP_CORE_TYPE_NUM_CAP, 213 ZIP_CORE_NUM_CAP, 214 ZIP_CLUSTER_COMP_NUM_CAP, 215 ZIP_CLUSTER_DECOMP_NUM_CAP, 216 ZIP_DECOMP_ENABLE_BITMAP, 217 ZIP_COMP_ENABLE_BITMAP, 218 ZIP_DRV_ALG_BITMAP, 219 ZIP_DEV_ALG_BITMAP, 220 ZIP_CORE1_ALG_BITMAP, 221 ZIP_CORE2_ALG_BITMAP, 222 ZIP_CORE3_ALG_BITMAP, 223 ZIP_CORE4_ALG_BITMAP, 224 ZIP_CORE5_ALG_BITMAP, 225 ZIP_CAP_MAX 226 }; 227 228 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 229 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 230 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 231 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 232 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 233 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 234 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 235 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 236 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 237 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 238 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 239 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 240 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 241 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 242 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 243 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 244 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30}, 245 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F}, 246 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 247 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 248 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 249 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 250 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 251 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 252 }; 253 254 static const struct hisi_qm_cap_query_info zip_cap_query_info[] = { 255 {QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C57, 0x7C77}, 256 {QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC57, 0x6C77}, 257 {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8}, 258 {ZIP_RAS_NFE_TYPE, "ZIP_RAS_NFE_TYPE ", 0x3130, 0x0, 0x7FE, 0x1FFE}, 259 {ZIP_RAS_NFE_RESET, "ZIP_RAS_NFE_RESET ", 0x3134, 0x0, 0x7FE, 0x7FE}, 260 {ZIP_RAS_CE_TYPE, "ZIP_RAS_CE_TYPE ", 0x3138, 0x0, 0x1, 0x1}, 261 {ZIP_CORE_INFO, "ZIP_CORE_INFO ", 0x313C, 0x12080206, 0x12080206, 0x12050203}, 262 {ZIP_CORE_EN, "ZIP_CORE_EN ", 0x3140, 0xFC0003, 0xFC0003, 0x1C0003}, 263 {ZIP_DRV_ALG_BITMAP_TB, "ZIP_DRV_ALG_BITMAP ", 0x3144, 0x0, 0x0, 0x30}, 264 {ZIP_ALG_BITMAP, "ZIP_ALG_BITMAP ", 0x3148, 0xF, 0xF, 0x3F}, 265 {ZIP_CORE1_BITMAP, "ZIP_CORE1_BITMAP ", 0x314C, 0x5, 0x5, 0xD5}, 266 {ZIP_CORE2_BITMAP, "ZIP_CORE2_BITMAP ", 0x3150, 0x5, 0x5, 0xD5}, 267 {ZIP_CORE3_BITMAP, "ZIP_CORE3_BITMAP ", 0x3154, 0xA, 0xA, 0x2A}, 268 {ZIP_CORE4_BITMAP, "ZIP_CORE4_BITMAP ", 0x3158, 0xA, 0xA, 0x2A}, 269 {ZIP_CORE5_BITMAP, "ZIP_CORE5_BITMAP ", 0x315C, 0xA, 0xA, 0x2A}, 270 }; 271 272 static const struct debugfs_reg32 hzip_dfx_regs[] = { 273 {"HZIP_GET_BD_NUM ", 0x00}, 274 {"HZIP_GET_RIGHT_BD ", 0x04}, 275 {"HZIP_GET_ERROR_BD ", 0x08}, 276 {"HZIP_DONE_BD_NUM ", 0x0c}, 277 {"HZIP_WORK_CYCLE ", 0x10}, 278 {"HZIP_IDLE_CYCLE ", 0x18}, 279 {"HZIP_MAX_DELAY ", 0x20}, 280 {"HZIP_MIN_DELAY ", 0x24}, 281 {"HZIP_AVG_DELAY ", 0x28}, 282 {"HZIP_MEM_VISIBLE_DATA ", 0x30}, 283 {"HZIP_MEM_VISIBLE_ADDR ", 0x34}, 284 {"HZIP_CONSUMED_BYTE ", 0x38}, 285 {"HZIP_PRODUCED_BYTE ", 0x40}, 286 {"HZIP_COMP_INF ", 0x70}, 287 {"HZIP_PRE_OUT ", 0x78}, 288 {"HZIP_BD_RD ", 0x7c}, 289 {"HZIP_BD_WR ", 0x80}, 290 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84}, 291 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88}, 292 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8c}, 293 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94}, 294 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9c}, 295 }; 296 297 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 298 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 299 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 300 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 301 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 302 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 303 }; 304 305 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 306 {"HZIP_GET_BD_NUM ", 0x00}, 307 {"HZIP_GET_RIGHT_BD ", 0x04}, 308 {"HZIP_GET_ERROR_BD ", 0x08}, 309 {"HZIP_DONE_BD_NUM ", 0x0c}, 310 {"HZIP_MAX_DELAY ", 0x20}, 311 }; 312 313 /* define the ZIP's dfx regs region and region length */ 314 static struct dfx_diff_registers hzip_diff_regs[] = { 315 { 316 .reg_offset = HZIP_CORE_DFX_BASE, 317 .reg_len = HZIP_CORE_REGS_BASE_LEN, 318 }, { 319 .reg_offset = HZIP_CORE_DFX_COMP_0, 320 .reg_len = HZIP_CORE_REGS_DFX_LEN, 321 }, { 322 .reg_offset = HZIP_CORE_DFX_COMP_1, 323 .reg_len = HZIP_CORE_REGS_DFX_LEN, 324 }, { 325 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 326 .reg_len = HZIP_CORE_REGS_DFX_LEN, 327 }, { 328 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 329 .reg_len = HZIP_CORE_REGS_DFX_LEN, 330 }, { 331 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 332 .reg_len = HZIP_CORE_REGS_DFX_LEN, 333 }, { 334 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 335 .reg_len = HZIP_CORE_REGS_DFX_LEN, 336 }, { 337 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 338 .reg_len = HZIP_CORE_REGS_DFX_LEN, 339 }, { 340 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 341 .reg_len = HZIP_CORE_REGS_DFX_LEN, 342 }, 343 }; 344 345 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 346 { 347 struct hisi_qm *qm = s->private; 348 349 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 350 ARRAY_SIZE(hzip_diff_regs)); 351 352 return 0; 353 } 354 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 355 356 static int perf_mode_set(const char *val, const struct kernel_param *kp) 357 { 358 int ret; 359 u32 n; 360 361 if (!val) 362 return -EINVAL; 363 364 ret = kstrtou32(val, 10, &n); 365 if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && 366 n != HZIP_HIGH_COMP_RATE)) 367 return -EINVAL; 368 369 return param_set_int(val, kp); 370 } 371 372 static const struct kernel_param_ops zip_com_perf_ops = { 373 .set = perf_mode_set, 374 .get = param_get_int, 375 }; 376 377 /* 378 * perf_mode = 0 means enable high compression rate mode, 379 * perf_mode = 1 means enable high compression performance mode. 380 * These two modes only apply to the compression direction. 381 */ 382 static u32 perf_mode = HZIP_HIGH_COMP_RATE; 383 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); 384 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); 385 386 static const struct kernel_param_ops zip_uacce_mode_ops = { 387 .set = uacce_mode_set, 388 .get = param_get_int, 389 }; 390 391 /* 392 * uacce_mode = 0 means zip only register to crypto, 393 * uacce_mode = 1 means zip both register to crypto and uacce. 394 */ 395 static u32 uacce_mode = UACCE_MODE_NOUACCE; 396 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 397 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 398 399 static bool pf_q_num_flag; 400 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 401 { 402 pf_q_num_flag = true; 403 404 return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 405 } 406 407 static const struct kernel_param_ops pf_q_num_ops = { 408 .set = pf_q_num_set, 409 .get = param_get_int, 410 }; 411 412 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 413 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 414 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 415 416 static const struct kernel_param_ops vfs_num_ops = { 417 .set = vfs_num_set, 418 .get = param_get_int, 419 }; 420 421 static u32 vfs_num; 422 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 423 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 424 425 static const struct pci_device_id hisi_zip_dev_ids[] = { 426 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 427 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 428 { 0, } 429 }; 430 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 431 432 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 433 { 434 if (node == NUMA_NO_NODE) 435 node = cpu_to_node(raw_smp_processor_id()); 436 437 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 438 } 439 440 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 441 { 442 u32 cap_val; 443 444 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val; 445 if ((alg & cap_val) == alg) 446 return true; 447 448 return false; 449 } 450 451 static int hisi_zip_set_high_perf(struct hisi_qm *qm) 452 { 453 u32 val; 454 int ret; 455 456 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); 457 if (perf_mode == HZIP_HIGH_COMP_PERF) 458 val |= HZIP_HIGH_COMP_PERF; 459 else 460 val &= ~HZIP_HIGH_COMP_PERF; 461 462 /* Set perf mode */ 463 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); 464 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, 465 val, val == perf_mode, HZIP_DELAY_1_US, 466 HZIP_POLL_TIMEOUT_US); 467 if (ret) 468 pci_err(qm->pdev, "failed to set perf mode\n"); 469 470 return ret; 471 } 472 473 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 474 { 475 u32 val; 476 int ret; 477 478 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 479 return; 480 481 /* Enable prefetch */ 482 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 483 val &= HZIP_PREFETCH_ENABLE; 484 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 485 486 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 487 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 488 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 489 if (ret) 490 pci_err(qm->pdev, "failed to open sva prefetch\n"); 491 } 492 493 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 494 { 495 u32 val; 496 int ret; 497 498 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 499 return; 500 501 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 502 val |= HZIP_SVA_PREFETCH_DISABLE; 503 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 504 505 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 506 val, !(val & HZIP_SVA_DISABLE_READY), 507 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 508 if (ret) 509 pci_err(qm->pdev, "failed to close sva prefetch\n"); 510 } 511 512 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 513 { 514 u32 val; 515 516 if (qm->ver < QM_HW_V3) 517 return; 518 519 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 520 val |= HZIP_CLOCK_GATED_EN; 521 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 522 523 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 524 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 525 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 526 } 527 528 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 529 { 530 void __iomem *base = qm->io_base; 531 u32 dcomp_bm, comp_bm; 532 u32 zip_core_en; 533 534 /* qm user domain */ 535 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 536 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 537 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 538 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 539 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 540 541 /* qm cache */ 542 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 543 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 544 545 /* disable FLR triggered by BME(bus master enable) */ 546 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 547 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 548 549 /* cache */ 550 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 551 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 552 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 553 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 554 555 /* user domain configurations */ 556 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 557 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 558 559 if (qm->use_sva && qm->ver == QM_HW_V2) { 560 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 561 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 562 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 563 } else { 564 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 565 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 566 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 567 } 568 569 /* let's open all compression/decompression cores */ 570 571 zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val; 572 dcomp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].shift) & 573 zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].mask; 574 comp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].shift) & 575 zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].mask; 576 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 577 578 /* enable sqc,cqc writeback */ 579 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 580 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 581 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 582 583 hisi_zip_enable_clock_gate(qm); 584 585 return hisi_dae_set_user_domain(qm); 586 } 587 588 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 589 { 590 u32 val1, val2; 591 592 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 593 if (enable) { 594 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 595 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 596 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 597 } else { 598 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 599 val2 = 0x0; 600 } 601 602 if (qm->ver > QM_HW_V2) 603 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 604 605 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 606 } 607 608 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 609 { 610 u32 nfe, ce; 611 612 if (qm->ver == QM_HW_V1) { 613 writel(HZIP_CORE_INT_MASK_ALL, 614 qm->io_base + HZIP_CORE_INT_MASK_REG); 615 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 616 return; 617 } 618 619 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 620 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 621 622 /* clear ZIP hw error source if having */ 623 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 624 625 /* configure error type */ 626 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 627 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 628 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 629 630 hisi_zip_master_ooo_ctrl(qm, true); 631 632 /* enable ZIP hw error interrupts */ 633 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 634 635 hisi_dae_hw_error_enable(qm); 636 } 637 638 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 639 { 640 u32 nfe, ce; 641 642 /* disable ZIP hw error interrupts */ 643 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 644 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 645 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 646 647 hisi_zip_master_ooo_ctrl(qm, false); 648 649 hisi_dae_hw_error_disable(qm); 650 } 651 652 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 653 { 654 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 655 656 return &hisi_zip->qm; 657 } 658 659 static u32 clear_enable_read(struct hisi_qm *qm) 660 { 661 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 662 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 663 } 664 665 static int clear_enable_write(struct hisi_qm *qm, u32 val) 666 { 667 u32 tmp; 668 669 if (val != 1 && val != 0) 670 return -EINVAL; 671 672 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 673 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 674 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 675 676 return 0; 677 } 678 679 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 680 size_t count, loff_t *pos) 681 { 682 struct ctrl_debug_file *file = filp->private_data; 683 struct hisi_qm *qm = file_to_qm(file); 684 char tbuf[HZIP_BUF_SIZE]; 685 u32 val; 686 int ret; 687 688 ret = hisi_qm_get_dfx_access(qm); 689 if (ret) 690 return ret; 691 692 spin_lock_irq(&file->lock); 693 switch (file->index) { 694 case HZIP_CLEAR_ENABLE: 695 val = clear_enable_read(qm); 696 break; 697 default: 698 goto err_input; 699 } 700 spin_unlock_irq(&file->lock); 701 702 hisi_qm_put_dfx_access(qm); 703 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 704 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 705 706 err_input: 707 spin_unlock_irq(&file->lock); 708 hisi_qm_put_dfx_access(qm); 709 return -EINVAL; 710 } 711 712 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 713 const char __user *buf, 714 size_t count, loff_t *pos) 715 { 716 struct ctrl_debug_file *file = filp->private_data; 717 struct hisi_qm *qm = file_to_qm(file); 718 char tbuf[HZIP_BUF_SIZE]; 719 unsigned long val; 720 int len, ret; 721 722 if (*pos != 0) 723 return 0; 724 725 if (count >= HZIP_BUF_SIZE) 726 return -ENOSPC; 727 728 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 729 if (len < 0) 730 return len; 731 732 tbuf[len] = '\0'; 733 ret = kstrtoul(tbuf, 0, &val); 734 if (ret) 735 return ret; 736 737 ret = hisi_qm_get_dfx_access(qm); 738 if (ret) 739 return ret; 740 741 spin_lock_irq(&file->lock); 742 switch (file->index) { 743 case HZIP_CLEAR_ENABLE: 744 ret = clear_enable_write(qm, val); 745 if (ret) 746 goto err_input; 747 break; 748 default: 749 ret = -EINVAL; 750 goto err_input; 751 } 752 753 ret = count; 754 755 err_input: 756 spin_unlock_irq(&file->lock); 757 hisi_qm_put_dfx_access(qm); 758 return ret; 759 } 760 761 static const struct file_operations ctrl_debug_fops = { 762 .owner = THIS_MODULE, 763 .open = simple_open, 764 .read = hisi_zip_ctrl_debug_read, 765 .write = hisi_zip_ctrl_debug_write, 766 }; 767 768 static int zip_debugfs_atomic64_set(void *data, u64 val) 769 { 770 if (val) 771 return -EINVAL; 772 773 atomic64_set((atomic64_t *)data, 0); 774 775 return 0; 776 } 777 778 static int zip_debugfs_atomic64_get(void *data, u64 *val) 779 { 780 *val = atomic64_read((atomic64_t *)data); 781 782 return 0; 783 } 784 785 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 786 zip_debugfs_atomic64_set, "%llu\n"); 787 788 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 789 { 790 hisi_qm_regs_dump(s, s->private); 791 792 return 0; 793 } 794 795 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 796 797 static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num) 798 { 799 u8 zip_comp_core_num; 800 u32 zip_core_info; 801 802 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 803 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 804 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 805 806 if (core_num < zip_comp_core_num) 807 return qm->io_base + HZIP_CORE_DFX_BASE + 808 (core_num + 1) * HZIP_CORE_ADDR_INTRVL; 809 810 return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE + 811 (core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL; 812 } 813 814 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 815 { 816 u32 zip_core_num, zip_comp_core_num; 817 struct device *dev = &qm->pdev->dev; 818 struct debugfs_regset32 *regset; 819 u32 zip_core_info; 820 struct dentry *tmp_d; 821 char buf[HZIP_BUF_SIZE]; 822 int i; 823 824 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 825 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 826 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 827 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 828 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 829 830 for (i = 0; i < zip_core_num; i++) { 831 if (i < zip_comp_core_num) 832 scnprintf(buf, sizeof(buf), "comp_core%d", i); 833 else 834 scnprintf(buf, sizeof(buf), "decomp_core%d", 835 i - zip_comp_core_num); 836 837 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 838 if (!regset) 839 return -ENOENT; 840 841 regset->regs = hzip_dfx_regs; 842 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 843 regset->base = get_zip_core_addr(qm, i); 844 regset->dev = dev; 845 846 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 847 debugfs_create_file("regs", 0444, tmp_d, regset, 848 &hisi_zip_regs_fops); 849 } 850 851 return 0; 852 } 853 854 static int zip_cap_regs_show(struct seq_file *s, void *unused) 855 { 856 struct hisi_qm *qm = s->private; 857 u32 i, size; 858 859 size = qm->cap_tables.qm_cap_size; 860 for (i = 0; i < size; i++) 861 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name, 862 qm->cap_tables.qm_cap_table[i].cap_val); 863 864 size = qm->cap_tables.dev_cap_size; 865 for (i = 0; i < size; i++) 866 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name, 867 qm->cap_tables.dev_cap_table[i].cap_val); 868 869 return 0; 870 } 871 872 DEFINE_SHOW_ATTRIBUTE(zip_cap_regs); 873 874 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 875 { 876 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 877 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 878 struct hisi_zip_dfx *dfx = &zip->dfx; 879 struct dentry *tmp_dir; 880 void *data; 881 int i; 882 883 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 884 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 885 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 886 debugfs_create_file(zip_dfx_files[i].name, 887 0644, tmp_dir, data, 888 &zip_atomic64_ops); 889 } 890 891 if (qm->fun_type == QM_HW_PF && hzip_regs) 892 debugfs_create_file("diff_regs", 0444, tmp_dir, 893 qm, &hzip_diff_regs_fops); 894 895 debugfs_create_file("cap_regs", CAP_FILE_PERMISSION, 896 qm->debug.debug_root, qm, &zip_cap_regs_fops); 897 } 898 899 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 900 { 901 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 902 int i; 903 904 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 905 spin_lock_init(&zip->ctrl->files[i].lock); 906 zip->ctrl->files[i].ctrl = zip->ctrl; 907 zip->ctrl->files[i].index = i; 908 909 debugfs_create_file(ctrl_debug_file_name[i], 0600, 910 qm->debug.debug_root, 911 zip->ctrl->files + i, 912 &ctrl_debug_fops); 913 } 914 915 return hisi_zip_core_debug_init(qm); 916 } 917 918 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 919 { 920 struct device *dev = &qm->pdev->dev; 921 int ret; 922 923 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 924 if (ret) { 925 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 926 return ret; 927 } 928 929 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 930 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 931 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 932 hzip_debugfs_root); 933 934 hisi_qm_debug_init(qm); 935 936 if (qm->fun_type == QM_HW_PF) { 937 ret = hisi_zip_ctrl_debug_init(qm); 938 if (ret) 939 goto debugfs_remove; 940 } 941 942 hisi_zip_dfx_debug_init(qm); 943 944 return 0; 945 946 debugfs_remove: 947 debugfs_remove_recursive(qm->debug.debug_root); 948 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 949 return ret; 950 } 951 952 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 953 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 954 { 955 u32 zip_core_info; 956 u8 zip_core_num; 957 int i, j; 958 959 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 960 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 961 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 962 963 /* enable register read_clear bit */ 964 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 965 for (i = 0; i < zip_core_num; i++) 966 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 967 readl(get_zip_core_addr(qm, i) + 968 hzip_dfx_regs[j].offset); 969 970 /* disable register read_clear bit */ 971 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 972 973 hisi_qm_debug_regs_clear(qm); 974 } 975 976 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 977 { 978 debugfs_remove_recursive(qm->debug.debug_root); 979 980 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 981 982 if (qm->fun_type == QM_HW_PF) { 983 hisi_zip_debug_regs_clear(qm); 984 qm->debug.curr_qm_qp_num = 0; 985 } 986 } 987 988 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 989 { 990 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 991 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 992 struct qm_debug *debug = &qm->debug; 993 void __iomem *io_base; 994 u32 zip_core_info; 995 u32 zip_core_num; 996 int i, j, idx; 997 998 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 999 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1000 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1001 1002 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 1003 sizeof(unsigned int), GFP_KERNEL); 1004 if (!debug->last_words) 1005 return -ENOMEM; 1006 1007 for (i = 0; i < com_dfx_regs_num; i++) { 1008 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 1009 debug->last_words[i] = readl_relaxed(io_base); 1010 } 1011 1012 for (i = 0; i < zip_core_num; i++) { 1013 io_base = get_zip_core_addr(qm, i); 1014 for (j = 0; j < core_dfx_regs_num; j++) { 1015 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1016 debug->last_words[idx] = readl_relaxed( 1017 io_base + hzip_dump_dfx_regs[j].offset); 1018 } 1019 } 1020 1021 return 0; 1022 } 1023 1024 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 1025 { 1026 struct qm_debug *debug = &qm->debug; 1027 1028 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1029 return; 1030 1031 kfree(debug->last_words); 1032 debug->last_words = NULL; 1033 } 1034 1035 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 1036 { 1037 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1038 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1039 u32 zip_core_num, zip_comp_core_num; 1040 struct qm_debug *debug = &qm->debug; 1041 char buf[HZIP_BUF_SIZE]; 1042 u32 zip_core_info; 1043 void __iomem *base; 1044 int i, j, idx; 1045 u32 val; 1046 1047 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1048 return; 1049 1050 for (i = 0; i < com_dfx_regs_num; i++) { 1051 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 1052 if (debug->last_words[i] != val) 1053 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 1054 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 1055 } 1056 1057 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1058 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1059 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1060 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 1061 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 1062 1063 for (i = 0; i < zip_core_num; i++) { 1064 if (i < zip_comp_core_num) 1065 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 1066 else 1067 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 1068 i - zip_comp_core_num); 1069 base = get_zip_core_addr(qm, i); 1070 1071 pci_info(qm->pdev, "==>%s:\n", buf); 1072 /* dump last word for dfx regs during control resetting */ 1073 for (j = 0; j < core_dfx_regs_num; j++) { 1074 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1075 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 1076 if (debug->last_words[idx] != val) 1077 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 1078 hzip_dump_dfx_regs[j].name, 1079 debug->last_words[idx], val); 1080 } 1081 } 1082 } 1083 1084 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1085 { 1086 const struct hisi_zip_hw_error *err = zip_hw_error; 1087 struct device *dev = &qm->pdev->dev; 1088 u32 err_val; 1089 1090 while (err->msg) { 1091 if (err->int_msk & err_sts) { 1092 dev_err(dev, "%s [error status=0x%x] found\n", 1093 err->msg, err->int_msk); 1094 1095 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1096 err_val = readl(qm->io_base + 1097 HZIP_CORE_SRAM_ECC_ERR_INFO); 1098 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1099 ((err_val >> 1100 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1101 } 1102 } 1103 err++; 1104 } 1105 } 1106 1107 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1108 { 1109 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1110 } 1111 1112 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1113 { 1114 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1115 } 1116 1117 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type) 1118 { 1119 u32 nfe_mask; 1120 1121 nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1122 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1123 } 1124 1125 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1126 { 1127 u32 val; 1128 1129 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1130 1131 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1132 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1133 1134 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1135 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1136 1137 hisi_dae_open_axi_master_ooo(qm); 1138 } 1139 1140 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1141 { 1142 u32 nfe_enb; 1143 1144 /* Disable ECC Mbit error report. */ 1145 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1146 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1147 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1148 1149 /* Inject zip ECC Mbit error to block master ooo. */ 1150 writel(HZIP_CORE_INT_STATUS_M_ECC, 1151 qm->io_base + HZIP_CORE_INT_SET); 1152 } 1153 1154 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm) 1155 { 1156 enum acc_err_result zip_result = ACC_ERR_NONE; 1157 enum acc_err_result dae_result; 1158 u32 err_status; 1159 1160 /* Get device hardware new error status */ 1161 err_status = hisi_zip_get_hw_err_status(qm); 1162 if (err_status) { 1163 if (err_status & qm->err_info.ecc_2bits_mask) 1164 qm->err_status.is_dev_ecc_mbit = true; 1165 hisi_zip_log_hw_error(qm, err_status); 1166 1167 if (err_status & qm->err_info.dev_reset_mask) { 1168 /* Disable the same error reporting until device is recovered. */ 1169 hisi_zip_disable_error_report(qm, err_status); 1170 return ACC_ERR_NEED_RESET; 1171 } else { 1172 hisi_zip_clear_hw_err_status(qm, err_status); 1173 } 1174 } 1175 1176 dae_result = hisi_dae_get_err_result(qm); 1177 1178 return (zip_result == ACC_ERR_NEED_RESET || 1179 dae_result == ACC_ERR_NEED_RESET) ? 1180 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED; 1181 } 1182 1183 static bool hisi_zip_dev_is_abnormal(struct hisi_qm *qm) 1184 { 1185 u32 err_status; 1186 1187 err_status = hisi_zip_get_hw_err_status(qm); 1188 if (err_status & qm->err_info.dev_shutdown_mask) 1189 return true; 1190 1191 return hisi_dae_dev_is_abnormal(qm); 1192 } 1193 1194 static int hisi_zip_set_priv_status(struct hisi_qm *qm) 1195 { 1196 return hisi_dae_close_axi_master_ooo(qm); 1197 } 1198 1199 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1200 { 1201 struct hisi_qm_err_info *err_info = &qm->err_info; 1202 1203 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1204 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1205 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1206 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1207 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1208 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1209 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1210 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1211 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1212 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1213 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1214 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1215 ZIP_RESET_MASK_CAP, qm->cap_ver); 1216 err_info->msi_wr_port = HZIP_WR_PORT; 1217 err_info->acpi_rst = "ZRST"; 1218 } 1219 1220 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1221 .hw_init = hisi_zip_set_user_domain_and_cache, 1222 .hw_err_enable = hisi_zip_hw_error_enable, 1223 .hw_err_disable = hisi_zip_hw_error_disable, 1224 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1225 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1226 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1227 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1228 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1229 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1230 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1231 .err_info_init = hisi_zip_err_info_init, 1232 .get_err_result = hisi_zip_get_err_result, 1233 .set_priv_status = hisi_zip_set_priv_status, 1234 .dev_is_abnormal = hisi_zip_dev_is_abnormal, 1235 }; 1236 1237 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1238 { 1239 struct hisi_qm *qm = &hisi_zip->qm; 1240 struct hisi_zip_ctrl *ctrl; 1241 int ret; 1242 1243 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1244 if (!ctrl) 1245 return -ENOMEM; 1246 1247 hisi_zip->ctrl = ctrl; 1248 ctrl->hisi_zip = hisi_zip; 1249 1250 ret = hisi_zip_set_user_domain_and_cache(qm); 1251 if (ret) 1252 return ret; 1253 1254 ret = hisi_zip_set_high_perf(qm); 1255 if (ret) 1256 return ret; 1257 1258 hisi_zip_open_sva_prefetch(qm); 1259 hisi_qm_dev_err_init(qm); 1260 hisi_zip_debug_regs_clear(qm); 1261 1262 ret = hisi_zip_show_last_regs_init(qm); 1263 if (ret) 1264 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1265 1266 return ret; 1267 } 1268 1269 static int zip_pre_store_cap_reg(struct hisi_qm *qm) 1270 { 1271 struct hisi_qm_cap_record *zip_cap; 1272 struct pci_dev *pdev = qm->pdev; 1273 size_t i, size; 1274 1275 size = ARRAY_SIZE(zip_cap_query_info); 1276 zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL); 1277 if (!zip_cap) 1278 return -ENOMEM; 1279 1280 for (i = 0; i < size; i++) { 1281 zip_cap[i].type = zip_cap_query_info[i].type; 1282 zip_cap[i].name = zip_cap_query_info[i].name; 1283 zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info, 1284 i, qm->cap_ver); 1285 } 1286 1287 qm->cap_tables.dev_cap_table = zip_cap; 1288 qm->cap_tables.dev_cap_size = size; 1289 1290 return 0; 1291 } 1292 1293 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1294 { 1295 u64 alg_msk; 1296 int ret; 1297 1298 qm->pdev = pdev; 1299 qm->mode = uacce_mode; 1300 qm->sqe_size = HZIP_SQE_SIZE; 1301 qm->dev_name = hisi_zip_name; 1302 1303 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1304 QM_HW_PF : QM_HW_VF; 1305 if (qm->fun_type == QM_HW_PF) { 1306 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1307 qm->qp_num = pf_q_num; 1308 qm->debug.curr_qm_qp_num = pf_q_num; 1309 qm->qm_list = &zip_devices; 1310 qm->err_ini = &hisi_zip_err_ini; 1311 if (pf_q_num_flag) 1312 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1313 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1314 /* 1315 * have no way to get qm configure in VM in v1 hardware, 1316 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1317 * to trigger only one VF in v1 hardware. 1318 * 1319 * v2 hardware has no such problem. 1320 */ 1321 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1322 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1323 } 1324 1325 ret = hisi_qm_init(qm); 1326 if (ret) { 1327 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1328 return ret; 1329 } 1330 1331 /* Fetch and save the value of capability registers */ 1332 ret = zip_pre_store_cap_reg(qm); 1333 if (ret) { 1334 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); 1335 goto err_qm_uninit; 1336 } 1337 1338 alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val; 1339 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); 1340 if (ret) { 1341 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1342 goto err_qm_uninit; 1343 } 1344 1345 ret = hisi_dae_set_alg(qm); 1346 if (ret) 1347 goto err_qm_uninit; 1348 1349 return 0; 1350 1351 err_qm_uninit: 1352 hisi_qm_uninit(qm); 1353 return ret; 1354 } 1355 1356 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1357 { 1358 hisi_qm_uninit(qm); 1359 } 1360 1361 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1362 { 1363 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1364 struct hisi_qm *qm = &hisi_zip->qm; 1365 int ret; 1366 1367 if (qm->fun_type == QM_HW_PF) { 1368 ret = hisi_zip_pf_probe_init(hisi_zip); 1369 if (ret) 1370 return ret; 1371 /* enable shaper type 0 */ 1372 if (qm->ver >= QM_HW_V3) { 1373 type_rate |= QM_SHAPER_ENABLE; 1374 1375 /* ZIP need to enable shaper type 1 */ 1376 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1377 qm->type_rate = type_rate; 1378 } 1379 } 1380 1381 return 0; 1382 } 1383 1384 static void hisi_zip_probe_uninit(struct hisi_qm *qm) 1385 { 1386 if (qm->fun_type == QM_HW_VF) 1387 return; 1388 1389 hisi_zip_show_last_regs_uninit(qm); 1390 hisi_zip_close_sva_prefetch(qm); 1391 hisi_qm_dev_err_uninit(qm); 1392 } 1393 1394 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1395 { 1396 struct hisi_zip *hisi_zip; 1397 struct hisi_qm *qm; 1398 int ret; 1399 1400 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1401 if (!hisi_zip) 1402 return -ENOMEM; 1403 1404 qm = &hisi_zip->qm; 1405 1406 ret = hisi_zip_qm_init(qm, pdev); 1407 if (ret) { 1408 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1409 return ret; 1410 } 1411 1412 ret = hisi_zip_probe_init(hisi_zip); 1413 if (ret) { 1414 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1415 goto err_qm_uninit; 1416 } 1417 1418 ret = hisi_qm_start(qm); 1419 if (ret) 1420 goto err_probe_uninit; 1421 1422 ret = hisi_zip_debugfs_init(qm); 1423 if (ret) 1424 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1425 1426 hisi_qm_add_list(qm, &zip_devices); 1427 ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1428 if (ret < 0) { 1429 pci_err(pdev, "failed to register driver to crypto!\n"); 1430 goto err_qm_del_list; 1431 } 1432 1433 if (qm->uacce) { 1434 ret = uacce_register(qm->uacce); 1435 if (ret) { 1436 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1437 goto err_qm_alg_unregister; 1438 } 1439 } 1440 1441 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1442 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1443 if (ret < 0) 1444 goto err_qm_alg_unregister; 1445 } 1446 1447 hisi_qm_pm_init(qm); 1448 1449 return 0; 1450 1451 err_qm_alg_unregister: 1452 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1453 1454 err_qm_del_list: 1455 hisi_qm_del_list(qm, &zip_devices); 1456 hisi_zip_debugfs_exit(qm); 1457 hisi_qm_stop(qm, QM_NORMAL); 1458 1459 err_probe_uninit: 1460 hisi_zip_probe_uninit(qm); 1461 1462 err_qm_uninit: 1463 hisi_zip_qm_uninit(qm); 1464 1465 return ret; 1466 } 1467 1468 static void hisi_zip_remove(struct pci_dev *pdev) 1469 { 1470 struct hisi_qm *qm = pci_get_drvdata(pdev); 1471 1472 hisi_qm_pm_uninit(qm); 1473 hisi_qm_wait_task_finish(qm, &zip_devices); 1474 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1475 hisi_qm_del_list(qm, &zip_devices); 1476 1477 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1478 hisi_qm_sriov_disable(pdev, true); 1479 1480 hisi_zip_debugfs_exit(qm); 1481 hisi_qm_stop(qm, QM_NORMAL); 1482 hisi_zip_probe_uninit(qm); 1483 hisi_zip_qm_uninit(qm); 1484 } 1485 1486 static const struct dev_pm_ops hisi_zip_pm_ops = { 1487 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1488 }; 1489 1490 static const struct pci_error_handlers hisi_zip_err_handler = { 1491 .error_detected = hisi_qm_dev_err_detected, 1492 .slot_reset = hisi_qm_dev_slot_reset, 1493 .reset_prepare = hisi_qm_reset_prepare, 1494 .reset_done = hisi_qm_reset_done, 1495 }; 1496 1497 static struct pci_driver hisi_zip_pci_driver = { 1498 .name = "hisi_zip", 1499 .id_table = hisi_zip_dev_ids, 1500 .probe = hisi_zip_probe, 1501 .remove = hisi_zip_remove, 1502 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1503 hisi_qm_sriov_configure : NULL, 1504 .err_handler = &hisi_zip_err_handler, 1505 .shutdown = hisi_qm_dev_shutdown, 1506 .driver.pm = &hisi_zip_pm_ops, 1507 }; 1508 1509 struct pci_driver *hisi_zip_get_pf_driver(void) 1510 { 1511 return &hisi_zip_pci_driver; 1512 } 1513 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1514 1515 static void hisi_zip_register_debugfs(void) 1516 { 1517 if (!debugfs_initialized()) 1518 return; 1519 1520 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1521 } 1522 1523 static void hisi_zip_unregister_debugfs(void) 1524 { 1525 debugfs_remove_recursive(hzip_debugfs_root); 1526 } 1527 1528 static int __init hisi_zip_init(void) 1529 { 1530 int ret; 1531 1532 hisi_qm_init_list(&zip_devices); 1533 hisi_zip_register_debugfs(); 1534 1535 ret = pci_register_driver(&hisi_zip_pci_driver); 1536 if (ret < 0) { 1537 hisi_zip_unregister_debugfs(); 1538 pr_err("Failed to register pci driver.\n"); 1539 } 1540 1541 return ret; 1542 } 1543 1544 static void __exit hisi_zip_exit(void) 1545 { 1546 pci_unregister_driver(&hisi_zip_pci_driver); 1547 hisi_zip_unregister_debugfs(); 1548 } 1549 1550 module_init(hisi_zip_init); 1551 module_exit(hisi_zip_exit); 1552 1553 MODULE_LICENSE("GPL v2"); 1554 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1555 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1556