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Searched refs:mcr (Results 1 – 25 of 147) sorted by relevance

123456

/linux/arch/arm/mm/
H A Dproc-arm940.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
174 2: mcr p1
[all...]
H A Dproc-mohawk.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
142 mcr p1
[all...]
H A Dproc-arm1020.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 mcr p1
[all...]
H A Dproc-arm946.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
144 mcr p1
[all...]
H A Dproc-arm926.S55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
73 mcr p15, 0, ip, c7, c10, 4 @ drain WB
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
113 mcr p1
[all...]
H A Dproc-arm925.S86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
113 mcr p15, 0, ip, c7, c10, 4 @ drain WB
115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
120 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
134 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
136 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
147 mcr p1
[all...]
H A Dproc-sa1100.S42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
113 mcr p1
[all...]
H A Dproc-arm920.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
81 mcr p15, 0, ip, c7, c10, 4 @ drain WB
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
200 1: mcr p1
[all...]
H A Dproc-v6.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
66 mcr p15, 0, r1, c7, c5, 4 @ ISB
80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
118 mcr p1
[all...]
H A Dproc-arm922.S65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
202 1: mcr p1
[all...]
H A Dproc-xscale.S92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
119 mcr p15, 0, r1, c1, c0, 1
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
150 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
159 mcr p1
[all...]
H A Dproc-xsc3.S69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
233 1: mcr p1
[all...]
H A Dproc-arm1022.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
222 mcr p1
[all...]
H A Dproc-arm1026.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
217 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
220 mcr p1
[all...]
H A Dproc-arm1020e.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
179 1: mcr p1
[all...]
H A Dproc-sa110.S38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
105 mcr p1
[all...]
H A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
132 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
139 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
140 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
155 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
160 mcr p1
[all...]
H A Dproc-arm740.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
76 mcr p15, 0, r0, c6, c3 @ disable area 3~7
77 mcr p15, 0, r0, c6, c4
78 mcr p15, 0, r0, c6, c5
79 mcr p15, 0, r0, c6, c6
80 mcr p15, 0, r0, c6, c7
83 mcr p1
[all...]
H A Dtlb-v6.S40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
72 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
87 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
88 mcr p1
[all...]
H A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
118 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
172 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
179 mcr p15, 0, r0, c7, c10, 4 @ drain WB
200 1: mcr p1
[all...]
H A Dtlb-fa.S41 mcr p15, 0, r3, c7, c10, 4 @ drain WB
44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
48 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
55 mcr p15, 0, r3, c7, c10, 4 @ drain WB
58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
62 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
63 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm720.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
74 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
145 mcr p1
[all...]
/linux/drivers/w1/masters/
H A Dsgi_w1.c23 u32 __iomem *mcr; member
28 static u8 sgi_w1_wait(u32 __iomem *mcr) in sgi_w1_wait() argument
33 mcr_val = readl(mcr); in sgi_w1_wait()
49 writel(MCR_PACK(520, 65), dev->mcr); in sgi_w1_reset_bus()
50 ret = sgi_w1_wait(dev->mcr); in sgi_w1_reset_bus()
66 writel(MCR_PACK(6, 13), dev->mcr); in sgi_w1_touch_bit()
68 writel(MCR_PACK(80, 30), dev->mcr); in sgi_w1_touch_bit()
70 ret = sgi_w1_wait(dev->mcr); in sgi_w1_touch_bit()
86 sdev->mcr = devm_platform_ioremap_resource(pdev, 0); in sgi_w1_probe()
87 if (IS_ERR(sdev->mcr)) in sgi_w1_probe()
[all...]
/linux/drivers/mtd/nand/raw/
H A Dtxx9ndfmc.c113 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_write_buf() local
115 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); in txx9ndfmc_write_buf()
118 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); in txx9ndfmc_write_buf()
138 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_cmd_ctrl() local
140 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); in txx9ndfmc_cmd_ctrl()
141 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; in txx9ndfmc_cmd_ctrl()
142 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; in txx9ndfmc_cmd_ctrl()
144 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; in txx9ndfmc_cmd_ctrl()
146 mcr &= ~TXX9_NDFMCR_CS_MASK; in txx9ndfmc_cmd_ctrl()
147 mcr | in txx9ndfmc_cmd_ctrl()
172 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_calculate_ecc() local
211 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_enable_hwecc() local
[all...]
/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p1
[all...]

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