arm/mm/proc-v6.S

46 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
64 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
66 	mcr	p15, 0, r1, c7, c5, 4		@ ISB
80 	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
81 	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
86 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
109 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
110 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
111 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
118 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
162 	mcr	p15, 0, ip, c7, c14, 0	@ clean+invalidate D cache
163 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
164 	mcr	p15, 0, ip, c7, c15, 0	@ clean+invalidate cache
165 	mcr	p15, 0, ip, c7, c10, 4	@ drain write buffer
166 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
168 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
170 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
173 	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
174 	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
175 	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
177 	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
178 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
179 	mcr	p15, 0, ip, c7, c5, 4	@ ISB
209 	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
214 	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
215 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
216 	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
218 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
219 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
224 	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
226 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer and