Lines Matching refs:mcr
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
744 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
752 mcr p15, 0, r0, c1, c0, 0 @ write control reg
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
761 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
764 mcr p15, 0, r0, c2, c0, 0 @ cache on
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
781 mcr p15, 0, r0, c1, c0, 0 @ write control reg
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
840 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
846 mcr p15, 7, r0, c15, c0, 0
855 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
856 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
863 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
876 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
898 mcr p15, 0, r0, c7, c5, 4 @ ISB
899 mcr p15, 0, r0, c1, c0, 0 @ load control register
902 mcr p15, 0, r0, c7, c5, 4 @ ISB
910 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
911 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
912 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
917 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
926 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
927 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
930 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
1162 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1164 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1165 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1172 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1174 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1183 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1184 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1198 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1200 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1201 mcr p15, 0, r0, c7, c10, 4 @ DSB
1202 mcr p15, 0, r0, c7, c5, 4 @ ISB
1227 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1230 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1238 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1245 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1246 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1247 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1254 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1256 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1267 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1277 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1281 mcr p15, 0, r10, c7, c10, 4 @ DSB
1282 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1283 mcr p15, 0, r10, c7, c10, 4 @ DSB
1284 mcr p15, 0, r10, c7, c5, 4 @ ISB
1292 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1325 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1326 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1327 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1335 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1448 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1489 mcr p15, 4, r1, c1, c0, 0
1491 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)