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Searched refs:base0 (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c243 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_read()
251 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_write()
273 value = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
278 writeb(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
281 readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
282 barrier_data(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
294 value = readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
299 writel(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
319 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], in cpg_mstp_clock_endisable()
323 priv->pub.base0 + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
[all …]
H A Dr7s9210-cpg-mssr.c164 void __iomem *base = pub->base0; in rza2_cpg_clk_register()
H A Drenesas-cpg-mssr.h52 void __iomem *base0; member
H A Dr8a77970-cpg-mssr.c225 void __iomem *base = pub->base0; in r8a77970_cpg_clk_register()
H A Drcar-gen2-cpg.c280 void __iomem *base = pub->base0; in rcar_gen2_cpg_clk_register()
/linux/drivers/mfd/
H A Dmcp-sa11x0.c28 void __iomem *base0; member
35 #define MCCR0(m) ((m)->base0 + 0x00)
36 #define MCDR0(m) ((m)->base0 + 0x08)
37 #define MCDR1(m) ((m)->base0 + 0x0c)
38 #define MCDR2(m) ((m)->base0 + 0x10)
39 #define MCSR(m) ((m)->base0 + 0x18)
195 m->base0 = ioremap(mem0->start, resource_size(mem0)); in mcp_sa11x0_probe()
197 if (!m->base0 || !m->base1) { in mcp_sa11x0_probe()
225 iounmap(m->base0); in mcp_sa11x0_probe()
250 iounmap(m->base0); in mcp_sa11x0_remove()
/linux/drivers/thermal/qcom/
H A Dtsens-v2.c142 struct regmap *map, u32 mode, u32 base0, u32 base1) in tsens_v2_calibrate_sensor() argument
163 slope = (TWO_PT_SHIFTED_GAIN / (base1 - base0)); in tsens_v2_calibrate_sensor()
165 czero = (base0 + sensor->offset - ((base1 - base0) / 3)); in tsens_v2_calibrate_sensor()
169 czero = base0 + sensor->offset - ONE_PT_CZERO_CONST; in tsens_v2_calibrate_sensor()
190 u32 mode, base0, base1; in tsens_v2_calibration() local
204 ret = nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); in tsens_v2_calibration()
215 mode, base0, base1); in tsens_v2_calibration()
/linux/drivers/perf/arm_cspmu/
H A Darm_cspmu.c358 pmiidr = readl(cspmu->base0 + PMIIDR); in arm_cspmu_get_pmiidr()
365 pmpidr = readl(cspmu->base0 + PMPIDR0); in arm_cspmu_get_pmiidr()
369 pmpidr = readl(cspmu->base0 + PMPIDR1); in arm_cspmu_get_pmiidr()
375 pmpidr = readl(cspmu->base0 + PMPIDR2); in arm_cspmu_get_pmiidr()
381 pmpidr = readl(cspmu->base0 + PMPIDR3); in arm_cspmu_get_pmiidr()
385 pmpidr = readl(cspmu->base0 + PMPIDR4); in arm_cspmu_get_pmiidr()
516 writel(PMCR_C | PMCR_P, cspmu->base0 + PMCR); in arm_cspmu_reset_counters()
521 writel(PMCR_E, cspmu->base0 + PMCR); in arm_cspmu_start_counters()
526 writel(0, cspmu->base0 + PMCR); in arm_cspmu_stop_counters()
764 writel(BIT(reg_bit), cspmu->base0 + inten_off); in arm_cspmu_enable_counter()
[all …]
H A Dampere_cspmu.c153 writel(threshold, cspmu->base0 + PMAUXR0); in ampere_cspmu_set_ev_filter()
154 writel(rank, cspmu->base0 + PMAUXR1); in ampere_cspmu_set_ev_filter()
155 writel(bank, cspmu->base0 + PMAUXR2); in ampere_cspmu_set_ev_filter()
H A Dnvidia_cspmu.c222 writel(filter, cspmu->base0 + PMEVFILTR + offset); in nv_cspmu_set_ev_filter()
227 writel(filter, cspmu->base0 + PMEVFILT2R + offset); in nv_cspmu_set_ev_filter()
236 writel(filter, cspmu->base0 + PMCCFILTR); in nv_cspmu_set_cc_filter()
H A Darm_cspmu.h228 void __iomem *base0; member
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-nsp-mux.c111 void __iomem *base0; member
425 base_address = pinctrl->base0; in nsp_pinmux_set()
484 val = readl(pinctrl->base0); in nsp_gpio_request_enable()
488 writel(val, pinctrl->base0); in nsp_gpio_request_enable()
505 val = readl(pinctrl->base0); in nsp_gpio_disable_free()
510 writel(val, pinctrl->base0); in nsp_gpio_disable_free()
568 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in nsp_pinmux_probe()
569 if (IS_ERR(pinctrl->base0)) in nsp_pinmux_probe()
570 return PTR_ERR(pinctrl->base0); in nsp_pinmux_probe()
H A Dpinctrl-cygnus-mux.c103 void __iomem *base0; member
813 val = readl(pinctrl->base0 + grp->mux.offset); in cygnus_pinmux_set()
816 writel(val, pinctrl->base0 + grp->mux.offset); in cygnus_pinmux_set()
948 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in cygnus_pinmux_probe()
949 if (IS_ERR(pinctrl->base0)) { in cygnus_pinmux_probe()
951 return PTR_ERR(pinctrl->base0); in cygnus_pinmux_probe()
H A Dpinctrl-ns2-mux.c117 void __iomem *base0; member
609 base_address = pinctrl->base0; in ns2_pinmux_set()
1039 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in ns2_pinmux_probe()
1040 if (IS_ERR(pinctrl->base0)) in ns2_pinmux_probe()
1041 return PTR_ERR(pinctrl->base0); in ns2_pinmux_probe()
/linux/drivers/gpio/
H A Dgpio-em.c24 void __iomem *base0; member
61 return ioread32(p->base0 + offs); in em_gio_read()
70 iowrite32(value, p->base0 + offs); in em_gio_write()
292 p->base0 = devm_platform_ioremap_resource(pdev, 0); in em_gio_probe()
293 if (IS_ERR(p->base0)) in em_gio_probe()
294 return PTR_ERR(p->base0); in em_gio_probe()
/linux/arch/x86/include/asm/
H A Ddesc_defs.h68 u16 base0; member
77 .base0 = ((base) >> 0) & 0xFFFF, \
106 u16 base0; member
H A Ddesc.h20 desc->base0 = (info->base_addr & 0x0000ffff); in fill_ldt()
169 desc->base0 = (u16) addr; in set_tssldt_descriptor()
384 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); in get_desc_base()
389 desc->base0 = base & 0xffff; in set_desc_base()
/linux/arch/arm/kernel/
H A Dbios32.c207 u32 base0, base1; in pci_fixup_cy82c693() local
210 base0 = 0x1f0; in pci_fixup_cy82c693()
213 base0 = 0x170; in pci_fixup_cy82c693()
218 base0 | PCI_BASE_ADDRESS_SPACE_IO); in pci_fixup_cy82c693()
/linux/drivers/pinctrl/
H A Dpinctrl-keembay.c116 void __iomem *base0; member
1193 return keembay_read_pin(kpc->base0 + offset, pin); in keembay_gpio_get()
1201 reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin); in keembay_gpio_set()
1204 kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin); in keembay_gpio_set()
1207 kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin); in keembay_gpio_set()
1276 val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin); in keembay_gpio_irq_handler()
1675 kpc->base0 = devm_platform_ioremap_resource(pdev, 0); in keembay_pinctrl_probe()
1676 if (IS_ERR(kpc->base0)) in keembay_pinctrl_probe()
1677 return PTR_ERR(kpc->base0); in keembay_pinctrl_probe()
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzt2h.c83 void __iomem *base0, *base1; member
95 ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
925 pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr"); in rzt2h_pinctrl_cfg_regions()
926 if (IS_ERR(pctrl->base0)) in rzt2h_pinctrl_cfg_regions()
927 return PTR_ERR(pctrl->base0); in rzt2h_pinctrl_cfg_regions()
/linux/arch/x86/math-emu/
H A Dfpu_system.h48 return base | ((unsigned long)d->base1 << 16) | d->base0; in seg_get_base()
/linux/drivers/bluetooth/
H A Dbtmrvl_sdio.c565 u8 base0, base1; in btmrvl_sdio_download_fw_w_helper() local
613 base0 = sdio_readb(card->func, in btmrvl_sdio_download_fw_w_helper()
619 base0, base0); in btmrvl_sdio_download_fw_w_helper()
634 len = (((u16) base1) << 8) | base0; in btmrvl_sdio_download_fw_w_helper()
/linux/arch/x86/hyperv/
H A Dhv_vtl.c97 (desc->base1 << 16) | desc->base0; in hv_vtl_system_desc_base()
/linux/drivers/net/wireless/marvell/mwifiex/
H A Dsdio.c1450 u8 base0, base1; in mwifiex_prog_fw_w_helper() local
1492 &base0); in mwifiex_prog_fw_w_helper()
1497 base0, base0); in mwifiex_prog_fw_w_helper()
1509 len = (u16) (((base1 & 0xff) << 8) | (base0 & 0xff)); in mwifiex_prog_fw_w_helper()
/linux/arch/arm64/boot/dts/qcom/
H A Dipq5332.dtsi211 tsens_base0: base0@3e1 {
244 "base0",

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