| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/ |
| H A D | dcn32_mpc.h | 36 SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
43 SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
44 SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
45 SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.h | 35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
43 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
44 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| H A D | dcn30_mpc.h | 47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/ |
| H A D | dcn401_mpc.h | 108 SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\
109 SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\
110 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\
111 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\
112 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\
113 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\
114 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\
115 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\
116 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\
117 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.h | 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.h | 35 SRII(PIXEL_RATE_CNTL, OTG, 0), \
36 SRII(PIXEL_RATE_CNTL, OTG, 1),\
37 SRII(PIXEL_RATE_CNTL, OTG, 2),\
38 SRII(PIXEL_RATE_CNTL, OTG, 3),\
39 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
40 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
41 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
42 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
| H A D | dcn10_mpc.h | 34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.h | 174 SRII(PIXEL_RATE_CNTL, OTG, 0), \
175 SRII(PIXEL_RATE_CNTL, OTG, 1),\
176 SRII(PIXEL_RATE_CNTL, OTG, 2),\
177 SRII(PIXEL_RATE_CNTL, OTG, 3),\
178 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
179 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
180 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
181 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 162 #define SRII(reg_name, block, id)\ macro
697 SRII(PIXEL_RATE_CNTL, OTG, 0), \
698 SRII(PIXEL_RATE_CNTL, OTG, 1),\
699 SRII(PIXEL_RATE_CNTL, OTG, 2),\
700 SRII(PIXEL_RATE_CNTL, OTG, 3),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
704 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 165 #define SRII(reg_name, block, id)\ macro
684 SRII(PIXEL_RATE_CNTL, OTG, 0), \
685 SRII(PIXEL_RATE_CNTL, OTG, 1),\
686 SRII(PIXEL_RATE_CNTL, OTG, 2),\
687 SRII(PIXEL_RATE_CNTL, OTG, 3),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 145 #define SRII(reg_name, block, id)\ macro
690 SRII(PIXEL_RATE_CNTL, OTG, 0), \
691 SRII(PIXEL_RATE_CNTL, OTG, 1),\
692 SRII(PIXEL_RATE_CNTL, OTG, 2),\
693 SRII(PIXEL_RATE_CNTL, OTG, 3),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
697 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 157 #define SRII(reg_name, block, id)\ macro
537 SRII(PIXEL_RATE_CNTL, OTG, 0), \
538 SRII(PIXEL_RATE_CNTL, OTG, 1),\
539 SRII(PIXEL_RATE_CNTL, OTG, 2),\
540 SRII(PIXEL_RATE_CNTL, OTG, 3),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 179 #define SRII(reg_name, block, id)\ macro
689 SRII(PIXEL_RATE_CNTL, OTG, 0), \
690 SRII(PIXEL_RATE_CNTL, OTG, 1),\
691 SRII(PIXEL_RATE_CNTL, OTG, 2),\
692 SRII(PIXEL_RATE_CNTL, OTG, 3),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 144 #define SRII(reg_name, block, id)\ macro
516 SRII(PIXEL_RATE_CNTL, OTG, 0), \
517 SRII(PIXEL_RATE_CNTL, OTG, 1),\
518 SRII(PIXEL_RATE_CNTL, OTG, 2),\
519 SRII(PIXEL_RATE_CNTL, OTG, 3),\
520 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
521 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
522 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
523 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 157 #define SRII(reg_name, block, id)\ macro
541 SRII(PIXEL_RATE_CNTL, OTG, 0), \
542 SRII(PIXEL_RATE_CNTL, OTG, 1),\
543 SRII(PIXEL_RATE_CNTL, OTG, 2),\
544 SRII(PIXEL_RATE_CNTL, OTG, 3),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
547 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
548 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/ |
| H A D | dcn31_hpo_dp_link_encoder.h | 68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 43 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 505 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 784 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 264 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 623 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 525 #define SRII(reg_name, block, id)\ macro
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 629 #define SRII(reg_name, block, id)\ macro
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 544 #define SRII(reg_name, block, id)\ macro
|