1*9ae42f61SWayne Lin /* SPDX-License-Identifier: MIT */ 2*9ae42f61SWayne Lin /* Copyright 2025 Advanced Micro Devices, Inc. */ 3*9ae42f61SWayne Lin 4*9ae42f61SWayne Lin #ifndef _DCN36_RESOURCE_H_ 5*9ae42f61SWayne Lin #define _DCN36_RESOURCE_H_ 6*9ae42f61SWayne Lin 7*9ae42f61SWayne Lin #include "core_types.h" 8*9ae42f61SWayne Lin 9*9ae42f61SWayne Lin extern struct _vcs_dpi_ip_params_st dcn3_6_ip; 10*9ae42f61SWayne Lin extern struct _vcs_dpi_soc_bounding_box_st dcn3_6_soc; 11*9ae42f61SWayne Lin 12*9ae42f61SWayne Lin #define TO_DCN36_RES_POOL(pool)\ 13*9ae42f61SWayne Lin container_of(pool, struct dcn36_resource_pool, base) 14*9ae42f61SWayne Lin 15*9ae42f61SWayne Lin struct dcn36_resource_pool { 16*9ae42f61SWayne Lin struct resource_pool base; 17*9ae42f61SWayne Lin }; 18*9ae42f61SWayne Lin 19*9ae42f61SWayne Lin struct resource_pool *dcn36_create_resource_pool( 20*9ae42f61SWayne Lin const struct dc_init_data *init_data, 21*9ae42f61SWayne Lin struct dc *dc); 22*9ae42f61SWayne Lin 23*9ae42f61SWayne Lin #define HWSEQ_DCN36_REG_LIST()\ 24*9ae42f61SWayne Lin SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 25*9ae42f61SWayne Lin SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 26*9ae42f61SWayne Lin SR(DIO_MEM_PWR_CTRL), \ 27*9ae42f61SWayne Lin SR(ODM_MEM_PWR_CTRL3), \ 28*9ae42f61SWayne Lin SR(MMHUBBUB_MEM_PWR_CNTL), \ 29*9ae42f61SWayne Lin SR(DCCG_GATE_DISABLE_CNTL), \ 30*9ae42f61SWayne Lin SR(DCCG_GATE_DISABLE_CNTL2), \ 31*9ae42f61SWayne Lin SR(DCCG_GATE_DISABLE_CNTL4), \ 32*9ae42f61SWayne Lin SR(DCCG_GATE_DISABLE_CNTL5), \ 33*9ae42f61SWayne Lin SR(DCFCLK_CNTL),\ 34*9ae42f61SWayne Lin SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 35*9ae42f61SWayne Lin SRII(PIXEL_RATE_CNTL, OTG, 0), \ 36*9ae42f61SWayne Lin SRII(PIXEL_RATE_CNTL, OTG, 1),\ 37*9ae42f61SWayne Lin SRII(PIXEL_RATE_CNTL, OTG, 2),\ 38*9ae42f61SWayne Lin SRII(PIXEL_RATE_CNTL, OTG, 3),\ 39*9ae42f61SWayne Lin SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 40*9ae42f61SWayne Lin SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 41*9ae42f61SWayne Lin SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 42*9ae42f61SWayne Lin SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 43*9ae42f61SWayne Lin SR(MICROSECOND_TIME_BASE_DIV), \ 44*9ae42f61SWayne Lin SR(MILLISECOND_TIME_BASE_DIV), \ 45*9ae42f61SWayne Lin SR(DISPCLK_FREQ_CHANGE_CNTL), \ 46*9ae42f61SWayne Lin SR(RBBMIF_TIMEOUT_DIS), \ 47*9ae42f61SWayne Lin SR(RBBMIF_TIMEOUT_DIS_2), \ 48*9ae42f61SWayne Lin SR(DCHUBBUB_CRC_CTRL), \ 49*9ae42f61SWayne Lin SR(DPP_TOP0_DPP_CRC_CTRL), \ 50*9ae42f61SWayne Lin SR(MPC_CRC_CTRL), \ 51*9ae42f61SWayne Lin SR(DOMAIN0_PG_CONFIG), \ 52*9ae42f61SWayne Lin SR(DOMAIN1_PG_CONFIG), \ 53*9ae42f61SWayne Lin SR(DOMAIN2_PG_CONFIG), \ 54*9ae42f61SWayne Lin SR(DOMAIN3_PG_CONFIG), \ 55*9ae42f61SWayne Lin SR(DOMAIN16_PG_CONFIG), \ 56*9ae42f61SWayne Lin SR(DOMAIN17_PG_CONFIG), \ 57*9ae42f61SWayne Lin SR(DOMAIN18_PG_CONFIG), \ 58*9ae42f61SWayne Lin SR(DOMAIN19_PG_CONFIG), \ 59*9ae42f61SWayne Lin SR(DOMAIN0_PG_STATUS), \ 60*9ae42f61SWayne Lin SR(DOMAIN1_PG_STATUS), \ 61*9ae42f61SWayne Lin SR(DOMAIN2_PG_STATUS), \ 62*9ae42f61SWayne Lin SR(DOMAIN3_PG_STATUS), \ 63*9ae42f61SWayne Lin SR(DOMAIN16_PG_STATUS), \ 64*9ae42f61SWayne Lin SR(DOMAIN17_PG_STATUS), \ 65*9ae42f61SWayne Lin SR(DOMAIN18_PG_STATUS), \ 66*9ae42f61SWayne Lin SR(DOMAIN19_PG_STATUS), \ 67*9ae42f61SWayne Lin SR(DC_IP_REQUEST_CNTL), \ 68*9ae42f61SWayne Lin SR(AZALIA_AUDIO_DTO), \ 69*9ae42f61SWayne Lin SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 70*9ae42f61SWayne Lin SR(HPO_TOP_HW_CONTROL),\ 71*9ae42f61SWayne Lin SR(DMU_CLK_CNTL) 72*9ae42f61SWayne Lin 73*9ae42f61SWayne Lin #endif /* _DCN36_RESOURCE_H_ */ 74