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/linux-5.10/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
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Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI) binding
10 - Han Xu <han.xu@nxp.com>
13 - $ref: "nand-controller.yaml"
17 flash chips. The device tree may optionally contain sub-nodes
24 - enum:
25 - fsl,imx23-gpmi-nand
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/linux-5.10/Documentation/devicetree/bindings/arm/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/linux-5.10/drivers/mtd/nand/raw/
Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
90 #define MTK_NAME "mtk-nand"
147 struct mtk_ecc *ecc; member
186 return (u8 *)p + i * chip->ecc.size; in data_ptr()
198 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
199 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
200 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
201 poi = chip->oob_poi; in oob_ptr()
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Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
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Dnandsim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
143 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
144 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
163 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
165 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
166 "be correctable in 512-byte blocks");
183 /* Busy-wait delay macros (microseconds, milliseconds) */
190 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
193 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
200 (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column)
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/linux-5.10/drivers/mtd/nand/
Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
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/linux-5.10/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
87 /* Reset Hardware ECC for read */
89 /* Reset Hardware ECC for write */
91 /* Enable Hardware ECC before syndrome is read back from flash */
96 * ecc.correct() returns -EBADMSG.
122 * Chip requires ready check on read (for auto-incremented sequential read).
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/linux-5.10/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
116 return -ETIMEDOUT; in gpmi_reset_block()
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/linux-5.10/arch/s390/include/uapi/asm/
Dpkey.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
31 /* Minimum size of a key blob */
40 /* the newer ioctls use a pkey_key_type enum for type information */
50 /* the newer ioctls use a pkey_key_size enum for key size information */
58 /* some of the newer ioctls use these flags */
113 __u16 cardnr; /* in: card to use or FFFF for any */
124 __u16 cardnr; /* in: card to use or FFFF for any */
136 __u16 cardnr; /* in: card to use or FFFF for any */
230 * (return -1 with errno ENODEV). You may use the PKEY_APQNS4KT ioctl to
234 * generating CCA cipher keys you can use one or more of the PKEY_KEYGEN_*
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/linux-5.10/Documentation/admin-guide/
Dras.rst33 -------------
44 * Memory – add error correction logic (ECC) to detect and correct errors;
47 Self-Monitoring, Analysis and Reporting Technology (SMART).
55 ---------------
57 Most mechanisms used on modern systems use technologies like Hamming
68 * **Correctable Error (CE)** - the error detection mechanism detected and
72 * **Uncorrected Error (UE)** - the amount of errors happened above the error
73 correction threshold, and the system was unable to auto-correct.
75 * **Fatal Error** - when an UE error happens on a critical component of the
79 * **Non-fatal Error** - when an UE error happens on an unused component,
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/linux-5.10/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
16 #include <linux/dma-mapping.h>
87 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
233 /* List of NAND hosts (one for each chip-select) */
236 /* EDU info, per-transaction */
254 /* in-memory cache of the FLASH_CACHE, used only for some commands */
260 const u8 *cs_offsets; /* within each chip-select */
270 /* for low-power standby/resume only */
290 /* use for low-power standby/resume only */
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/linux-5.10/drivers/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 Use VIA PadLock for AES algorithm.
39 called padlock-aes.
48 Use VIA PadLock for SHA1/SHA256 algorithms.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
104 down the use of the available crypto hardware.
113 kernel or userspace applications may use these functions.
131 AES cipher algorithms for use with protected key.
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/linux-5.10/include/linux/
Dedac.h6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
98 * can't be corrected by ECC, but it is not
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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/linux-5.10/drivers/net/ethernet/intel/e1000e/
Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
147 /* Use byte values for the following shift parameters
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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/linux-5.10/drivers/edac/
Damd64_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is
9 * cleared to prevent re-enabling the hardware by this driver.
18 /* Per-node stuff */
23 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
65 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
78 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
90 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); in f15h_select_dct()
91 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
93 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
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/linux-5.10/drivers/mtd/
Dsm_ftl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
34 /* ------------------- sysfs attributes ---------------------------------- */
47 strncpy(buf, sm_attr->data, sm_attr->len); in sm_attr_show()
48 return sm_attr->len; in sm_attr_show()
61 vendor = kstrndup(ftl->cis_buffer + SM_CIS_VENDOR_OFFSET, in sm_create_sysfs_attributes()
62 SM_SMALL_PAGE - SM_CIS_VENDOR_OFFSET, GFP_KERNEL); in sm_create_sysfs_attributes()
72 sysfs_attr_init(&vendor_attribute->dev_attr.attr); in sm_create_sysfs_attributes()
74 vendor_attribute->data = vendor; in sm_create_sysfs_attributes()
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/linux-5.10/fs/pstore/
Dplatform.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Persistent Storage - platform driver interface parts.
5 * Copyright (C) 2007-2008 Google, Inc.
39 * We defer making "oops" entries appear in pstore - see
43 static int pstore_update_ms = -1;
46 "(default is -1, which means runtime updates are disabled; "
57 "powerpc-ofw",
58 "powerpc-common",
60 "powerpc-opal",
81 MODULE_PARM_DESC(backend, "specific backend to use");
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/linux-5.10/arch/arm/boot/dts/
Dimx7-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2016-2020 Toradex
8 compatible = "pwm-backlight";
9 pinctrl-names = "default";
10 pinctrl-0 = <&pinctrl_gpio_bl_on>;
12 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
15 reg_module_3v3: regulator-module-3v3 {
16 compatible = "regulator-fixed";
17 regulator-name = "+V3.3";
18 regulator-min-microvolt = <3300000>;
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/linux-5.10/drivers/mtd/ubi/
Dubi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
31 #include "ubi-media.h"
57 * This marker in the EBA table means that the LEB is um-mapped.
60 #define UBI_LEB_UNMAPPED -1
64 * returning error. The below constant defines how many times UBI re-tries.
70 * number of (global) erase cycles PEBs are protected from the wear-leveling
76 #define UBI_UNKNOWN -1
86 * Error codes returned by the I/O sub-system.
91 * (uncorrectable ECC error in case of NAND)
95 * (uncorrectable ECC error in case of NAND)
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Dio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * UBI input/output sub-system.
12 * This sub-system provides a uniform way to work with all kinds of the
18 * sub-system validates every single header it reads from the flash media.
24 * (i.e. aligned to the minimum I/O unit size). Data starts next to the VID
35 * @ubi->mtd->writesize field. But as an exception, UBI admits use of another
41 * headers at one NAND page. Thus, UBI may use "sub-page" size as the minimal
42 * I/O unit for the headers (the @ubi->hdrs_min_io_size field). But it still
43 * reports NAND page size (@ubi->min_io_size) as a minimal I/O unit for the UBI
46 * Example: some Samsung NANDs with 2KiB pages allow 4x 512-byte writes, so
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/linux-5.10/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 This option is best suited for non-NUMA systems with
56 memory hot-plug systems. This is normal.
60 hot-plug and hot-remove.
83 # Both the NUMA code and DISCONTIGMEM use arrays of pg_data_t's
138 # Keep arch NUMA mapping infrastructure post-init.
154 bool "Allow for memory hot-add"
173 See Documentation/admin-guide/mm/memory-hotplug.rst for more information.
175 Say Y here if you want all hot-plugged memory blocks to appear in
177 Say N here if you want the default policy to keep all hot-plugged
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/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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