1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE		-1
82 #define NAND_DATA_IFACE_CHECK_ONLY	-1
85  * Constants for Hardware ECC
87 /* Reset Hardware ECC for read */
89 /* Reset Hardware ECC for write */
91 /* Enable Hardware ECC before syndrome is read back from flash */
96  * ecc.correct() returns -EBADMSG.
122  * Chip requires ready check on read (for auto-incremented sequential read).
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
172  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173  * on the default ->cmdfunc() implementation, you may want to let the core
182  * Whether the NAND chip is a boot medium. Drivers might use this information
183  * to select ECC algorithms supported by the boot ROM or similar restrictions.
206  * Some controllers with pipelined ECC engines override the BBM marker with
207  * data or ECC bytes, thus making bad block detection through bad block marker
223  * struct nand_parameters - NAND generic parameters from the parameter page
245  * struct nand_id - NAND id structure
255  * struct nand_ecc_step_info - ECC step information of ECC engine
256  * @stepsize: data bytes per ECC step
267  * struct nand_ecc_caps - capability of ECC engine
268  * @stepinfos: array of ECC step information
269  * @nstepinfos: number of ECC step information
270  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
293  * struct nand_ecc_ctrl - Control structure for ECC
294  * @engine_type: ECC engine type
296  * @algo:	ECC algorithm
297  * @steps:	number of ECC steps per page
298  * @size:	data bytes per ECC step
299  * @bytes:	ECC bytes per step
300  * @strength:	max number of correctible bits per ECC step
301  * @total:	total number of ECC bytes per page
302  * @prepad:	padding information for syndrome based ECC generators
303  * @postpad:	padding information for syndrome based ECC generators
304  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
305  * @priv:	pointer to private ECC control data
306  * @calc_buf:	buffer for calculated ECC, size is oobsize.
307  * @code_buf:	buffer for ECC read from flash, size is oobsize.
308  * @hwctl:	function to control hardware ECC generator. Must only
309  *		be provided if an hardware ECC is available
310  * @calculate:	function for ECC calculation or readback from ECC hardware
311  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
313  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
314  *		ECC strength, or any other error code if the error is not
316  *		If -EBADMSG is returned the input buffers should be left
318  * @read_page_raw:	function to read a raw page without ECC. This function
319  *			should hide the specific layout used by the ECC
320  *			controller and always return contiguous in-band and
321  *			out-of-band data even if they're not stored
323  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
324  *			out-of-band data).
325  * @write_page_raw:	function to write a raw page without ECC. This function
326  *			should hide the specific layout used by the ECC
328  *			in-band and out-of-band data. ECC controller is
331  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
332  *			out-of-band data).
333  * @read_page:	function to read a page according to the ECC generator
335  *		any single ECC step, -EIO hw error
336  * @read_subpage:	function to read parts of the page covered by ECC;
338  * @write_subpage:	function to write parts of the page covered by ECC.
339  * @write_page:	function to write a page according to the ECC generator
341  * @write_oob_raw:	function to write chip OOB data without ECC
342  * @read_oob_raw:	function to read chip OOB data without ECC
386  * struct nand_sdr_timings - SDR NAND chip timings
407  * @tCHZ_max: CE# high to output hi-Z
416  * @tIR_min: Output hi-Z to RE# low
423  * @tRHZ_max: RE# high to output hi-Z
478  * enum nand_interface_type - NAND interface type
486  * struct nand_interface_config - NAND interface timing
490  * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
503  * nand_get_sdr_timings - get SDR timing from data interface
509 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
510 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
512 	return &conf->timings.sdr;  in nand_get_sdr_timings()
516  * struct nand_op_cmd_instr - Definition of a command instruction
524  * struct nand_op_addr_instr - Definition of an address instruction
534  * struct nand_op_data_instr - Definition of a data instruction
539  * @force_8bit: force 8-bit access
555  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
563  * enum nand_op_instr_type - Definition of all instruction types
579  * struct nand_op_instr - Instruction object
581  * @ctx:  extra data associated to the instruction. You'll have to use the
583  * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
584  * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
585  * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
587  * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
694  * struct nand_subop - a sub operation
695  * @cs: the CS line to select for this NAND sub-operation
699  *			   of the sub-operation
701  *			of the sub-operation
707  * be split by the parser into sub-operations which will be passed to the
728  * struct nand_op_parser_addr_constraints - Constraints for address instructions
737  * struct nand_op_parser_data_constraints - Constraints for data instructions
745  * struct nand_op_parser_pattern_elem - One element of a pattern
795  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
798  * @exec: the function that will issue a sub-operation
804  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
827  * struct nand_op_parser - NAND controller operation parser descriptor
853  * struct nand_operation - NAND operation descriptor
858  * The actual operation structure that will be passed to chip->exec_op().
881 	switch (instr->type) {  in nand_op_trace()
884 			 instr->ctx.cmd.opcode);  in nand_op_trace()
888 			 instr->ctx.addr.naddrs,  in nand_op_trace()
889 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
890 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
891 			 instr->ctx.addr.addrs);  in nand_op_trace()
895 			 instr->ctx.data.len,  in nand_op_trace()
896 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
897 			 ", force 8-bit" : "");  in nand_op_trace()
901 			 instr->ctx.data.len,  in nand_op_trace()
902 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
903 			 ", force 8-bit" : "");  in nand_op_trace()
907 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
914  * struct nand_controller_ops - Controller operations
918  *		 size have been set up. ECC requirements are available if
920  *		 choose the appropriate ECC configuration and allocate
924  *		 nand_controller_ops->attach_chip().
927  *		 This method replaces chip->legacy.cmdfunc(),
928  *		 chip->legacy.{read,write}_{buf,byte,word}(),
929  *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
946  * struct nand_controller - Structure used to describe a NAND controller
958 	mutex_init(&nfc->lock);  in nand_controller_init()
962  * struct nand_legacy - NAND chip legacy fields/hooks
1013  * struct nand_chip_ops - NAND chip operations
1018  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1032  * struct nand_manufacturer - NAND manufacturer structure
1042  * struct nand_chip - NAND Private Flash Chip Data
1049  *          to use any of these fields/hooks, and if you're modifying an
1065  * @badblockbits: Minimum number of set bits in a good block's bad block marker
1074  * @pagemask: Page number mask = number of (pages / chip) - 1
1080  * @pagecache.page: Page number currently in the cache. -1 means no page is
1082  * @buf_align: Minimum buffer alignment required by a platform
1086  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1093  * @ecc: The ECC controller structure
1143 	struct nand_ecc_ctrl ecc;  member
1154 	return &chip->base.mtd;  in nand_to_mtd()
1159 	return chip->priv;  in nand_get_controller_data()
1164 	chip->priv = priv;  in nand_set_controller_data()
1170 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1175 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1190  * nand_get_interface_config - Retrieve the current interface configuration
1197 	return chip->current_interface_config;  in nand_get_interface_config()
1225 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1226 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1229  * struct nand_flash_dev - NAND Flash Device ID Structure
1230  * @name: a human-readable name of the NAND chip
1245  * @ecc: ECC correctability and step information from the datasheet.
1246  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1248  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1250  *               For example, the "4bit ECC for each 512Byte" can be set with
1271 	} ecc;  member
1283 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1284 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1285 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1307 				void *ecc, int ecclen,
1403  * nand_get_data_buf() - Get the internal page buffer
1406  * Returns the pre-allocated page buffer after invalidating the cache. This
1418 	chip->pagecache.page = -1;  in nand_get_data_buf()
1420 	return chip->data_buf;  in nand_get_data_buf()