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/linux-5.10/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
[all …]
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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/linux-5.10/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
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/linux-5.10/Documentation/devicetree/bindings/arm/
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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Dcci.txt5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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Darm,scmi.txt2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
41 Each protocol supported shall have a sub-node with corresponding compatible
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/linux-5.10/drivers/iommu/arm/arm-smmu/
Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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/linux-5.10/drivers/perf/
Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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/linux-5.10/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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/linux-5.10/drivers/rtc/
Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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/linux-5.10/arch/xtensa/include/asm/
Dthread_info.h2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
51 unsigned long status; /* thread-synchronous flags */
73 * macros/functions for gaining access to the thread information structure
99 #define GET_THREAD_INFO(reg,sp) \ argument
100 extui reg, sp, 0, CURRENT_SHIFT; \
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/linux-5.10/drivers/iommu/
Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
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/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
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/linux-5.10/drivers/staging/wfx/
Dfwio.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
92 return -ENOMEM; in sram_write_dma_safe()
111 wdev->pdata.file_fw, keyset_chip); in get_firmware()
112 ret = firmware_request_nowarn(fw, filename, wdev->dev); in get_firmware()
114 dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", in get_firmware()
115 filename, wdev->pdata.file_fw); in get_firmware()
117 wdev->pdata.file_fw); in get_firmware()
118 ret = request_firmware(fw, filename, wdev->dev); in get_firmware()
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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/linux-5.10/drivers/mailbox/
Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/soc/ti/ti-msgmgr.h>
23 #define Q_DATA_OFFSET(proxy, queue, reg) \ argument
24 ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
29 #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ argument
30 (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
40 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
52 * struct ti_msgmgr_desc - Description of message manager integration
62 * @valid_queues: List of Valid queues that the processor can access
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/linux-5.10/drivers/crypto/caam/
Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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/linux-5.10/drivers/irqchip/
Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
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/linux-5.10/arch/powerpc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 # On Book3S 64, the default virtual address space for 64-bit processes
20 # between bottom-up and top-down allocations for applications that
23 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
24 default 33 if PPC_BOOK3S_64 # 33 = 45 (32T) - 12 (4K)
26 # On all other 64-bit platforms (currently only Book3E), the virtual
29 default 32 if 64BIT # 32 = 44 (16T) - 12 (4K)
31 # For 32-bit, use the compat values, as they're the same.
36 default 14 if 64BIT && PPC_64K_PAGES # 14 = 30 (1GB) - 16 (64K)
37 default 18 if 64BIT # 18 = 30 (1GB) - 12 (4K)
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/linux-5.10/arch/arm/mach-imx/
Dcpu-imx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
42 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
60 if (mx5_cpu_rev == -1) in mx51_revision()
71 * Dependent on link order - so the assumption is that vfp_init is called
88 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
108 if (mx5_cpu_rev == -1) in mx53_revision()
134 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
138 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
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/linux-5.10/arch/arm/mach-omap2/
Dcontrol.h2 * arch/arm/mach-omap2/control.h
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
22 #define OMAP242X_CTRL_REGADDR(reg) \ argument
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24 #define OMAP243X_CTRL_REGADDR(reg) \ argument
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26 #define OMAP343X_CTRL_REGADDR(reg) \ argument
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28 #define AM33XX_CTRL_REGADDR(reg) \ argument
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/linux-5.10/arch/powerpc/kvm/
Dbook3s_hv_uvmem.c1 // SPDX-License-Identifier: GPL-2.0
3 * Secure pages management: Migration of pages between normal and secure
10 * A pseries guest can be run as secure guest on Ultravisor-enabled
13 * hypervisor (HV) and secure memory managed by Ultravisor (UV).
15 * The page-in or page-out requests from UV will come to HV as hcalls and
18 * Private ZONE_DEVICE memory equal to the amount of secure memory
19 * available in the platform for running secure guests is hotplugged.
20 * Whenever a page belonging to the guest becomes secure, a page from this
21 * private device memory is used to represent and track that secure page
31 * kvm->arch.uvmem_lock is a per-guest lock that prevents concurrent
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/linux-5.10/arch/arm/mm/
Dcache-l2x0.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
54 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) in l2c_wait_mask() argument
57 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
62 * By default, we write directly to secure registers. Platforms must
63 * override this if they are running non-secure.
65 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec() argument
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