Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
103 #define IMCTR 0x0000 /* R-Car Gen2/3 */
104 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
105 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
106 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
108 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */
109 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
110 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
111 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
112 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
113 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
114 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
116 #define IMBUSCR 0x000c /* R-Car Gen2 only */
117 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
118 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
120 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
121 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
123 #define IMSTR 0x0020 /* R-Car Gen2/3 */
124 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
125 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
126 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
127 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
129 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */
131 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
132 #define IMEUAR 0x0034 /* R-Car Gen3 only */
136 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
137 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
138 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
139 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
140 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
143 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
144 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
146 /* -----------------------------------------------------------------------------
154 return mmu->root == mmu; in ipmmu_is_root()
176 /* -----------------------------------------------------------------------------
177 * Read/Write Access
182 return ioread32(mmu->base + offset); in ipmmu_read()
188 iowrite32(data, mmu->base + offset); in ipmmu_write()
192 unsigned int context_id, unsigned int reg) in ipmmu_ctx_reg() argument
194 return mmu->features->ctx_offset_base + in ipmmu_ctx_reg()
195 context_id * mmu->features->ctx_offset_stride + reg; in ipmmu_ctx_reg()
199 unsigned int context_id, unsigned int reg) in ipmmu_ctx_read() argument
201 return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg)); in ipmmu_ctx_read()
205 unsigned int context_id, unsigned int reg, u32 data) in ipmmu_ctx_write() argument
207 ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data); in ipmmu_ctx_write()
211 unsigned int reg) in ipmmu_ctx_read_root() argument
213 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); in ipmmu_ctx_read_root()
217 unsigned int reg, u32 data) in ipmmu_ctx_write_root() argument
219 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_root()
223 unsigned int reg, u32 data) in ipmmu_ctx_write_all() argument
225 if (domain->mmu != domain->mmu->root) in ipmmu_ctx_write_all()
226 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); in ipmmu_ctx_write_all()
228 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_all()
231 static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg) in ipmmu_utlb_reg() argument
233 return mmu->features->utlb_offset_base + reg; in ipmmu_utlb_reg()
248 /* -----------------------------------------------------------------------------
260 dev_err_ratelimited(domain->mmu->dev, in ipmmu_tlb_sync()
261 "TLB sync timed out -- MMU may be deadlocked\n"); in ipmmu_tlb_sync()
270 u32 reg; in ipmmu_tlb_invalidate() local
272 reg = ipmmu_ctx_read_root(domain, IMCTR); in ipmmu_tlb_invalidate()
273 reg |= IMCTR_FLUSH; in ipmmu_tlb_invalidate()
274 ipmmu_ctx_write_all(domain, IMCTR, reg); in ipmmu_tlb_invalidate()
285 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_utlb_enable()
288 * TODO: Reference-count the microTLB as several bus masters can be in ipmmu_utlb_enable()
295 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | in ipmmu_utlb_enable()
297 mmu->utlb_ctx[utlb] = domain->context_id; in ipmmu_utlb_enable()
306 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_utlb_disable()
309 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; in ipmmu_utlb_disable()
331 /* -----------------------------------------------------------------------------
341 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_allocate_context()
343 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); in ipmmu_domain_allocate_context()
344 if (ret != mmu->num_ctx) { in ipmmu_domain_allocate_context()
345 mmu->domains[ret] = domain; in ipmmu_domain_allocate_context()
346 set_bit(ret, mmu->ctx); in ipmmu_domain_allocate_context()
348 ret = -EBUSY; in ipmmu_domain_allocate_context()
350 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_allocate_context()
360 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_free_context()
362 clear_bit(context_id, mmu->ctx); in ipmmu_domain_free_context()
363 mmu->domains[context_id] = NULL; in ipmmu_domain_free_context()
365 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_free_context()
374 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
380 * We use long descriptors and allocate the whole 32-bit VA space to in ipmmu_domain_setup_context()
383 if (domain->mmu->features->twobit_imttbcr_sl0) in ipmmu_domain_setup_context()
388 if (domain->mmu->features->cache_snoop) in ipmmu_domain_setup_context()
396 domain->cfg.arm_lpae_s1_cfg.mair); in ipmmu_domain_setup_context()
399 if (domain->mmu->features->setup_imbuscr) in ipmmu_domain_setup_context()
412 * Enable the MMU and interrupt generation. The long-descriptor in ipmmu_domain_setup_context()
428 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory in ipmmu_domain_init_context()
429 * access, Long-descriptor format" that the NStable bit being set in a in ipmmu_domain_init_context()
432 * not to comply with this, as it generates a secure access page fault in ipmmu_domain_init_context()
434 * non-secure mode. in ipmmu_domain_init_context()
436 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; in ipmmu_domain_init_context()
437 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; in ipmmu_domain_init_context()
438 domain->cfg.ias = 32; in ipmmu_domain_init_context()
439 domain->cfg.oas = 40; in ipmmu_domain_init_context()
440 domain->cfg.tlb = &ipmmu_flush_ops; in ipmmu_domain_init_context()
441 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); in ipmmu_domain_init_context()
442 domain->io_domain.geometry.force_aperture = true; in ipmmu_domain_init_context()
445 * cache handling. For now, delegate it to the io-pgtable code. in ipmmu_domain_init_context()
447 domain->cfg.coherent_walk = false; in ipmmu_domain_init_context()
448 domain->cfg.iommu_dev = domain->mmu->root->dev; in ipmmu_domain_init_context()
453 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); in ipmmu_domain_init_context()
457 domain->context_id = ret; in ipmmu_domain_init_context()
459 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, in ipmmu_domain_init_context()
461 if (!domain->iop) { in ipmmu_domain_init_context()
462 ipmmu_domain_free_context(domain->mmu->root, in ipmmu_domain_init_context()
463 domain->context_id); in ipmmu_domain_init_context()
464 return -EINVAL; in ipmmu_domain_init_context()
473 if (!domain->mmu) in ipmmu_domain_destroy_context()
484 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); in ipmmu_domain_destroy_context()
487 /* -----------------------------------------------------------------------------
494 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_domain_irq()
516 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", in ipmmu_domain_irq()
519 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", in ipmmu_domain_irq()
531 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) in ipmmu_domain_irq()
534 dev_err_ratelimited(mmu->dev, in ipmmu_domain_irq()
548 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_irq()
553 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_irq()
554 if (!mmu->domains[i]) in ipmmu_irq()
556 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) in ipmmu_irq()
560 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_irq()
565 /* -----------------------------------------------------------------------------
577 mutex_init(&domain->mutex); in __ipmmu_domain_alloc()
579 return &domain->io_domain; in __ipmmu_domain_alloc()
613 free_io_pgtable_ops(domain->iop); in ipmmu_domain_free()
628 return -ENXIO; in ipmmu_attach_device()
631 mutex_lock(&domain->mutex); in ipmmu_attach_device()
633 if (!domain->mmu) { in ipmmu_attach_device()
635 domain->mmu = mmu; in ipmmu_attach_device()
639 domain->mmu = NULL; in ipmmu_attach_device()
642 domain->context_id); in ipmmu_attach_device()
644 } else if (domain->mmu != mmu) { in ipmmu_attach_device()
650 dev_name(mmu->dev), dev_name(domain->mmu->dev)); in ipmmu_attach_device()
651 ret = -EINVAL; in ipmmu_attach_device()
653 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); in ipmmu_attach_device()
655 mutex_unlock(&domain->mutex); in ipmmu_attach_device()
660 for (i = 0; i < fwspec->num_ids; ++i) in ipmmu_attach_device()
661 ipmmu_utlb_enable(domain, fwspec->ids[i]); in ipmmu_attach_device()
673 for (i = 0; i < fwspec->num_ids; ++i) in ipmmu_detach_device()
674 ipmmu_utlb_disable(domain, fwspec->ids[i]); in ipmmu_detach_device()
687 return -ENODEV; in ipmmu_map()
689 return domain->iop->map(domain->iop, iova, paddr, size, prot, gfp); in ipmmu_map()
697 return domain->iop->unmap(domain->iop, iova, size, gather); in ipmmu_unmap()
704 if (domain->mmu) in ipmmu_flush_iotlb_all()
721 return domain->iop->iova_to_phys(domain->iop, iova); in ipmmu_iova_to_phys()
729 ipmmu_pdev = of_find_device_by_node(args->np); in ipmmu_init_platform_device()
731 return -ENODEV; in ipmmu_init_platform_device()
773 * For R-Car Gen3 use a white list to opt-in slave devices. in ipmmu_slave_whitelist()
779 /* Check whether this R-Car Gen3 can use the IPMMU correctly or not */ in ipmmu_slave_whitelist()
797 return -ENODEV; in ipmmu_of_xlate()
799 iommu_fwspec_add_ids(dev, spec->args, 1); in ipmmu_of_xlate()
801 /* Initialize once - xlate() will call multiple times */ in ipmmu_of_xlate()
818 * - Create one mapping per context (TLB). in ipmmu_init_arm_mapping()
819 * - Make the mapping size configurable ? We currently use a 2GB mapping in ipmmu_init_arm_mapping()
822 if (!mmu->mapping) { in ipmmu_init_arm_mapping()
828 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); in ipmmu_init_arm_mapping()
833 mmu->mapping = mapping; in ipmmu_init_arm_mapping()
837 ret = arm_iommu_attach_device(dev, mmu->mapping); in ipmmu_init_arm_mapping()
846 if (mmu->mapping) in ipmmu_init_arm_mapping()
847 arm_iommu_release_mapping(mmu->mapping); in ipmmu_init_arm_mapping()
860 return ERR_PTR(-ENODEV); in ipmmu_probe_device()
862 return &mmu->iommu; in ipmmu_probe_device()
873 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); in ipmmu_probe_finalize()
886 if (mmu->group) in ipmmu_find_group()
887 return iommu_group_ref_get(mmu->group); in ipmmu_find_group()
891 mmu->group = group; in ipmmu_find_group()
915 /* -----------------------------------------------------------------------------
924 for (i = 0; i < mmu->num_ctx; ++i) in ipmmu_device_reset()
958 .compatible = "renesas,ipmmu-vmsa",
961 .compatible = "renesas,ipmmu-r8a774a1",
964 .compatible = "renesas,ipmmu-r8a774b1",
967 .compatible = "renesas,ipmmu-r8a774c0",
970 .compatible = "renesas,ipmmu-r8a774e1",
973 .compatible = "renesas,ipmmu-r8a7795",
976 .compatible = "renesas,ipmmu-r8a7796",
979 .compatible = "renesas,ipmmu-r8a77961",
982 .compatible = "renesas,ipmmu-r8a77965",
985 .compatible = "renesas,ipmmu-r8a77970",
988 .compatible = "renesas,ipmmu-r8a77990",
991 .compatible = "renesas,ipmmu-r8a77995",
1005 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); in ipmmu_probe()
1007 dev_err(&pdev->dev, "cannot allocate device data\n"); in ipmmu_probe()
1008 return -ENOMEM; in ipmmu_probe()
1011 mmu->dev = &pdev->dev; in ipmmu_probe()
1012 spin_lock_init(&mmu->lock); in ipmmu_probe()
1013 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); in ipmmu_probe()
1014 mmu->features = of_device_get_match_data(&pdev->dev); in ipmmu_probe()
1015 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); in ipmmu_probe()
1016 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); in ipmmu_probe()
1020 mmu->base = devm_ioremap_resource(&pdev->dev, res); in ipmmu_probe()
1021 if (IS_ERR(mmu->base)) in ipmmu_probe()
1022 return PTR_ERR(mmu->base); in ipmmu_probe()
1025 * The IPMMU has two register banks, for secure and non-secure modes. in ipmmu_probe()
1027 * corresponds to the running mode of the CPU. When running in secure in ipmmu_probe()
1028 * mode the non-secure register bank is also available at an offset. in ipmmu_probe()
1030 * Secure mode operation isn't clearly documented and is thus currently in ipmmu_probe()
1032 * non-secure operation with the main register bank were not successful. in ipmmu_probe()
1033 * Offset the registers base unconditionally to point to the non-secure in ipmmu_probe()
1036 if (mmu->features->use_ns_alias_offset) in ipmmu_probe()
1037 mmu->base += IM_NS_ALIAS_OFFSET; in ipmmu_probe()
1039 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); in ipmmu_probe()
1043 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. in ipmmu_probe()
1045 if (!mmu->features->has_cache_leaf_nodes || in ipmmu_probe()
1046 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) in ipmmu_probe()
1047 mmu->root = mmu; in ipmmu_probe()
1049 mmu->root = ipmmu_find_root(); in ipmmu_probe()
1054 if (!mmu->root) in ipmmu_probe()
1055 return -EPROBE_DEFER; in ipmmu_probe()
1063 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, in ipmmu_probe()
1064 dev_name(&pdev->dev), mmu); in ipmmu_probe()
1066 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); in ipmmu_probe()
1072 if (mmu->features->reserved_context) { in ipmmu_probe()
1073 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); in ipmmu_probe()
1074 set_bit(0, mmu->ctx); in ipmmu_probe()
1080 * - R-Car Gen2 IPMMU (all devices registered) in ipmmu_probe()
1081 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) in ipmmu_probe()
1083 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { in ipmmu_probe()
1084 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, in ipmmu_probe()
1085 dev_name(&pdev->dev)); in ipmmu_probe()
1089 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops); in ipmmu_probe()
1090 iommu_device_set_fwnode(&mmu->iommu, in ipmmu_probe()
1091 &pdev->dev.of_node->fwnode); in ipmmu_probe()
1093 ret = iommu_device_register(&mmu->iommu); in ipmmu_probe()
1118 iommu_device_sysfs_remove(&mmu->iommu); in ipmmu_remove()
1119 iommu_device_unregister(&mmu->iommu); in ipmmu_remove()
1121 arm_iommu_release_mapping(mmu->mapping); in ipmmu_remove()
1138 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_resume_noirq()
1139 if (!mmu->domains[i]) in ipmmu_resume_noirq()
1142 ipmmu_domain_setup_context(mmu->domains[i]); in ipmmu_resume_noirq()
1146 /* Re-enable active micro-TLBs */ in ipmmu_resume_noirq()
1147 for (i = 0; i < mmu->features->num_utlbs; i++) { in ipmmu_resume_noirq()
1148 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) in ipmmu_resume_noirq()
1151 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); in ipmmu_resume_noirq()
1167 .name = "ipmmu-vmsa",