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/linux-6.15/Documentation/devicetree/bindings/pwm/
Dpwm-nexus-node.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-nexus-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM Nexus node properties
19 - Herve Codina <herve.codina@bootlin.com>
24 '#pwm-cells': true
26 pwm-map:
27 $ref: /schemas/types.yaml#/definitions/uint32-matrix
29 pwm-map-mask:
[all …]
/linux-6.15/drivers/gpio/
Dgpio-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
[all …]
/linux-6.15/drivers/pwm/
Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
28 struct regmap *map; member
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
40 u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2); in jz4740_pwm_can_use_chn()
42 device_property_read_u32(pwmchip_parent(chip)->parent, in jz4740_pwm_can_use_chn()
[all …]
Dpwm-stm32.c1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
17 #include <linux/pwm.h>
30 struct mutex lock; /* protect pwm config/enable */
49 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
62 struct pwm_device *pwm, in stm32_pwm_round_waveform_tohw() argument
68 unsigned int ch = pwm->hwpwm; in stm32_pwm_round_waveform_tohw()
73 if (wf->period_length_ns == 0) { in stm32_pwm_round_waveform_tohw()
[all …]
/linux-6.15/drivers/hwmon/
Dmlxreg-fan.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
[all …]
/linux-6.15/arch/arm/boot/dts/marvell/
Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
/linux-6.15/drivers/pinctrl/
Dpinctrl-th1520.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
115 [TH1520_MUX_PWM] = "pwm",
284 TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
285 TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
286 TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
287 TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
[all …]
/linux-6.15/drivers/clocksource/
Dsamsung_pwm_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * samsung - Common hr-timer support (s3c and s5p)
79 static struct samsung_pwm_clocksource pwm; variable
92 reg = readl(pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
94 reg |= (prescale - 1) << shift; in samsung_timer_set_prescale()
95 writel(reg, pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
107 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
111 reg = readl(pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
114 writel(reg, pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
129 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_stop()
[all …]
Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
40 struct regmap *map; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
83 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel)); in ingenic_tcu_cevt_set_state_shutdown()
95 return -EINVAL; in ingenic_tcu_cevt_set_next()
97 regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next); in ingenic_tcu_cevt_set_next()
98 regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0); in ingenic_tcu_cevt_set_next()
[all …]
/linux-6.15/drivers/leds/rgb/
Dleds-qcom-lpg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2022 Linaro Ltd
4 * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/led-class-multicolor.h>
11 #include <linux/nvmem-consumer.h>
14 #include <linux/pwm.h>
17 #include <linux/soc/qcom/qcom-pbs.h>
43 #define PWM_DTEST_REG(x) (0xe2 + (x) - 1)
87 * struct lpg - LPG device context
[all …]
/linux-6.15/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.15/arch/riscv/boot/dts/microchip/
Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
8 core_pwm0: pwm@40000000 {
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/linux-6.15/arch/mips/boot/dts/brcm/
Dbcm7358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
[all …]
Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/linux-6.15/arch/arm/boot/dts/nxp/ls/
Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
[all …]
/linux-6.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/linux-6.15/arch/arm/boot/dts/broadcom/
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
/linux-6.15/arch/arm/boot/dts/intel/ixp/
Dintel-ixp42x-linksys-nslu2.dts1 // SPDX-License-Identifier: ISC
6 /dts-v1/;
8 #include "intel-ixp42x.dtsi"
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
25 stdout-path = "uart0:115200n8";
33 compatible = "gpio-leds";
34 led-status {
37 default-state = "on";
[all …]
/linux-6.15/drivers/leds/
Dleds-lp5562.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/platform_data/leds-lp55xx.h>
21 #include "leds-lp55xx-common.h"
32 #define LP5562_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
108 led->led_current = led_current; in lp5562_set_led_current()
109 lp55xx_write(led->chip, addr[led->chan_nr], led_current); in lp5562_set_led_current()
152 /* Initialize all channels PWM to zero -> leds off */ in lp5562_post_init_device()
158 /* Set LED map as register PWM by default */ in lp5562_post_init_device()
166 struct lp55xx_chip *chip = led->chip; in lp5562_multicolor_brightness()
176 guard(mutex)(&chip->lock); in lp5562_multicolor_brightness()
[all …]
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt7988a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
7 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
[all …]

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